DE102014014420A1 - Kombiniertes Waferherstellungsverfahren mit einer Mehrkomponentenaufnahmeschicht - Google Patents

Kombiniertes Waferherstellungsverfahren mit einer Mehrkomponentenaufnahmeschicht Download PDF

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Publication number
DE102014014420A1
DE102014014420A1 DE102014014420.8A DE102014014420A DE102014014420A1 DE 102014014420 A1 DE102014014420 A1 DE 102014014420A1 DE 102014014420 A DE102014014420 A DE 102014014420A DE 102014014420 A1 DE102014014420 A1 DE 102014014420A1
Authority
DE
Germany
Prior art keywords
solid
layer
polymer
receiving layer
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE102014014420.8A
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German (de)
English (en)
Inventor
Jan Richter
Christian Beyer
Anas Ajaj
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siltectra GmbH
Original Assignee
Siltectra GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siltectra GmbH filed Critical Siltectra GmbH
Priority to DE102014014420.8A priority Critical patent/DE102014014420A1/de
Priority to US15/515,480 priority patent/US10707068B2/en
Priority to EP15767168.6A priority patent/EP3201944B1/fr
Priority to PCT/EP2015/071949 priority patent/WO2016050597A1/fr
Publication of DE102014014420A1 publication Critical patent/DE102014014420A1/de
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H01L21/0201—Specific process step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
DE102014014420.8A 2014-09-29 2014-09-29 Kombiniertes Waferherstellungsverfahren mit einer Mehrkomponentenaufnahmeschicht Pending DE102014014420A1 (de)

Priority Applications (4)

Application Number Priority Date Filing Date Title
DE102014014420.8A DE102014014420A1 (de) 2014-09-29 2014-09-29 Kombiniertes Waferherstellungsverfahren mit einer Mehrkomponentenaufnahmeschicht
US15/515,480 US10707068B2 (en) 2014-09-29 2015-09-24 Combined wafer production method with a multi-component receiving layer
EP15767168.6A EP3201944B1 (fr) 2014-09-29 2015-09-24 Procédé combiné de fabrication de tranches au moyen d'une couche réceptrice à plusieurs constituants
PCT/EP2015/071949 WO2016050597A1 (fr) 2014-09-29 2015-09-24 Procédé combiné de fabrication de tranches au moyen d'une couche réceptrice à plusieurs constituants

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102014014420.8A DE102014014420A1 (de) 2014-09-29 2014-09-29 Kombiniertes Waferherstellungsverfahren mit einer Mehrkomponentenaufnahmeschicht

Publications (1)

Publication Number Publication Date
DE102014014420A1 true DE102014014420A1 (de) 2016-04-14

Family

ID=54151292

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102014014420.8A Pending DE102014014420A1 (de) 2014-09-29 2014-09-29 Kombiniertes Waferherstellungsverfahren mit einer Mehrkomponentenaufnahmeschicht

Country Status (4)

Country Link
US (1) US10707068B2 (fr)
EP (1) EP3201944B1 (fr)
DE (1) DE102014014420A1 (fr)
WO (1) WO2016050597A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3542222B1 (fr) * 2017-03-28 2020-10-07 HP Indigo B.V. Encre(s) électrostatique(s)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080012140A1 (en) 2006-07-14 2008-01-17 Nec Electronics Corporation Wiring substrate, semiconductor device, and method of manufacturing the same
WO2013113730A1 (fr) 2012-01-30 2013-08-08 Siltectra Gmbh Procédé de production de plaques minces en matières de faible ductilité, au moyen de contraintes mécaniques induites par la température, en utilisant des films de polymère préfabriqués
DE102014013107A1 (de) 2013-10-08 2015-04-09 Siltectra Gmbh Neuartiges Waferherstellungsverfahren

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8440129B2 (en) * 2007-11-02 2013-05-14 President And Fellows Of Harvard College Production of free-standing solid state layers by thermal processing of substrates with a polymer
FR2925221B1 (fr) 2007-12-17 2010-02-19 Commissariat Energie Atomique Procede de transfert d'une couche mince
EP2105972A3 (fr) * 2008-03-28 2015-06-10 Semiconductor Energy Laboratory Co, Ltd. Dispositif de conversion photoélectrique et procédé de fabrication de celui-ci
EP2620409B1 (fr) * 2008-12-23 2017-03-01 Siltectra GmbH Procédé de production de minces couches libres de matériaux à l'état solide avec des surfaces structurées

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080012140A1 (en) 2006-07-14 2008-01-17 Nec Electronics Corporation Wiring substrate, semiconductor device, and method of manufacturing the same
WO2013113730A1 (fr) 2012-01-30 2013-08-08 Siltectra Gmbh Procédé de production de plaques minces en matières de faible ductilité, au moyen de contraintes mécaniques induites par la température, en utilisant des films de polymère préfabriqués
DE102014013107A1 (de) 2013-10-08 2015-04-09 Siltectra Gmbh Neuartiges Waferherstellungsverfahren

Also Published As

Publication number Publication date
US10707068B2 (en) 2020-07-07
US20180233347A1 (en) 2018-08-16
EP3201944B1 (fr) 2022-12-21
WO2016050597A1 (fr) 2016-04-07
EP3201944A1 (fr) 2017-08-09

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