DE102014003659A1 - Systeme, vorrichtungen und verfahren zum bestimmen eines folgenden niedrigstwertigen maskierungsbits eines schreibmaskenregisters - Google Patents
Systeme, vorrichtungen und verfahren zum bestimmen eines folgenden niedrigstwertigen maskierungsbits eines schreibmaskenregisters Download PDFInfo
- Publication number
- DE102014003659A1 DE102014003659A1 DE102014003659.6A DE102014003659A DE102014003659A1 DE 102014003659 A1 DE102014003659 A1 DE 102014003659A1 DE 102014003659 A DE102014003659 A DE 102014003659A DE 102014003659 A1 DE102014003659 A1 DE 102014003659A1
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- Prior art keywords
- write mask
- bit position
- source
- zero
- operand
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Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
- G06F9/30152—Determining start or end of instruction; determining instruction length
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30018—Bit or string instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
- G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Complex Calculations (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/840,809 | 2013-03-15 | ||
| US13/840,809 US9323531B2 (en) | 2013-03-15 | 2013-03-15 | Systems, apparatuses, and methods for determining a trailing least significant masking bit of a writemask register |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE102014003659A1 true DE102014003659A1 (de) | 2014-09-18 |
Family
ID=50554642
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE102014003659.6A Withdrawn DE102014003659A1 (de) | 2013-03-15 | 2014-03-14 | Systeme, vorrichtungen und verfahren zum bestimmen eines folgenden niedrigstwertigen maskierungsbits eines schreibmaskenregisters |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US9323531B2 (pt) |
| JP (1) | JP5806748B2 (pt) |
| KR (1) | KR101624786B1 (pt) |
| CN (1) | CN104049946A (pt) |
| BR (1) | BR102014006118A2 (pt) |
| DE (1) | DE102014003659A1 (pt) |
| GB (1) | GB2513467B (pt) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107220027A (zh) * | 2011-12-23 | 2017-09-29 | 英特尔公司 | 用于执行掩码位压缩的系统、装置以及方法 |
| US10387150B2 (en) | 2015-06-24 | 2019-08-20 | International Business Machines Corporation | Instructions to count contiguous register elements having a specific value in a selected location |
| US10162603B2 (en) * | 2016-09-10 | 2018-12-25 | Sap Se | Loading data for iterative evaluation through SIMD registers |
| WO2019005165A1 (en) | 2017-06-30 | 2019-01-03 | Intel Corporation | METHOD AND APPARATUS FOR VECTORIZING INDIRECT UPDATING BUCKLES |
| KR101999006B1 (ko) | 2017-09-11 | 2019-07-11 | 중앙대학교 산학협력단 | 세균성 벼흰잎마름병균의 OprXBo 단백질 및 이의 용도 |
| US11853757B2 (en) * | 2020-03-06 | 2023-12-26 | Intel Corporation | Vectorization of loops based on vector masks and vector count distances |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5207132A (en) | 1991-10-16 | 1993-05-04 | Textron Inc. | Elliptical lobed drive system |
| US5446912A (en) | 1993-09-30 | 1995-08-29 | Intel Corporation | Partial width stalls within register alias table |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2636075B2 (ja) * | 1990-11-16 | 1997-07-30 | 甲府日本電気株式会社 | ベクトル処理装置 |
| US5651121A (en) * | 1992-12-18 | 1997-07-22 | Xerox Corporation | Using mask operand obtained from composite operand to perform logic operation in parallel with composite operand |
| US7129864B2 (en) * | 2004-12-31 | 2006-10-31 | Intel Corporation | Fast compact decoder for huffman codes |
| US8209525B2 (en) | 2008-08-15 | 2012-06-26 | Apple Inc. | Method and apparatus for executing program code |
| US8793472B2 (en) | 2008-08-15 | 2014-07-29 | Apple Inc. | Vector index instruction for generating a result vector with incremental values based on a start value and an increment value |
| US7966523B2 (en) * | 2008-08-21 | 2011-06-21 | Rockwell Automation Technologies, Inc. | Industrial automation and information solutions having industry specific modalities |
| US8667042B2 (en) * | 2010-09-24 | 2014-03-04 | Intel Corporation | Functional unit for vector integer multiply add instruction |
| US9092213B2 (en) * | 2010-09-24 | 2015-07-28 | Intel Corporation | Functional unit for vector leading zeroes, vector trailing zeroes, vector operand 1s count and vector parity calculation |
| US8972701B2 (en) * | 2011-12-06 | 2015-03-03 | Arm Limited | Setting zero bits in architectural register for storing destination operand of smaller size based on corresponding zero flag attached to renamed physical register |
| US9703558B2 (en) * | 2011-12-23 | 2017-07-11 | Intel Corporation | Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate |
| EP2798478A4 (en) | 2011-12-30 | 2016-12-21 | Intel Corp | EFFICIENT DECOMPRESSION BASED ON ZERO |
| US9116686B2 (en) * | 2012-04-02 | 2015-08-25 | Apple Inc. | Selective suppression of branch prediction in vector partitioning loops until dependency vector is available for predicate generating instruction |
-
2013
- 2013-03-15 US US13/840,809 patent/US9323531B2/en not_active Expired - Fee Related
-
2014
- 2014-02-18 JP JP2014028431A patent/JP5806748B2/ja not_active Expired - Fee Related
- 2014-03-06 GB GB1403993.7A patent/GB2513467B/en not_active Expired - Fee Related
- 2014-03-14 KR KR1020140030541A patent/KR101624786B1/ko active IP Right Grant
- 2014-03-14 BR BR102014006118A patent/BR102014006118A2/pt not_active Application Discontinuation
- 2014-03-14 DE DE102014003659.6A patent/DE102014003659A1/de not_active Withdrawn
- 2014-03-17 CN CN201410097430.XA patent/CN104049946A/zh active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5207132A (en) | 1991-10-16 | 1993-05-04 | Textron Inc. | Elliptical lobed drive system |
| US5446912A (en) | 1993-09-30 | 1995-08-29 | Intel Corporation | Partial width stalls within register alias table |
Also Published As
| Publication number | Publication date |
|---|---|
| KR101624786B1 (ko) | 2016-05-26 |
| GB201403993D0 (en) | 2014-04-23 |
| GB2513467A (en) | 2014-10-29 |
| BR102014006118A2 (pt) | 2015-10-20 |
| US20140281401A1 (en) | 2014-09-18 |
| US9323531B2 (en) | 2016-04-26 |
| JP2014182796A (ja) | 2014-09-29 |
| KR20140113555A (ko) | 2014-09-24 |
| CN104049946A (zh) | 2014-09-17 |
| GB2513467B (en) | 2015-11-04 |
| JP5806748B2 (ja) | 2015-11-10 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R012 | Request for examination validly filed | ||
| R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |