DE102013210146A1 - SEMICONDUCTOR POWER MODULE ARRANGEMENT - Google Patents

Abstract

The invention relates to a semiconductor module arrangement and a method for its operation. The semiconductor module assembly comprises a main substrate (3) having an insulating support (30) provided with a patterned metallization layer (31) and having first and second metallization sections (311, 312). On the first metallization section (311), a first sub-substrate (1) is arranged which has a first insulation carrier (10) and a first upper metallization layer (11). Disposed on the second contiguous metallization section (312) is a second sub-substrate (2) having a second isolation support (20), a second top metallization layer (21), and a second bottom metallization layer (22) disposed on an underside of the second isolation support (20) is applied. A first controllable semiconductor chip (6) having a first load terminal (61) and a control terminal (63) facing away from one of the first upper metallization layer (11) is arranged on a first section (111) of the first upper metallization layer (11) Top of the first semiconductor chip (6) are arranged, and a second load terminal (62) which is arranged on an underside of the first semiconductor chip (6). On a first section (211) of the second upper metallization layer (21), a second controllable semiconductor chip (7) is arranged, which has a first load terminal (71) and a control terminal (73) arranged on an upper side of the second semiconductor chip (7) and a second load terminal (72) disposed on an underside of the second semiconductor chip (7). The first contiguous metallization section (311) has a first base area (A311). The second contiguous metallization section (312) has a second footprint (A312) that is less than 1 / 0.95 times the first footprint (A311) and greater than 1 / 1.05 times the first footprint (A311 ).

Description

In the operation of power semiconductor modules with at least two power semiconductor chips occurs due to unavoidable inductances and capacitances for the formation of interference currents on the one hand in the same direction ("common mode currents" or "common mode currents") and on the other hand in opposite directions ("differential mode currents" or "push-pull currents") train the power electronic device. Both types of interference currents are the cause of the on the one hand conducted and on the other hand radiated emissions of a converter device.

A significant influencing factor is, for example, the size of the output capacitance that exists between an output of the power semiconductor module and ground. Typically, the output capacitance is determined very significantly by the size of a metallization surface of a printed circuit board, which is based on the electrical potential of the relevant output. In order to keep the caused by the output capacitance fraction of the interference, it is generally desirable to make the output capacitance as low as possible. The same applies to the capacitances between ground and metallization surfaces, which are at a positive or negative electrical potential, for. B. to the electrical power supply of the semiconductor module, are.

When the load paths of the two power semiconductor chips are electrically connected in series to a half-bridge, the series connection between the load paths has a circuit node which is usually at the electrical potential of the output. The power semiconductor chip connected to a positive supply potential of the half-bridge is then often referred to as a "high-side chip", the power semiconductor chip connected to a negative supply potential of the half-bridge accordingly as a "low-side chip". If, in a first switching state, the high-side chip conducts and the low-side chip blocks, the circuit node is essentially at the positive supply potential. Conversely, in a second switching state, if the high-side chip blocks and the low-side chip conducts, the circuit node is essentially at the negative supply potential. Thus, either a positive or a negative supply potential can be supplied to the output by a suitable control of the power semiconductor chips. When changing from the first to the second switching state or from the second to the first switching state occurs in the system with the half-bridge and connected to the half-bridge intermediate circuit capacitor including the associated connecting lines, depending on the symmetry of the system, to form unavoidable DC and balanced currents (im The following interference currents) which can also influence one another and consequently result in the emission of interfering emissions.

Another influencing factor is the metallization of printed circuit boards, which are based on the electrical potential of control terminals such as gate or base of the power semiconductor chips. Together with ground planes, these also form capacitances which lead to interference currents and, consequently, to the emission of interfering emissions. While a metallization surface located on the electrical potential of the control terminal of a low-side semiconductor chip can achieve an improvement by the geometry of this metallization surface to a certain extent, a metallization surface lying on the electrical potential of the control terminal of a high-side semiconductor chip can substantially only by reducing the size of this metallization area an improvement can be achieved.

In some module designs, a reduction in the emission of spurious emissions can be achieved through the use of a p-channel type power semiconductor chip, but have higher on-resistance than n-channel types, which is also undesirable.

Other module designs provide for the use of power semiconductor chips in flip-chip mounting technique, i. the relevant power semiconductor chip is mounted on a printed circuit board such that the control terminal and a load terminal are located on the side of the power semiconductor chip facing the printed circuit board. Although this makes it possible to realize short control connection lines, such a mounting technique is very complicated and involves disadvantages in chip heating.

The object of the invention is to provide a power semiconductor module arrangement which emits little interference emissions during operation, and a method for operating such a power semiconductor module arrangement. This object is achieved by power semiconductor module arrangements according to claims 1 and 12 or by a method for operating a semiconductor module arrangement according to claim 19. Embodiments and developments of the invention are the subject of dependent claims.

A power semiconductor module assembly according to the present invention comprises a main substrate having an insulating support having an upper surface to which a patterned metallization layer is applied. This points a first contiguous metallization section and a second contiguous metallization section separated therefrom.

A first sub-substrate is disposed on a first portion of the first contiguous metallization section. This has a first insulating support, as well as a first upper metallization. The first upper metallization layer is applied to an upper side of the first insulation carrier facing away from the first contiguous metallization section.

Correspondingly, a second sub-substrate is arranged on a first section of the second contiguous metallization section. This has a second insulating support, and a second upper metallization. The second upper metallization layer is applied to an upper side of the second insulation carrier facing away from the second contiguous metallization section.

Furthermore, a first controllable semiconductor chip is arranged on the first upper metallization layer. This has a first load terminal and a control terminal, which are both disposed on an upper side of the first controllable semiconductor chip facing away from the first upper metallization layer, and a second load terminal which is arranged on an underside of the first controllable semiconductor chip facing the first upper metallization layer.

Accordingly, a second controllable semiconductor chip is arranged on the second upper metallization layer. This likewise has a first load connection and a control connection, both of which are arranged on an upper side of the second controllable semiconductor chip remote from the second upper metallization layer, and a second load connection, which is arranged on an underside of the second controllable semiconductor chip facing the second upper metallization layer.

The first contiguous metallization section has a first and the second contiguous metallization section has a second base area. The second footprint is less than 1 / 0.95 times the first footprint and greater than 1 / 1.05 times the first footprint.

In the context of the present invention, the base area of a metallization or of a metallization section is considered to be the largest area that it possesses on a plane in the case of an orthogonal projection.

A further aspect of the invention relates to a semiconductor module arrangement having a number N1 ≥ 1 of first metallization sections, which are galvanically connected together in the case of N 1> 1. Each of these first metallization sections is designed as a thin metallization layer and has a base area. The total sum of all these bases results in a first base area. The semiconductor module arrangement furthermore has a number N 2 ≥ 1 of second metallization sections, which are galvanically connected together in the case of N 2> 1. Each of these second metallization sections is designed as a thin metallization layer and has a base area. The total sum of all these footprints results in a second footprint that is less than 1 / 0.95 times the first footprint and greater than 1 / 1.05 times the first footprint.

Furthermore, the semiconductor module arrangement contains a first controllable semiconductor chip and a second controllable semiconductor chip, each of which has a first load terminal, a second load terminal and a control terminal.

The first load terminal and the control terminal of the first semiconductor chip are arranged on top of the first controllable semiconductor chip, while the second load terminal of the first semiconductor chip is located on its underside facing away from the top. Accordingly, the first load terminal and the control terminal of the second semiconductor chip are arranged on the upper side of the second controllable semiconductor chip, while the second load terminal of the second semiconductor chip is located on its underside facing away from the upper side. The first and the second semiconductor chip are interconnected to form a half-bridge by the first load terminal of the first controllable semiconductor chip and the second load terminal of the second controllable semiconductor chip are galvanically connected together.

Furthermore, the second load connection of the first controllable semiconductor chip is galvanically connected to the first metallization sections, and the first load connection of the second controllable semiconductor chip is galvanically connected to the second metallization sections.

Since the size of the first base area and the second base area are not or only slightly different in size, the emission of interference emissions occurring during operation of the semiconductor module arrangement can be significantly reduced compared to conventional arrangements. By choosing similarly sized first and second base areas, it can be achieved that the entirety of the N1 first metallization sections has a first capacitance relative to the electrical ground element, and the entirety of the N2 second metallization sections opposite the electrical ground element has a second capacitance less than 1/95 times the first capacitance and greater than 1/105 times the first capacitance.

In the method for operating one of the semiconductor module arrangements described above, a first electrical supply potential is applied to the second load terminal of the first controllable semiconductor chip, and a second electrical supply potential different from the first electrical supply potential is applied to the first load terminal of the second controllable semiconductor chip.

The invention will be explained below with reference to embodiments with reference to the accompanying figures. In the figures, like reference numerals designate like elements. Show it:

1 a vertical section through a power semiconductor module;

2 a plan view of the power semiconductor module according to 1 ;

3 a vertical section through a power semiconductor module, the structure of the power semiconductor module according to the 1 and 2 corresponds, however, additionally having an optional housing and which is mounted on a heat sink;

4 an equivalent circuit diagram of a based on the 1 to 3 explained semiconductor module;

5 a section of the basis of the 1 to 3 explained semiconductor module;

6 two individual semiconductor modules, each with a semiconductor switch;

7 the two in 6 shown and arranged on a common heat sink semiconductor modules; and

8th two arranged on a common heat sink semiconductor modules, each of which has a structure like that of the 1 to 3 explained semiconductor module.

In order to clarify the respective structure, the arrangements shown in the figures are not shown to scale.

1 shows a power semiconductor module 100 in vertical section and 2 in plan view. The section plane EE according to the view 1 is in 2 shown. The power semiconductor module 100 comprises a main substrate 3 with an electrically insulating support 30 , an upper metallization layer 31 , as well as an optional lower metallization layer 32 , The upper metallization layer 31 is on a top 30t of the insulating support 30 applied, the lower metallization layer 32 on one of the top opposite bottom 30b of the insulating support 30 , The upper metallization layer 31 and the lower metallization layer 32 are through the electrically insulating support 30 electrically isolated from each other.

3 shows this semiconductor module 100 after mounting on a heat sink 9 , By the insulating carrier 30 are the heat sink 9 and the upper metallization layer 31 electrically isolated from each other.

To the thermal contact resistance between the heat sink 9 and the main substrate 3 can reduce, between this and the heat sink 9 a thermal grease is introduced, which both the heat sink 9 as well as the main substrate 3 contacted over a large area.

Furthermore, an optional housing 8th provided in which the semiconductor chips 6 . 7 are arranged. The housing 8th is only schematically represents. It may, for example, consist of an electrically insulating, for example thermosetting or thermoplastic, plastic. Optionally, it may have one or more mounting openings, and / or one or more mounting flanges, with which the semiconductor module 100 for example on the heat sink 9 can be attached.

The upper metallization layer 31 is structured and has a first contiguous metallization section 311 and a second contiguous metallization section separated therefrom 312 , For the purposes of the present application, "separated" means that the upper metallization layer 31 has no section containing the two metallization sections 311 and 312 permanently galvanically connected to each other. Mathematically speaking, the two metallization sections 311 and 312 within the metallization layer 31 not connected.

Between the two metallization sections 311 and 312 There is also no permanent, low-resistance galvanic electrical connection. An electrical connection of the two metallization sections 311 and 312 by at least temporarily switched off (high-resistance) semiconductor components (here the semiconductor chips 6 and 7 ) is not considered "permanent" for the purposes of the present invention. A "low-resistance galvanic connection" between the two metallization sections 311 and 312 For example, if if between the two metallization sections 311 and 312 permanently ohmic resistance of less than 1 ohm vorläge. These definitions apply not only to the present embodiment, but for all possible embodiments of the invention.

On the first continuous metallization section 311 is a first sub-substrate 1 arranged on the second contiguous Metallisierungsabschnitt 312 a second sub-substrate 2 ,

The first sub-substrate 1 has a first insulating support 10 on, a first upper metallization layer 11 , as well as an optional first lower metallization layer 12 , The first upper metallization layer 11 is on a first contiguous metallization section 311 remote from the top of the first insulation carrier 10 applied, the first lower metallization layer 12 to a first contiguous metallization section 311 facing bottom of the first insulation carrier 10 , The first upper metallization layer 11 has a first section 111 and a second section 112 on.

Accordingly, the second sub-substrate 2 a second insulation carrier 20 on, a second upper metallization layer 21 , as well as an optional second lower metallization layer 22 , The second upper metallization layer 21 is on a second contiguous metallization section 312 remote top side of the second insulation carrier 20 applied, the second lower metallization layer 22 to a second contiguous metallization section 312 facing bottom of the second insulation carrier 20 , The second upper metallization layer 12 has a first section 211 and a second section 212 on.

The electrically insulating carrier 30 , the first insulation carrier 10 and the second insulation carrier 20 each consist of an electrically insulating material, wherein the different carriers 10 . 20 . 30 can consist of the same material, but also of any different materials. Well suited, for example, electrically insulating ceramics, eg. For example, alumina (Al2O3), aluminum nitride (AlN), beryllium oxide (BeO), zirconium oxide (ZrO2), silicon nitride (Si3N4), but also other ceramics. The metallization layers 11 . 12 . 21 . 22 . 31 and 32 consist of electrically highly conductive materials, such as copper, or copper alloys, aluminum or aluminum alloys. The electrical conductivity of the metallization layers 11 . 12 . 21 . 22 . 31 and 32 is preferably more than 35 MS / m (Mega-Siemens per meter) at a temperature of 300 K, more preferably more than 55 MS / m.

In the carrier substrate 3 are the upper metallization layer 31 and, if present, the optional lower metallization layer 32 directly on the insulation carrier 30 applied. Accordingly, in the first sub-substrate 1 are the first upper metallization layer 11 and, if present, the optional first lower metallization layer 12 directly on the first insulation support 10 applied, and in the second sub-substrate 2 are the second upper metallization layer 21 and, if present, the optional second lower metallization layer 22 directly on the second insulation carrier 20 applied.

The first sub-substrate 1 is at the first lower metallization layer 12 by means of a bonding layer 41 electrically conductive and mechanically connected to the first contiguous metallization section 311 connected. The connection layer 41 contacts both the first lower metallization layer 12 as well as the first contiguous metallization section 311 ,

Accordingly, the second sub-substrate 2 at the second lower metallization layer 22 by means of a bonding layer 42 electrically conductive and mechanically connected to the second contiguous metallization section 312 connected. The connection layer 42 contacts both the second lower metallization layer 22 as well as the second contiguous metallization section 312 ,

The connecting layers 41 . 42 can be formed independently of one another and any desired combinations with one another, for example as solder layers or as sintered compound layers. For the purposes of the present invention, "layers of sintering compounds" are considered to be layers which connect two elements to one another and which have been produced by sintering a metal powder. Such sintered compound layers are electrically conductive, which is why they are equally suitable for the production of electrically conductive and high-strength mechanical connections.

The connecting layers 41 and 42 For example, both may be formed as solder layers or both as sintered compound layers. Likewise, however, any of the two connecting layers can also be used 41 . 42 as a layer of solder and the other 42 . 41 be formed as a sintered compound layer.

If the first sub-substrate 1 no first lower metallization layer 12 may be on the tie layer 41 be waived. Instead, the first insulation support 10 directly on the first contiguous metallization section 311 applied and thus firmly with be connected to this. Accordingly, in the second sub-substrate 2 if this does not have a second lower metallization layer 22 has, on the connection layer 42 be waived. Instead, the second insulation support 20 directly on the second continuous metallization section 312 applied and thereby be firmly connected to this.

On the first section 111 the first upper metallization layer 11 is a first controllable semiconductor chip 6 arranged. This has a first load connection 61 and a control terminal 63 on, both at one of the section 111 remote top side of the first controllable semiconductor chip 6 are arranged. A second load connection 62 of the first controllable semiconductor chip 6 is at one of the section 111 facing bottom of the first controllable semiconductor chip 6 arranged.

Accordingly, on the first section 211 the second upper metallization layer 12 a second controllable semiconductor chip 7 arranged. This also has a first load connection 71 and a control terminal 73 on, both at one of the section 211 remote top side of the second controllable semiconductor chip 7 are arranged. There is also a second load connection 72 of the second controllable semiconductor chip 7 at one of the section 211 facing bottom of the second controllable semiconductor chip 7 arranged.

For the purposes of the present invention, the load or control connections are terminal contacts of the relevant semiconductor chip 6 . 7 considered, the electrical contacting of the semiconductor chip 6 . 7 are freely accessible. At the present load and control connections 61 . 62 . 63 . 71 . 72 . 73 For example, each may be a planar contact metallization of the relevant semiconductor chip 6 . 7 act. At the load connections 61 / 62 For example, it may be drain / source, source / drain, emitter / collector, collector / emitter, anode / cathode, or cathode / anode at the control port 63 around gate or base. Regardless, it may be at the load ports 71 / 72 for example, drain / source, source / drain, emitter / collector, collector / emitter, anode / cathode or cathode / anode, and at the control terminal 73 around gate or base.

The semiconductor chips 6 and 7 are not in flip-chip technology on the respective sub-substrates 1 respectively. 2 assembled. Rather, each of the semiconductor chips 1 and 2 at its the main substrate 3 facing side no more than an electrical connection. In the semiconductor chip 6 this is its second load connection 62 , in the semiconductor chip 7 its second load connection 72 ,

Optionally, the semiconductor chips 6 and or 7 be designed as so-called "vertical" semiconductor chips, ie as semiconductor chips 6 . 7 whose semiconductor body has a drift zone in which a load current, ie the current between the load terminals 61 and 62 or between the load connections 71 and 72 , substantially between two opposite sides of the semiconductor chip 6 respectively. 7 runs.

The first semiconductor chip 6 is at its second load port 62 by means of a bonding layer 43 electrically conductive and mechanical with the section 111 the first upper metallization layer 11 connected. The connection layer 43 contacts both the second load connection 62 as well as the section 111 , Accordingly, the second semiconductor chip 7 at its second load connection 72 by means of a bonding layer 44 electrically conductive and mechanical with the section 211 the second upper metallization layer 21 connected. The connection layer 44 contacts both the second load connection 72 as well as the section 211 ,

The semiconductor chips 6 . 7 can, independently of each other and in any combination with each other, each having an electrical component. Suitable is, for example, any type of bipolar or unipolar transistor, such as insulated gate field effect transistor (IGFET), a JFET, thyristors, but also any other electrical power devices. Suitable IGFETs are, for example, MOSFETs or IGBTs, but also all other types of IGFETs. Optionally, the first and the second controllable semiconductor chip 6 respectively. 7 be of the same type. In particular, they may also be identical in the sense that they are constructed identically within the scope of usual manufacturing tolerances and therefore have substantially identical electrical properties.

By applying suitable control signals to the control terminals 63 respectively. 73 the semiconductor chips 6 respectively. 7 can be a load path between the two load ports 61 and 62 respectively. 71 and 72 of the relevant semiconductor chip 6 respectively. 7 is formed to be placed in an electrically conductive, an electrically blocking or a state therebetween. The two semiconductor chips 6 . 7 are connected in a half-bridge by their load paths are electrically connected in series. For this purpose, the first load connection 61 of the first semiconductor chip 6 low-resistance electrically conductive with the second load connection 72 of the second semiconductor chip 7 connected. The corresponding electrical connection is made via one or more bonding wires 53 , each of which is connected both to the first load connection 61 as well as the second upper metallization layer 21 is bonded, as well as the second upper metallization 21 and the second connection layer 44 ,

Alternatively or in addition to the one or more bonding wires 53 However, other electrical connection techniques may be used, for example, one or more flat tapes, each by wire bonding both to the first load terminal 61 as well as the second upper metallization layer 21 are bonded, or one or more angled shaped sheets, each directly adjacent to both the first load port 61 as well as the second upper metallization layer 21 are soldered.

The power supply of the half-bridge takes place via the first contiguous metallization section 311 and the second continuous metallization section 312 , In the embodiment shown, the first semiconductor chip 6 the high-side chip and the second semiconductor chip 7 Therefore, during operation of the semiconductor module 100 the second load connection 62 of the first semiconductor chip 6 to a positive supply potential DC + and the first load connection 61 of the second semiconductor chip 7 connected to a negative supply potential DC-, which is less than the positive supply potential DC +. The difference between the positive supply potential DC + and the negative supply potential DC- may be at least 10 V, for example.

As a result, the positive supply potential DC + is at the first contiguous metallization section 311 and the negative supply potential DC- at the second contiguous metallization section 312 , As 2 can be seen, the first contiguous metallization section 311 a first base A311 and the second contiguous metallization section 312 a second base area A312. The second base area A312 is smaller than 1 / 0.95 times the first base area A311 and larger than the 1 / 1.05 times the first base area A311. Particularly preferably, the first base area A311 and the second base area A312 have the same area size.

To the second load connection 62 of the first semiconductor chip 6 low-resistance electrically connected to the positive supply potential DC + are one or more bonding wires 51 present, each of which both to the second load port 62 as well as the first contiguous metallization section 311 is bonded. Alternatively or in addition to the one or more bonding wires 51 However, other electrical connection techniques may be used, for example, one or more flat tapes, each by wire bonding both to the second load terminal 62 as well as the first contiguous metallization section 311 bonded or one or more angled shaped sheets, each directly adjacent to both the second load port 62 as well as the first contiguous metallization section 311 are soldered.

Accordingly, the first load connection 71 of the second semiconductor chip 7 low-resistance electrically connected to the positive supply potential DC-, one or more bonding wires 52 present, each of which is connected both to the first load connection 71 as well as the second contiguous metallization section 312 is bonded. Alternatively or in addition to the one or more bonding wires 52 However, other electrical connection techniques may be used, for example, one or more flat tapes, each by wire bonding both to the first load terminal 71 as well as the second contiguous metallization section 312 are bonded, or one or more angled shaped sheets, each directly adjacent to both the first load port 71 as well as the second contiguous metallization section 312 are soldered.

To the first contiguous metallization section 311 supplying the positive supply potential DC + is a first electrically conductive connection terminal 81 present, the low impedance with the first contiguous Metallisierungsabschnitt 311 , For example, by soldering, welding, electrically conductive bonding or wire bonding, is electrically connected.

Accordingly, the second contiguous metallization section 312 the negative supply potential DC supply, a second electrically conductive connection terminal 82 present, the low impedance with the second contiguous Metallisierungsabschnitt 312 , For example, by soldering, welding, electrically conductive bonding or wire bonding, is electrically connected.

A third electrically conductive connection terminal 83 serves to connect an electrical load to the so-called phase output Ph of the half-bridge. For this purpose, the third electrically conductive connection terminal 83 For example, by soldering, welding, electrically conductive bonding or wire bonding, low resistance to a circuit node between the first load terminal 61 of the first semiconductor chip 6 and the second load terminal 72 of the second semiconductor chip 7 connected. In the example shown, the third connection terminal is 83 on the second upper metallization layer 21 of the second sub-substrate 2 arranged and materially connected to this.

To the control terminal 63 of the first semiconductor chip 6 supplying a control signal is also an electrically conductive connection terminal 85 intended. This is, for example, by soldering, welding, electrically conductive bonding or wire bonding, galvanically low resistance to the second section 112 the first upper metallization layer 11 connected. In addition, the second section 112 the first upper metallization layer 11 through a bonding wire 55 that goes to both the second section 112 as well as to the control terminal 63 is permanently galvanically connected to the control terminal 63 connected.

Accordingly, to the control terminal 73 of the second semiconductor chip 7 to supply a control signal, an electrically conductive connection terminal 86 intended. This is, for example, by soldering, welding, electrically conductive bonding or wire bonding, galvanically low resistance to the second section 212 the second upper metallization layer 21 connected. Furthermore, the second section 212 the second upper metallization layer 21 through a bonding wire 56 that goes to both the second section 212 as well as to the control terminal 73 is permanently galvanically connected to the control terminal 73 connected.

As in 3 is illustrated, the connection terminals 81 . 82 . 83 . 85 . 86 each from a housing 8th of the semiconductor module 100 be led out, leaving their ends from the outside of the case 8th are accessible and can be electrically contacted from the outside. The connection connections 81 . 82 . 83 . 85 . 86 For example, they may be formed as metallic sheets or as metallic pins. At her from the outside of the case 8th they can be designed as solder connections or as press-fit contacts (press-fit contacts), for example, or they can each have a screw-on opening. Optionally, further connections are conceivable, such as auxiliary collector connections or connections for contacting a temperature monitoring element.

The circuit diagram according to 4 represents an equivalent circuit diagram for that in the 1 to 3 shown semiconductor module 100 It shows the semi-bridge connected in series and exemplified as n-channel IGBTs semiconductor chips 6 and 7 , In the diagram, for the sake of simplicity, no free-wheeling diode is drawn to the IGBTs, but this can optionally be provided and connected in anti-parallel to the respective IGBTs. It must then also be taken into account in the module in terms of layout technology!

A capacitance C + between the metallization layer (s) at or at which the positive supply potential DC + is permanently applied during operation and the metallization layer (s) which are grounded (GND potential) during operation are substantially the same in the example shown Capacitance between the first contiguous metallization section 311 on the one hand and the lower metallization layer 32 of the main substrate 3 and / or the heat sink 9 ( 3 ). Correspondingly, a capacitance C- between the metallization layer (s) on which or at which the negative supply potential DC- is permanently applied during operation and the metallization layer (s) which are grounded (GND potential) during operation is in the example shown in FIG Essentially by the capacitance between the second contiguous metallization section 312 on the one hand and the lower metallization layer 32 of the main substrate 3 and / or the heat sink 9 ( 3 ).

A capacitance CGH between the metallization layers or layers, which when operating permanently at the electrical potential of the control terminal 63 of the first semiconductor chip 6 lie, and the one or more metallization layers, on which or permanently applied to the operation in the positive supply potential DC +, in the example shown is essentially by the capacity between the second section 112 the first upper metallization layer 11 on the one hand and the first contiguous metallization section 311 on the other hand. Correspondingly, a capacitance CGL between the metallization layer (s) that during operation is permanently at the electrical potential of the control terminal 73 of the second semiconductor chip 7 lie, and the one or more metallization layers on which or on which the negative supply potential DC- permanently applied during operation, is in the example shown essentially by the capacitance between the second section 212 the second upper metallization layer 21 on the one hand and the second contiguous metallization section 312 on the other hand.

In addition, an output capacitance Cout of the half-bridge is essentially determined by the capacitance between the metallization layer (s) permanently at the electrical potential of the phase output Ph during operation and the metallization layer (s) at or at which the negative supply potential DC- is given. In the example shown, Cout is essentially due to the capacitance between the first section 211 the second upper metallization layer 21 on the one hand and the second contiguous metallization section 312 on the other hand.

Also shown in 4 are inductances L + and L-, which are the inductances of the represent electrical connection lines, over which the semiconductor module 100 an external positive supply potential DC '+ or DC'- is supplied. This potential DC '+ and DC'- may differ slightly from the potentials DC + and DC- respectively. The connection port 81 makes a contribution to L +, the connection port 82 a contribution to L-. Also shown is the output capacitance Cout.

5 shows a part of the basis of the 1 to 3 explained semiconductor module 100 who is the first section 211 the second upper metallization layer 21 contains. During normal operation of the semiconductor module 100 is, as explained above, each of the semiconductor chips 6 and 7 the half-bridge alternately turned on and off, in such a way that at any time, the load path of at most one of the semiconductor chips 6 and 7 passes. This is due to the first section 211 (apart from a small voltage drop across the semiconductor chips 6 respectively. 7 ) alternately the potentials DC + and DC-. In order to keep the thereby caused Umladungsströme to ground small, it is advantageous if the capacity between the section 211 and mass (here the metallization layer 32 and possibly a heat sink attached thereto 9 (please refer 3 ) is kept low. In the present case, this is achieved by the metallization section lying at DC potential 312 between the section 211 and mass is arranged, in such a way that the metallization section 312 at each point S211 of the section 211 vertically below the section 211 located.

In other words, for every location S211 of the first section 211 in that a straight connection g extending from this point S211 to the insulating support 30 facing side of the lower metallization 32 extends and perpendicular to this side, the second contiguous Metallisierungsabschnitt 312 cuts.

Interference currents to ground GND can also flow across the capacitance which is between ground GND and the one electrically connected to the control terminal 63 of the first controllable semiconductor chip 6 connected second section 112 the first upper metallization layer 11 is trained. To keep these interference currents low, the first contiguous metallization section 311 the metallization layer 31 between ground GND and the second section 112 the first upper metallization layer 11 be arranged. The electrically connected to the first connection terminal 81 for DC + connected, first contiguous metallization section 311 the metallization layer 31 causes a shield and thus a reduction of interference. In this case, optionally, the first metallization section 311 the metallization layer 31 such between the second section 112 the first upper metallization layer 11 and ground GND may be arranged such that the first metallization section 311 at every point of the second section 112 the first upper metallization layer 11 perpendicular to the second section 112 the first upper metallization layer 11 located below this. In other words, every point in the second section applies 112 the first upper metallization layer 11 in that a straight connecting line extending from this point to the insulating support 30 facing side of the lower metallization 32 extends and perpendicular to this side, the first metallization 311 the metallization layer 31 cuts.

Accordingly, interference currents to ground GND can also flow across the capacitance which is between ground GND and the electrical to the control terminal 73 of the second controllable semiconductor chip 7 connected second section 212 the second upper metallization layer 21 is trained. To keep these interference currents low, the second contiguous metallization section 312 the metallization layer 31 between ground GND and the second section 212 the second upper metallization layer 21 be arranged. The electrically connected to the second connection terminal 82 for DC-connected, second continuous metallization section 312 the metallization layer 31 causes a shield and thus a reduction of interference. In this case, optionally, the second metallization section 312 the metallization layer 31 such between the second section 212 the second upper metallization layer 21 and ground GND may be arranged such that the second metallization section 312 at every point of the second section 212 the second upper metallization layer 21 perpendicular to the second section 212 the second upper metallization layer 21 located below this. In other words, every point in the second section applies 212 the second upper metallization layer 21 in that a straight connecting line extending from this point to the insulating support 30 facing side of the lower metallization 32 extends and perpendicular to this side, the second metallization 312 the metallization layer 31 cuts.

6 shows two separate semiconductor modules 100 and 100 ' each with a semiconductor chip 6 respectively. 7 , The left semiconductor module 100 corresponds essentially to the left part of the in 1 illustrated semiconductor module 100 , the right semiconductor module 100 ' essentially the right part of the 1 illustrated semiconductor module 100 , This division into separate semiconductor modules eliminates the in the semiconductor module 100 of the 1 existing bond connection 53 , Instead of that was in the first upper metallization layer 11 in addition to the first section 111 and the second section 112 a third section 113 added. By means of a bonding wire 53 ' which is connected to this third section 113 as well as the first load connection 61 of the first semiconductor chip 6 Bonded is the third section 113 galvanic with the first load connection 61 connected. A likewise supplemented, electrically conductive connection connection 83 ' that is galvanic with the third section 113 is connected, facilitates the electrical contacting of the first load terminal 61 ,

Compared to the semiconductor module 100 according to 1 own the semiconductor modules 100 and 100 ' according to 6 no common carrier substrate 3 more. Instead, the semiconductor module points 100 a carrier substrate 3 with an insulation carrier 30 on top of which an upper metallization layer 31 and an optional lower metallization layer 32 are applied. Accordingly, the semiconductor module 100 ' a carrier substrate 3 ' with an insulation carrier 30 ' on top of which an upper metallization layer 31 ' and an optional lower metallization layer 32 ' are applied. The structure of the carrier substrates 3 and 3 ' , in particular the materials used for this purpose, are identical to the structure of the carrier substrate 3 according to 1 ,

In the arrangement according to 7 are these two semiconductor modules 100 and 100 ' each in its own housing 8th respectively. 8th' arranged and on a common heat sink 9 assembled. Alternatively, the two semiconductor modules could 100 and 100 ' be arranged in a common housing. For the realization of a half-bridge whose structure according to the circuit arrangement according to 1 corresponds, are the connection terminals 83 ' of the semiconductor module 100 and 83 of the semiconductor module 100 ' with a connection line 83 " galvanically connected. To these connection connections 83 . 83 ' or the connection line 83 " In addition, an electrical load can be connected.

During operation of the half-bridge, the alternating potential of the phase output PH, PH ', 83 " So both at the third section 113 the metallization layer 31 as well as the first section 211 the metallization layer 21 at. To the capacities that the sections 113 and 211 with respect to mass, to keep low, is between the relevant section 113 . 211 on the one hand and ground GND on the other hand each one of the metallization sections 311 respectively. 312 which is at the potential DC + or DC- during operation of the module.

Circuit technology corresponds to the arrangement according to 7 the arrangements according to the 1 to 4 , However, the first contiguous metallization section is 311 now part of the upper metallization layer 31 of the carrier 3 and the second contiguous metallization section 312 is part of the upper metallization layer 31 ' of the carrier 3 ' , However, here too, the first contiguous metallization section 311 a first base A311 and the second contiguous metallization section 312 a second base A312, wherein the second base A312 is smaller than 1/955 times the first base A311 and larger than 1 / 1.05 times the first base A311. The two base areas A311 and A312 may in particular also have the same area.

In the arrangement according to 8th are two semiconductor modules 100-1 and 100-2 together on a flat surface section 9t a heat sink 9 arranged. The structure of each of the semiconductor modules 100-1 and 100-2 corresponds to the structure of the semiconductor module according to the 1 to 3 , Thus, each of the semiconductor modules 100-1 and 100-2 a half-bridge on. the phase output of the semiconductor module 100-1 is designated PH-1, the phase output of the semiconductor module 100-2 with PH-2. The phase outputs PH-1 and PH-2 are independent of each other. However, the two semiconductor modules 100-1 and 100-2 supplied by the same supply voltage, for example a DC link voltage. These are the connection connections 81 the two modules 100-1 and 100-2 , which serve to connect a positive supply potential DC + ', via a connecting line 81 " galvanically connected to each other. Accordingly, the connection terminals 82 the two modules 100-1 and 100-2 , which serve to connect a negative supply potential DC- ', via a connecting line 82 " galvanically connected to each other. In a corresponding manner, three or more such semiconductor modules can also be operated on a common voltage supply.

Regardless of the number of on the flat surface section 9t arranged semiconductor modules 100-1 . 100-2 and irrespective of the concrete structure of a semiconductor module arrangement, it may have a number N1 ≥ 1 of first metallization sections 311-1 . 311-2 have, which are galvanically connected to each other in the case of N1> 1 and which are each formed as a thin metallization. During operation of the semiconductor module arrangement, these are all located at an arbitrary first (the same) of the potentials DC + and DC-. Each of the N1 metallization sections 311-1 . 311-2 has a base area whose total gives a first base area A311.

Accordingly, the semiconductor module arrangement can have a number N 2 ≥ 1 of second metallization sections 312-1 . 312-2 have, which are galvanically connected to each other in the case of N2> 1 and which are each formed as a thin metallization. During operation of the semiconductor module arrangement, these lie on the other second (same) of the potentials DC + or DC-, on which the first metallization sections are not already located. Each of the N2 metallization sections 312-1 . 312-2 has a base area whose total gives a second base area A312.

The number N1 can be identical to all metallization sections 311-1 . 311-2 , ... of the semiconductor module arrangement, which are formed as thin metallization layers and which are applied directly to an insulating support, wherein different of these metallization sections 311-1 . 311-2 , ... can be applied on the same or on any number of different insulation carriers. The total area A311 then indicates the total area of all the thin metallization layers that lie on the first of the potentials DC + and DC- during operation of the semiconductor module arrangement.

Accordingly, the number N2 may be identical to all the metallization sections 312-1 . 312-2 , ... of the semiconductor module arrangement, which are formed as thin metallization layers and which are applied directly to an insulating support, wherein different of these metallization sections 312-1 . 312-2 , ... can be applied on the same or on any number of different insulation carriers. The total area A312 then indicates the total area of all the thin metallization layers that lie on the second of the potentials DC + and DC- during operation of the semiconductor module arrangement.

Unlike the examples shown, the base areas of the N1 first metallization sections 311-1 . 311-2 , ... not all be identical. Rather, any combinations are possible. Correspondingly, the bases of the N2 must also have second metallization sections 312-1 . 312-2 , ... not all be identical. Again, any combinations are possible.

To only a small difference of the capacities C + and C- (corresponding 4 ), the second base area A312 is smaller than 1 / 0.95 times the first base area A311 and larger than 1 / 1.05 times the first base area A311. The two base areas A311 and A312 can also be chosen the same.

In addition, the capacities of the metallization sections 211-1 . 211-2 , which are electrically connected to the phase outputs PH-1 and PH-2 to keep low, is between the mass element lying on ground GND (here, the heat sink 9 and the metallizations 32 ) and the respective metallization section 211-1 . 211-2 any of the first or second metallization sections 311-1 . 311-2 , ... and 312-1 . 312-2 , ..., which serves as Abschirmmetallisierung, in such a way that the electrical mass element 32 . 9 , GND at its respective metallization section 211-1 . 211-2 facing side a flat surface section 9t and that for each location S211-1, S211-2 of each of the third metallization sections 211-1 . 211-2 holds that one to the surface section 9t vertical connecting line g1 or g2, extending from this point S211-1 or S211-2 to the surface portion 9t extending to the respective third metallization section 211-1 . 211-2 belonging shielding metallization 311-1 . 311-2 , ... 312-1 . 312-2 , ... cuts through.

Analogously, in a semiconductor module arrangement of the present invention, all metallizations / metallization sections can also be used 112 . 212 (please refer 2 ), which is galvanic with a control terminal 63 . 73 the semiconductor chips 6 . 7 the semiconductor module assembly are connected, in each case by a Abschirmmetallisierung between the lying on ground GND mass element (here again the heat sink 9 and the metallizations 32 ) and the respective metallization / metallization section 112 . 212 be arranged, wherein the respective Abschirmmetallisierung by any of the first or second metallization sections 311-1 . 311-2 , ... and 312-1 . 312-2 , ... can be given.

In addition, the capacities of the metallization sections 211-1 . 211-2 , which are electrically connected to the phase outputs PH-1 and PH-2 to keep low, is between the mass element lying on ground GND (here, the heat sink 9 and the metallizations 32 ) and the respective metallization section 211-1 . 211-2 any of the first or second metallization sections 311-1 . 311-2 , ... and 312-1 . 312-2 , ... arranged, in such a way that the electrical mass element 32 . 9 , GND at its respective metallization section 211-1 . 211-2 facing side facing a flat surface portion 9t having; and that for each location S211-1, S211-2 of each of the third metallization sections 211-1 . 211-2 holds that one to the surface section 9t vertical connecting line g1 or g2, extending from this point S211-1 or S211-2 to the surface portion 9t extending to the respective third metallization section 211-1 . 211-2 intersecting shielding metallization.

In the above-explained metallization layers 11 . 12 . 21 . 22 . 31 . 32 . 31 ' . 32 ' and metallization sections 111 . 112 . 113 . 211 . 212 . 311 . 312 . 311-1 . 311-2 . 312-1 . 312-2 a circuit carrier 1 . 2 . 3 . 3 ' These are in each case thin metallization layers, which are applied over the whole area to an insulation carrier or to one of a plurality of insulation carriers, contacting it over the entire area. In this sense, provide connection connections 81 . 82 . 83 . 83-1 . 83-2 . 85 . 86 or bonding wires 51 . 52 . 53 . 55 . 56 no metallization layers or metallization sections (= sections of metallization layers). The maximum thickness of each of the metallization layers 11 . 12 . 21 . 22 . 31 . 32 . 31 ' . 32 ' For the purposes of the present invention, for example, be less than or equal to 1 mm.

Claims (19)

Semiconductor module arrangement comprising a main substrate ( 3 ) with an insulating support ( 30 ), which has a top ( 30t ), to which a structured metallization layer ( 31 ), wherein the structured metallization layer ( 31 ) a first contiguous metallization section ( 311 ) and a second contiguous metallization section separated therefrom ( 312 ), wherein on the first contiguous metallization section ( 311 ) a first sub-substrate ( 1 ) is arranged, the - a first insulation support ( 10 ), - a first upper metallization layer ( 11 ) projecting onto a first contiguous metallization section ( 311 ) facing away from the top of the first insulating substrate ( 10 ) is applied; on the second contiguous metallization section ( 312 ) a second sub-substrate ( 2 ), which - a second insulation support ( 20 ), - a second upper metallization layer ( 21 ) facing a second contiguous metallization section ( 312 ) facing away from the top of the second insulation carrier ( 20 ), and - a second lower metallization layer ( 22 ) facing a second contiguous metallization section ( 312 ) facing the underside of the second insulation carrier ( 20 ) is applied; on a first section ( 111 ) of the first upper metallization layer ( 11 ) a first controllable semiconductor chip ( 6 ), which - a first load terminal ( 61 ) and a control terminal ( 63 ) located on one of the first upper metallization layer ( 11 ) facing away from the top of the first controllable semiconductor chip ( 6 ) are arranged; and - a second load connection ( 62 ) located on one of the first upper metallization layer ( 11 ) facing the underside of the first controllable semiconductor chip ( 6 ) is arranged; on a first section ( 211 ) of the second upper metallization layer ( 21 ) a second controllable semiconductor chip ( 7 ), which - a first load terminal ( 71 ) and a control terminal ( 73 ) located on one of the second upper metallization layer ( 21 ) facing away from the top of the second controllable semiconductor chip ( 7 ) are arranged; and - a second load connection ( 72 ) located on one of the second upper metallization layer ( 21 ) facing the underside of the second controllable semiconductor chip ( 7 ) is arranged; the first contiguous metallization section ( 311 ) has a first base (A311); and the second contiguous metallization section ( 312 ) has a second base area (A312) that is smaller than 1 / 0.95 times the first base area (A311) and greater than 1 / 1.05 times the first base area (A311).  A semiconductor module assembly according to claim 1, wherein the first base (A311) is equal to the second base (A312). Semiconductor module arrangement according to Claim 1 or 2, in which the insulating support ( 30 ) one of its top ( 30t ) opposite bottom ( 30b ) to which a lower metallization layer ( 32 ) is applied; and for each digit (S211) of the first section (S211) 211 ) of the second upper metallization layer ( 21 ) holds that a connection path (g) extending from this point (S211) to the insulating support (S2) 30 ) facing side of the lower metallization layer ( 32 ) and perpendicular to this side, the second contiguous metallization section (FIG. 312 ) cuts through. Semiconductor module arrangement according to one of the preceding claims, in which the first load connection ( 61 ) of the first semiconductor chip ( 6 ) and the second load terminal ( 72 ) of the second semiconductor chip ( 7 ) are permanently galvanically connected to each other. Semiconductor module arrangement according to one of the preceding claims, in which the first contiguous metallization section ( 311 ) and the second contiguous metallization section ( 312 ) no one has a portion between the other of these metallization sections ( 311 . 321 ) and the insulating support ( 30 ) is arranged. Semiconductor module arrangement according to one of the preceding claims, in which the first controllable semiconductor chip ( 6 ) between its first load terminal ( 61 ) and its second load terminal ( 62 ) has a first load path; and the second controllable semiconductor chip ( 7 ) between its first load terminal ( 71 ) and its second load terminal ( 72 ) has a second load path, which is electrically connected in series with the first load path. Semiconductor module arrangement according to one of the preceding claims, in which the first controllable semiconductor chip ( 6 ) and the second controllable semiconductor chip ( 7 ) is each formed as an n-channel field effect transistor with an electrically insulated gate; or the first controllable semiconductor chip ( 6 ) and the second controllable semiconductor chip ( 7 ) is formed in each case as a p-channel field effect transistor with an electrically insulated gate. Semiconductor module arrangement according to one of the preceding claims, in which a first bonding wire ( 51 ) to the first contiguous metallization section ( 311 ) and to the first upper metallization layer ( 11 ) is bonded. Semiconductor module arrangement according to one of the preceding claims, in which a second bonding wire ( 52 ) to the second contiguous metallization section ( 312 ) and to the first load terminal ( 71 ) of the second controllable semiconductor chip ( 7 ) is bonded. Semiconductor module arrangement according to one of the preceding claims, in which a third bonding wire ( 53 ) to the second upper metallization layer ( 21 ) and to the first load terminal ( 61 ) of the first controllable semiconductor chip ( 6 ) is bonded. Semiconductor module arrangement according to one of the preceding claims, in which the first sub-substrate ( 1 ) a first lower metallization layer ( 12 ), which on a first contiguous Metallisierungsabschnitt ( 311 ) facing the underside of the first insulation carrier ( 10 ) is applied and by means of a first connecting layer ( 41 ) containing the first contiguous metallization section ( 311 ) and the first lower metallization layer ( 12 ) contacted, cohesively with the first contiguous metallization section ( 311 ) connected is; and / or the second sub-substrate ( 2 ) a second lower metallization layer ( 22 ) facing a second contiguous metallization section ( 312 ) facing the underside of the second insulation carrier ( 20 ) is applied and by means of a second connection layer ( 42 ) comprising the second contiguous metallization section ( 312 ) and the second lower metallization layer ( 22 ) contacted, cohesively with the second contiguous metallization section ( 312 ) connected is. Semiconductor module arrangement comprising a number N1 ≥ 1, in the case of N1> 1 galvanically interconnected, first metallization sections ( 311-1 . 311-2 ), each of which - is formed as a thin metallization; and - has a base area; the total sum of these bases giving a first base area (A311); a number N2 ≥ 1, in the case of N2> 1 galvanically interconnected, second metallization sections ( 312-1 . 312-2 ), each of which - is formed as a thin metallization; and - has a base area; the total sum of these base areas giving a second base area (A312); a first controllable semiconductor chip ( 6 ), the - a second load connection ( 62 ), which on an underside of the first controllable semiconductor chip ( 6 ) arranged one of the first metallization sections ( 311-1 . 311-2 facing); and - a first load connection ( 61 ) and a control terminal ( 63 ), which on one of the underside opposite top of the first controllable semiconductor chip ( 6 ) are arranged; a second controllable semiconductor chip ( 7 ), the - a second load connection ( 72 ), which on an underside of the second controllable semiconductor chip ( 7 ) arranged one of the second metallization sections ( 312-1 . 312-2 facing); and - a first load connection ( 71 ) and a control terminal ( 73 ), which on one of the underside opposite top of the second controllable semiconductor chip ( 7 ) are arranged; wherein the first load connection ( 61 ) of the first controllable semiconductor chip ( 6 ) and the second load terminal ( 72 ) of the second controllable semiconductor chip ( 7 ) are galvanically connected to each other; the second load connection ( 62 ) of the first controllable semiconductor chip ( 6 ) with the first metallization sections ( 311-1 . 311-2 ) is galvanically connected; the first load connection ( 71 ) of the second controllable semiconductor chip ( 7 ) with the second metallization sections ( 312-1 . 312-2 ) is galvanically connected; the second footprint (A312) is less than 1 / 0.95 times the first footprint (A311) and greater than 1 / 1.05 times the first footprint (A311).  A semiconductor module assembly according to claim 12, wherein the first base (A311) is equal to the second base (A312). Semiconductor module arrangement according to one of claims 12 or 13 with a number N3 ≥ 1, in the case of N3> 1 galvanically interconnected, third metallization sections ( 113 . 211 . 211-1 . 211-2 ), each connected to the first load terminal ( 61 ) of the first controllable semiconductor chip ( 6 ) and with the second load connection ( 72 ) of the second controllable semiconductor chip ( 7 ) are galvanically connected. Semiconductor module arrangement according to Claim 14 with an electrical ground element ( 32 . 9 , GND), in which each of the third metallization sections ( 113 . 211 . 211-1 . 211-2 by a shield metallization, each through one of the first metallization sections ( 311-1 . 311-2 ) or through one of the second metallization sections ( 312-1 . 312-2 ) is formed, opposite the mass element ( 32 . 9 , GND) shielded by the relevant Abschirmmetallisierung between this third Metallisierungsabschnitt ( 113 . 211 . 211-1 . 211-2 ) and the mass element ( 32 . 9 , GND) is arranged. Semiconductor module arrangement according to Claim 15, in which the electrical ground element ( 32 . 9 , GND) at one of the third metallization sections ( 32 . 9 Facing side, a flat surface portion ( 9t ) having; and for each location (S113, S211, S211-1, S211-2) of each of the third metallization sections ( 113 . 211 . 211-1 . 211-2 ), one to the surface section ( 9t ) vertical connecting line (g1, g2) extending from this point (S113, S211, S211-1, S211-2) to the surface portion ( 9t ) extending to the respective third metallization section ( 113 . 211 . 211-1 . 211-2 ) intersecting Abschirmmetallisierung. Semiconductor module arrangement according to one of Claims 15 or 16, in which the entirety of the N1 first metallization sections ( 311-1 . 311-2 ) relative to the electrical mass element ( 32 . 9 , GND) has a first capacitance (C +); the entirety of the N2 second metallization sections ( 312-1 . 312-2 ) relative to the electrical mass element ( 32 . 9 , GND) has a second capacity (C-); and the second capacitance (C-) is less than 1 / 0.95 times the first capacitance (C +) and greater than 1 / 1.05 times the first capacitance (C +). Semiconductor module arrangement according to one of Claims 12 to 17 with one or more insulation carriers ( 10 . 20 . 30 . 30 ' ), wherein each of the first, second and, if present, third metallization sections ( 113 . 211 . 211-1 . 211-2 ) in an extension region which passes through the lateral edges of the relevant metallization section ( 113 . 211 . 211-1 . 211-2 ), one of the isolation carriers ( 10 . 20 . 30 . 30 ' ) contacted over the entire surface. A method of operating a semiconductor module assembly comprising the steps of: providing a semiconductor module assembly formed according to any one of the preceding claims; Applying a first electrical supply potential (DC +) to the second load connection ( 62 ) of the first controllable semiconductor chip ( 6 ); Applying a second electrical supply potential (DC-) different from the first electrical supply potential (DC +) to the first load connection ( 71 ) of the second controllable semiconductor chip ( 7 ).

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