DE102015108909A1 - Arrangement of a plurality of power semiconductor chips and method for producing the same - Google Patents

Arrangement of a plurality of power semiconductor chips and method for producing the same

Info

Publication number
DE102015108909A1
DE102015108909A1 DE102015108909.2A DE102015108909A DE102015108909A1 DE 102015108909 A1 DE102015108909 A1 DE 102015108909A1 DE 102015108909 A DE102015108909 A DE 102015108909A DE 102015108909 A1 DE102015108909 A1 DE 102015108909A1
Authority
DE
Germany
Prior art keywords
semiconductor chips
chip carrier
power
power semiconductor
surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE102015108909.2A
Other languages
German (de)
Inventor
Georg Meyer-Berg
Edward Fuergut
Joachim Mahler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE102015108909.2A priority Critical patent/DE102015108909A1/en
Publication of DE102015108909A1 publication Critical patent/DE102015108909A1/en
Application status is Pending legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/44Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements the complete device being wholly immersed in a fluid other than air
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/38Structure, shape, material or disposition of the strap connectors prior to the connecting process of a plurality of strap connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/41Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/32227Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the layer connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/3701Shape
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/40227Connecting the strap to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/40227Connecting the strap to a bond pad of the item
    • H01L2224/40228Connecting the strap to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/404Connecting portions
    • H01L2224/40475Connecting portions connected to auxiliary connecting means on the bonding areas
    • H01L2224/40499Material of the auxiliary connecting means
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/41Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H01L2224/4105Shape
    • H01L2224/41051Connectors having different shapes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/41Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H01L2224/411Disposition
    • H01L2224/4118Disposition being disposed on at least two different sides of the body, e.g. dual array
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8384Sintering
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/8484Sintering
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/9201Forming connectors during the connecting process, e.g. in-situ formation of bumps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06575Auxiliary carrier between devices, the carrier having no electrical connection structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06582Housing for the assembly, e.g. chip scale package [CSP]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385Assembly of a plurality of insulating substrates
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15151Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00Constructional details common to different types of electric apparatus
    • H05K7/02Arrangements of circuit components or wiring on supporting structure
    • H05K7/023Stackable modules
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00Constructional details common to different types of electric apparatus
    • H05K7/02Arrangements of circuit components or wiring on supporting structure
    • H05K7/06Arrangements of circuit components or wiring on supporting structure on insulating boards, e.g. wiring harnesses
    • H05K7/08Arrangements of circuit components or wiring on supporting structure on insulating boards, e.g. wiring harnesses on perforated boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00Constructional details common to different types of electric apparatus
    • H05K7/02Arrangements of circuit components or wiring on supporting structure
    • H05K7/10Plug-in assemblages of components, e.g. IC sockets
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00Constructional details common to different types of electric apparatus
    • H05K7/20Modifications to facilitate cooling, ventilating, or heating

Abstract

A semiconductor power device includes a chip carrier having a first surface and a second surface opposite the first surface. The semiconductor power device further includes a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and / or the second surface of the chip carrier.

Description

  • FIELD OF TECHNOLOGY
  • This invention relates to the art of arranging multiple power semiconductor chips, and more particularly to high density power semiconductor chip assemblies.
  • GENERAL PRIOR ART
  • Power semiconductor device manufacturers are constantly striving to increase the performance of their products while reducing their manufacturing costs. A costly area in the manufacture of power semiconductor devices is the packaging of the power semiconductor chip. Because the performance of semiconductor power devices is highly dependent on the heat dissipation capability provided by the package, much effort, expense, and expense are needed to implement semiconductor power devices that include a plurality of dense power semiconductor chips. Therefore, low cost semiconductor power devices having high thermal resistance, improved heat dissipation capability, and increased reliability and electrical performance are desirable.
  • For these and other reasons, there is a need for the present invention.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are incorporated to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as the same becomes better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding like parts.
  • 1 FIG. 12 schematically illustrates a top view of an exemplary semiconductor power device including a carrier and a plurality of power semiconductor chips attached to the carrier by via techniques.
  • 2 FIG. 12 schematically illustrates a side view of the exemplary semiconductor power device of FIG 1 , as from point A of 1 seen from.
  • 3 FIG. 12 schematically illustrates a top view of an exemplary semiconductor power device including a carrier and a plurality of power semiconductor chips mounted to the carrier by a surface mount technique.
  • 4 FIG. 12 schematically illustrates a side view of the exemplary semiconductor power device of FIG 3 , as from point A of 3 seen from.
  • 5 FIG. 12 schematically illustrates a top view of an exemplary semiconductor power device including a carrier and a plurality of power semiconductor chips attached to the carrier by metal foil support or winding techniques.
  • 6 FIG. 12 schematically illustrates a side view of the exemplary semiconductor power device of FIG 5 , as from point A of 5 seen from.
  • 7 schematically illustrates a side view of a portion of an exemplary semiconductor power assembly, such as. From point B of 3 seen from.
  • 8th schematically illustrates a side view of a portion of an exemplary semiconductor power assembly, such as. From point A of 5 seen from.
  • 9 FIG. 10 is a flowchart of an exemplary process for producing a semiconductor power device. FIG.
  • DETAILED DESCRIPTION
  • In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this connection, directional terminology such as "top", "bottom", "front", "back", "top", "bottom" etc. is used with reference to the orientation of the figures described. Because components of embodiments may be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is not intended to be limiting in any way. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is therefore not to be considered as limiting, and the scope of the present invention is defined by the appended claims.
  • It should be understood that the features of the various embodiments described herein may be combined with each other unless expressly stated otherwise.
  • Further, as used in this specification, the terms "bonded," "attached," "connected," "coupled," and / or "electrically connected / electrically coupled" are not intended to mean that the elements or layers must be brought into direct contact ; Intermediate elements or layers may be provided between the "bonded", "attached", "connected", "coupled" and / or "electrically connected / electrically coupled" elements, respectively. However, the above-mentioned terms according to the disclosure may optionally also have the special meaning that the elements or layers are brought into direct contact, i. H. no intermediate elements or layers are provided between the "bonded", "attached", "connected", "coupled" and / or "electrically connected / electrically coupled" elements.
  • Further, the words "over" or "above" used with respect to a part, element, or layer of material formed above or above a surface or "above" or "above." Is used herein to mean that the part, element or layer of material "directly on," e.g. B. is in direct contact with the intended surface (eg, set thereon, formed, deposited, etc.). The words "above" or "above" used in reference to a part, element or layer of material formed "above" or "above" a surface, or "over" or "above" a surface may be used herein to mean that the part, element, or layer of material is "located on," or deposited on the intended surface (eg, on top of it, formed, deposited, etc.) and one or more additional parts, elements or layers between the intended surface and the part, the element or the material layer are arranged. The same applies analogously to the terms "under", "below" etc.
  • The semiconductor power devices described herein include a plurality of power semiconductor chips. These power semiconductor chips may be of different types and may be manufactured by different technologies. They include (monolithic) integrated power circuits and further include, for example, possibly integrated logic circuits, analog integrated circuits, mixed signal integrated circuits, memory circuits or sensors. The power semiconductor chips referred to herein may be made of a specific semiconductor material such as Si, SiC, SiGe, GaAs, GaN, AlGaN, InGaAs, InAlAs, etc., and may further contain inorganic and / or organic materials are not semiconductors.
  • The power semiconductor chips referred to herein are e.g. B. possibly circuit breakers, power transistors, power diodes, etc. They may additionally contain control circuits, microprocessors, memory circuits and / or sensors.
  • For example, the power semiconductor chips referred to herein may be formed as power MISFETs (metal-insulator-semiconductor field-effect transistors), power MOSFETs (metal-oxide-semiconductor field-effect transistors), IGBTs (insulated-gate bipolar transistors), JFETs (Junction Field Effect Transistors), HEMTs (High Electron Mobility Transistors), Power Bipolar Transistors or Power Diodes, e.g. B. as a PIN diode or Schottky diode.
  • The power semiconductor chips referred to herein may be e.g. B. have a vertical structure, that is, the semiconductor chips may be prefabricated such that electrical currents can flow in a direction perpendicular to the main surfaces of the semiconductor chip direction. A power semiconductor chip having a vertical structure has electrodes on its two major surfaces, that is, on the surfaces of its top and bottom surfaces.
  • The power semiconductor chips referred to herein may have a horizontal structure. A power semiconductor chip having a horizontal structure often has chip electrodes on only one of its two major surfaces, e.g. On its active surface.
  • The semiconductor power device described herein includes a chip carrier to which a plurality of power semiconductor chips are attached. The chip carrier can z. B. a ceramic plate coated with one or more structured metal layers, e.g. B. include a ceramic substrate with Metallbondung. By way of example, the chip carrier may comprise a DCB ceramic substrate (DCB = Direct Copper Bonded). It is also possible that the chip carrier may include or may be a PCB. The PCB can z. For example, a multilayer PCB may include or be comprised of a plurality of stacked organic and metal layers, wherein the metal layers may form a wiring or an electrical interconnect of the PCB. Next can the chip carrier z. B. a lead frame, an IMS (IMS = Isolated Metal Substrate, insulated metal substrate) or an MIS (Molded Interconnect Substrate), such as. For example, an injection molded circuit ceramic interposer or an injection molded circuit lead frame may be or may be one of these elements. It should be noted that, in addition to the power semiconductor chips, further electronic components can also be mounted on the chip carrier and electrically connected to it. The further electronic components can be designed as passive and / or active components. A passive component is z. As a resistor, a capacitor, a coil, a clock and / or an integrated passive device (Integrated Passive Device, PID). An active component is z. A logic semiconductor chip, a memory semiconductor chip, a drive semiconductor chip to drive one or more of the power semiconductor chips, a level shifter, and a microcontroller chip or sensor. In contrast to the / the semiconductor chip (s), the (further) electronic components z. B. be mounted by means of a conventional SMD technology on the chip carrier.
  • Various different types of semiconductor power devices may be configured in accordance with the disclosure herein. In particular, a semiconductor power device described herein may comprise a plurality of half-bridge circuits including a high-side transistor, a low-side transistor, and optionally a z. B. as a transistor gate driver serving chip with integrated logic circuit. Further, the semiconductor power assembly disclosed herein may comprise a full bridge, e.g. B. a B6 circuit z. B. 6 power transistors and (optional) a z. B. serving as a power transistor gate driver chip with integrated logic circuit includes.
  • The power semiconductor chips can z. B. connected in series or in parallel or electrically isolated from each other. The electrical interconnection between the power semiconductor chips can be provided by the wiring of the chip carrier.
  • Semiconductor power module arrangements, as described herein, are e.g. B. implementable in various electronic circuits, z. In circuits that include or include a power supply, a voltage converter, a rectifier, a PFC (Power Factor Correction) circuit, etc. By way of example, a voltage converter for the conversion of DC or AC voltages into DC voltages can be designed as so-called DC-DC converters or AC-DC converters. DC-DC converters can be used to convert a DC input voltage provided by a battery or a rechargeable battery into a DC output voltage that is tailored to the needs of downstream electronic circuits. A DC-DC converter described herein is e.g. For example, you might have a down converter or a down converter. AC-to-DC converters may be used to provide an input AC voltage, e.g. B. is provided by a high voltage AC mains, to convert into a DC output voltage, which is tailored to the needs of downstream electronic circuits.
  • 1 illustrates a top view of an exemplary semiconductor power device 100 if this in a housing 10 is introduced. As will be described in more detail below, the housing may 10 be filled with a cooling fluid, wherein the plurality of power semiconductor chips to be immersed in the cooling fluid.
  • The semiconductor power device includes a chip carrier 110 with a first surface 110a and a second surface 110b opposite the first surface 110a , The chip carrier 110 may be in the form of a plate, wherein the first surface 110a and the second surface 110b the main surfaces of the plate are and a top surface 110c which in the top view of 1 is visible, an edge surface of the plate is.
  • The chip carrier 110 includes an electrical wiring 111 , The electrical wiring 111 may include structured metal layers on the first surface 110a and / or the second surface 110b of the chip carrier 110 are applied. Furthermore, the electrical wiring can be an internal electrical interconnection of the chip carrier 110 that z. B. is implemented by structured metal layers, which are along the direction of the main plane of the chip carrier 110 extend, comprise or designed as such. The main level of the chip carrier 110 can through the plate-shaped extension of the chip carrier 110 be defined (see, for example, 2 ).
  • The chip carrier 110 can continue an electrical connector 113 include. The electrical connector 113 can with the electrical wiring 111 , z. B. with the internal electrical interconnection of the chip carrier 110 if present, and / or with the textured metal layers on the first surface 110a and / or the second surface 110b of the chip carrier 110 are applied, be electrically connected.
  • As mentioned earlier, the chip carrier 110 of any suitable type, e.g. Possibly a PCB or a ceramic plate, which is covered by structured metal layers, or is possibly a plastic plate, which is an electrical wiring 111 comprises, as exemplified above. Further, it may include a lead frame, an MIS or an IMS. As will be further understood below, the chip carrier 110 being an ordinary inexpensive carrier, since its ability to dissipate heat and promote heat dissipation is typically of little importance to the semiconductor power devices described herein.
  • A variety of power semiconductor chips 120 is on the chip carrier 110 attached. The power semiconductor chips 120 are to the first surface 110a and / or to the second surface 110b of the chip carrier 110 inclined. In particular, as in 1 1, the power semiconductor chips 120 perpendicular to the first surface 110a and / or to the second surface 110b of the chip carrier 110 be arranged, ie the main plane of the plate-shaped chip carrier 110 , As mentioned above, in this and all other examples described herein, except for the power semiconductor chips 120 other electronic components (not shown) on the chip carrier 110 be mounted. The further electronic components can be designed as passive and / or active components.
  • In the following it will be assumed, without loss of generality and to simplify the description, that the power semiconductor chips 120 perpendicular to the chip carrier 110 are oriented. However, in general, any inclination angle between the power semiconductor chips 120 and the chip carrier 110 (or more precisely, the main level thereof), e.g. B. angles equal to or less than 80 °, 70 °, 60 °, 50 °, etc.
  • The power semiconductor chips 120 can be oriented parallel to each other. A distance D between adjacent power semiconductor chips 120 may be equal to or less than 4.0 mm, 3.0 mm, 2.0 mm, 1.5 mm, 1.0 mm, 0.75 mm, 0.5 mm, 0.3 mm. As will be better understood, for reasons which will be explained in more detail below, quite short distances D between adjacent power semiconductor chips can be achieved 120 realize. In other words, a high density chip device can be achieved by the technique described herein.
  • It should be noted that the spacing D between adjacent power semiconductor chips 120 may be identical for all semiconductor chip pairs, but does not have to be. More specifically, the distance D can be variations for different pairs of power semiconductor chips 120 subject. By way of example, such variations may be based on design limitations, e.g. B. on the location of the connector 113 taking more space between adjacent power semiconductor chips 120 required. In other cases, the distance D and / or variations of the distance D may be based on electrical constraints, e.g. As the Kriechweglänge (cd), as the minimum distance between adjacent power semiconductor chips 120 must be guaranteed. The creepage distance may depend on the breakdown strength of the medium (eg, cooling fluid) between the adjacent power semiconductor chips 120 can also depend on the operating voltage of the power semiconductor chips 120 depend. If so some of the power semiconductor chips 120 have a different operating voltage than other of the power semiconductor chips 120 , the creepage distance between different pairs of power semiconductor chips 120 vary, as well as the distances D in between. In addition, the (minimum) distance D may depend on thermal limitations, e.g. B. from the power class of power semiconductor chips 120 and / or the heat dissipation capability of the medium (cooling fluid) between the power semiconductor chips 120 which may depend on many parameters, e.g. From the chemical composition of the cooling fluid, the power of a heat exchanger for the cooling fluid, flow rates of fluid flows to the power semiconductor chips 120 in the case 10 , the angles of inclination of the power semiconductor chips 120 relative to the chip carrier 110 Etc.
  • The power semiconductor chips 120 can be naked chips. The term nude chip means that the power semiconductor chip is provided only with load and control electrodes, if present, and optionally with electrical traces connected to these electrodes and over the power semiconductor chip 120 extend, but without an injection molded or laminated, the power semiconductor chip 120 embedding encapsulation. Such injection-molded or laminated organic encapsulants are often used in the prior art for the packaging of power semiconductor chips, but may be omitted in the examples described herein for reasons which will become more readily apparent from the description below.
  • The power semiconductor chips 120 can each have a first surface 120a and a second surface 120b opposite the first surface 120a exhibit. One or both of these surfaces 120a . 120b can be equipped with electrodes, z. B. load electrodes and / or control electrodes. If the power semiconductor chips 120 vertical components are, load electrodes are usually located on both surfaces 120a . 120b the power semiconductor chips 120 , If the power semiconductor chips 120 horizontal components are, the load electrodes are usually either only on the first surface 120a or only on the second surface 120b ,
  • The power semiconductor chips 120 can with a first metallization layer 121 that are about the first surface 120a extends, and / or with a second metallization layer 121b extending over the second surface 120b extends, be provided. Both the first metallization layer 121 as well as the second metallization layer 121b may be either continuous or structured, ie they may be subdivided into a plurality of island-like subsections.
  • The first insulating layer 121 and the second insulating layer 121b can provide the chip electrodes. Thus, no metal interconnects connected to the electrodes are provided. The power semiconductor chips 120 in this case simply correspond to a power semiconductor chip with prefabricated chip electrodes. In other examples, the first metallization layer 121 and / or the second metallization layer 121b continue to provide metal interconnects, via the power semiconductor chip 120 run and are adapted to the power semiconductor chip electrodes with the chip carrier 110 connect to.
  • In other words, the first metallization layer 121 and the second metallization layer 121b , in the 1 can be implemented by chip electrodes or reinforced chip electrodes (eg galvanically or chemically or physically reinforced chip electrodes) or by metal interconnects connected to the chip electrodes (wherein the metal interconnects can also be prefabricated by a galvanic or chemical or physical deposition).
  • The first metallization layer 121 and / or the second metallization layer 121b the power semiconductor chips 120 can be with the wiring 111 of the chip carrier 110 connect electrically. The connection may be to any internal electrical interconnection or any external structured metal layers of the wiring 111 being constructed.
  • Next will be with reference to 1 the power semiconductor chips 120 shown in the chip carrier 110 penetrate while an upper edge side 120c the power semiconductor chips 120 in the top view of 1 remains visible. This corresponds to a slit-shaped (slot-shaped) configuration of the chip carrier 110 , In other examples, the power semiconductor chips 120 in the chip carrier 110 penetrate by passing through through holes in it. In this case, the upper edge side would be 120c the power semiconductor chips 120 just outside the chip carrier 110 visible, noticeable.
  • 2 illustrates a side view of the power assembly 100 from 1 , as from point A of 1 from, it being assumed that the side wall 10c of the housing 10 is transparent. More sidewalls 10a and 10b be in the 1 and 2 also illustrated.
  • For example, the front power semiconductor chip 120 , as in 2 can be seen, a first metallization 121 which is structured. By way of example, it is structured such that it has a first subsection 121a_1 and a second subsection 121a_2 includes. As described above, this first subsection 121a_1 and this second subsection 121a_2 (optionally reinforced) chip electrodes can and do with the wiring 111 of the chip carrier 110 be directly connected. This is accompanied by the fact that both chip electrodes, as from the first section 121a_1 and from the second subsection 121_2 illustrated with the geometry of the chip carrier 110 overlap. Otherwise, as already mentioned above, the first metallization layer 121 additionally with electrical tracks for connecting chip electrodes to the wiring 111 of the chip carrier 110 be provided.
  • Further referring to 2 and without loss of generality, the power semiconductor chip 120 z. B. be designed as a power transistor, for example as a power MOSFET, IGBT, JFET or power bipolar transistor or as a power diode. In the case of a power MOSFET or JFET, a first load electrode is defined by a first section 121a_1 the first metallization layer 121 may be provided, possibly a source electrode, a second load electrode passing through the second metallization layer 121b may be provided, for. B. possibly a drain electrode, and a third electrode through a second section 121a_2 the first metallization layer 121 may be provided, may be a gate electrode. In the case of an IGBT, analogously is a first load electrode (eg a first subsection 121a_1 the first metallization layer 121 ) possibly an emitter electrode, a second load electrode (eg the second metallization layer 121b ) is possibly a collector electrode, and a third electrode (eg, a second section 121a_2 the first metallization layer 121 ) is possibly a gate electrode. In the case of a power bipolar transistor, the first load electrode may be an emitter electrode, the second load electrode may be a collector electrode, and a third electrode may be a base electrode. In the case of a power diode, the first and second load electrodes are a cathode or an anode, and there is no third electrode. During operation, voltages greater than 5, 50, 100, 500, 1000 or 1200 V may be applied between the first and second load electrodes. A switching frequency applied to the third electrode may be in the range of 100 Hz to 100 MHz, but may be outside this range.
  • The 3 and 4 illustrate a top view and a side view, respectively, of point A of a semiconductor power device 300 , The semiconductor power device 300 can the semiconductor power supply 100 similar and in most respects to it, and reference is made to the above disclosure to avoid repetition.
  • Unlike in the semiconductor power device 100 penetrate the power semiconductor chips 120 the semiconductor power device 300 the chip carrier 110 Not. Instead, the power semiconductor chips 120 on the first surface 110a and / or the second surface 110b of the chip carrier 110 surface mounted.
  • Therefore, edges of the power semiconductor chips 120 on the first surface 110a and / or the second surface 110b of the chip carrier 110 be mounted. The assembly may include that of the power semiconductor chips 120 by a bonding material (not shown) such. As a solder or a sintered or a plating material to the wiring 111 of the chip carrier 110 be attached.
  • Next, the chip carrier 110 with a pattern of trenches 115 in the first surface 110a and / or the second surface 110b be provided. In this case, an edge portion of the power semiconductor chips 120 into corresponding trenches 115 the first surface 110a or the second surface 110b introduce, see enlarged section of 3 , This simplifies the placement process, in which the power semiconductor chips 120 in an upright position on the chip carrier 110 be applied.
  • As in 3 exemplified, the chip carrier 110 be designed so that it individual power semiconductor chips 120 on both surfaces 110a and 110b holds. Thereby, the chip density of the semiconductor power device becomes 300 further increased.
  • Regarding 4 are two separate power semiconductor chips 120 visible, one of which is on the first surface 110a of the chip carrier 110 and one on the second surface 110b of the chip carrier 110 is attached. As a result, in the exemplary semiconductor power device 300 the second section 121a_2 the first metallization layer 121 at the "mounting" edge 120d each power semiconductor chip 120 are located.
  • The 5 and 6 illustrate a plan view and a side view, respectively, of a semiconductor power device 500 , as from point A of 5 seen from. The semiconductor power device 500 can the semiconductor power assemblies 100 . 300 similar or identical to most features. Therefore, reference is made to the description above to avoid repetition.
  • In the semiconductor power supply 500 are the power semiconductor chips 120 on a metal foil located on a first side 520a and / or a metal foil located on a second side 520b attached and are supported by this metal foil / these metal foils. If both metal foils 520a . 520b can be used, the power semiconductor chips 120 between these metal foils 520a . 520b each sandwiched. The metal foil on the first page 520a can be at least part of the first surface 120a of the power semiconductor chip 120 Cover, and / or located on the second side metal foil 520b can be at least part of the second surface 120b of the power semiconductor chip 120 cover. The metal foil on the first page 520a and the metal foil on the second side 520b can be electrically isolated from each other. The metal foil on the first page 520a can with one or more chip electrodes on the first surface 120a of the power semiconductor chip 120 be connected, and / or located on the second side metal foil 520b can with one or more chip electrodes on the second surface 120b of the power semiconductor chip 120 be connected. If the first surface 120a and / or the second surface 120b include a plurality of chip electrodes, the respective metal foils located on the first and second sides 520a . 520b be divided into different sections or strips that are electrically isolated from each other and each may be connected to a chip electrode.
  • The metal foil on the first page 520a and / or the metal foil located on the second side 520b can on the chip carrier 110 to be appropriate. In 5 are various examples of the attachment of the metal foil on the first side 520a and / or the metal foil on the second side 520b illustrated. Exemplary, as in 501 illustrated, the metal foil located on the first side 520a and / or the metal foil located on the second side 520b be bent over at their ends, so that they are the chip carrier 110 are facing to flanges to be provided on the chip carrier 110 or more precisely, metal layers of the wiring 111 that on the first surface 110a and / or the second surface 110b of the chip carrier 110 are attached, attached (eg soldered to it, sintered on it etc.) could be.
  • at 502 another solution is shown in which the ends of the metal foil on the first side 520a and the metal foil on the second side 520b that the chip carrier 110 are facing, are introduced in column (slots) in the chip carrier 110 are provided. This solution uses a plug-in connection technique to fix the metal foil on the first side 520a and the metal foil on the second side 520b in which the power semiconductor chips 120 on the chip carrier 110 be arranged in between.
  • at 503 Another example is illustrated in which the chip carrier 110 a gap in its upper surface 110c and the first metal foil 520a and / or the second metal foil 520b are introduced into this gap.
  • at 504 Yet another example solution is illustrated in which the chip carrier 110 may have a through hole and the metal foil located on the first side 520a and / or the metal foil located on the second side 520b are adapted to pass through the through hole when the power semiconductor chip 120 is attached in the place.
  • In all these examples for mounting the power semiconductor chips 120 on the chip carrier 110 can be the metal foil on the first page 520a and / or the metal foil located on the second side 520b on the chip carrier 110 , z. B. at its wiring 111 , attached and electrically connected to him / her or bonded to him / her. Next can be found in all examples 501 . 502 . 503 . 504 the metal foil on the first side 520a and / or the metal foil located on the second side 520b be adapted to the power semiconductor chip 120 to hold mechanically in place. By way of example, a thickness of the metal foil located on the first side 520a and / or the metal foil on the second side 520b possibly equal to or greater than 100 μm, 200 μm, 300 μm, 400 μm or even larger. This will ensure that the mechanical stability and rigidity of the metal foil located on the first side 520a and / or the metal foil on the second side 520b are good enough for a secure connection between the power semiconductor chip 120 and the chip carrier 110 to guarantee. The greater the thickness T, the better the ability of the metal foil on the first side 520a and / or the metal foil on the second side 520b for carrying current peaks. On the other hand, the thickness T of the metal foil on the first side should be 520a and / or the metal foil on the second side 520b not too large, since the foils can function as thermal insulations, and therefore increasing the thickness T also means increasing the thermal resistance between the power semiconductor chips 120 and the medium (cooling fluid) inside 11 of the housing 10 should be included. The metal foils may comprise any metal material or be of any metal material, e.g. B. a metal material with a good thermal conductivity such. As copper or an alloy thereof. The metal foils 520a . 520b may also include other materials (eg, dielectrics, organic material, polymeric material) or reinforcing layers comprising or made of these materials (eg, dielectric layer, organic layer, polymer layer). Therefore, as used herein, the term metal foil should also include interconnect layer structures that include at least one metal foil.
  • 7 FIG. 12 illustrates a side view of a portion of an exemplary semiconductor power device. FIG 300 , such as From point B of 3 seen from. A first (eg reinforced) metallization layer 121 is divided into a first section 121a_1 , which corresponds to a source terminal, and a second subsection 121a_2 which corresponds to a gate terminal. The second (eg reinforced) metallization layer 121b serves as a drain connection. At the chip carrier 110 are the source, the gate and the drain with metal layers 701 . 702 . 703 connected, which is part of the wiring 111 form.
  • The exemplary structure of the first (eg, reinforced) metallization layer 121 and the second (eg, reinforced) metallization layer 121b , as in 7 can be shown analogous to the structure of the metal foil located on the first side 520a and / or the metal foil on the second side 520b in the 5 and 6 correspond. That is, the structure of the metal foil on the first side 520a includes z. B. possibly a source terminal and a gate terminal and / or the structure of the metal foil located on the second side 520b includes z. B. possibly a drain connection.
  • 8th FIG. 12 illustrates a side view of a portion of an exemplary semiconductor power device. FIG 500 , such as From point A of 5 seen from. As already described, the exemplary semiconductor device represents 500 by way of example a "foil routing" of the power semiconductor chips 120 to the chip carrier 110 In this example contains the first surface 120a of the power semiconductor chip 120 z. B. a gate electrode G and a source electrode S. A drain electrode is z. On the second surface 120b of the power semiconductor chip 120 , in the 8th is not visible.
  • The metal foil on the second side 520b covers the drain and includes a strip 520b ' about which she is using the chip carrier 110 connected is. The source electrode S is of a first section 520a_1 the metal foil on the first page 520a covered, a strip 520a_1 ' includes, over which it with the chip carrier 110 connected is. The gate electrode G is of a second section 520a_2 the metal foil on the first page 520a covered, a strip 520a_2 ' includes, over which it with the chip carrier 110 connected is. The spacing between the stripes 520a_1 ' and 520b ' should be equal to or greater than the creepage distance (cd) to prevent electrical breakdown. It should be noted that the edge 120d of the power semiconductor chip 120 by a certain distance from the chip carrier 110 can be spaced.
  • In all the examples described herein, power semiconductor chips could be used 120 be used from high performance classes. Cooling is crucial, especially for high-performance applications, because the maximum current that can be switched depends heavily on the operating temperature. The higher the operating temperature, the lower the current that can be switched. For example, if a maximum switching current of about 150 A at 25 ° C is reached, the maximum switching current may drop to about 75 A at 100 ° C.
  • For example, a power semiconductor chip having an operating voltage of about 1200 V and an operating current of about 30 A (at a certain operating temperature) has a switching power of 36 kW. If z. B. 1% of the switching power is converted into heat, a heat output of 360 W is dissipate during operation. The concept of heat removal by using a cooling fluid is z. B. suitable for a heat dissipation of equal to or above 200, 300, 400, 500, 600, 700 or 800 W per power semiconductor chip. Thus, high maximum switching currents for semiconductor chips from high power classes could be realized.
  • 9 FIG. 10 illustrates an exemplary method of manufacturing a semiconductor power device, such as a semiconductor power device. B. the semiconductor power assemblies 100 . 300 . 500 , The method includes, at S1, attaching a plurality of power semiconductor chips to a chip carrier, the chip carrier having a first surface and a second surface opposite the first surface, wherein the power semiconductor chips are inclined to the first and / or second surfaces of the chip carrier. In this way, both the first surface and the second surface of the power semiconductor chips are not bonded to the chip carrier. Instead, they may both be exposed to heat transfer to a surrounding medium (cooling fluid). The chip carrier, on the other hand, need not have a complex design for optimizing the transfer and dissipation of heat.
  • During operation, the housing is 10 filled with a cooling fluid. The semiconductor power devices 100 . 300 . 500 and in particular, the plurality of power semiconductor chips 120 are completely immersed in the cooling fluid.
  • During operation of the semiconductor power device 100 . 300 . 500 The cooling fluid is heated and circulated by free convection to allow adequate heat removal. A heat exchanger (not shown) may be in the housing 10 be included to effectively dissipate the heat from the cooling fluid. One advantage is that the main heat dissipation path is not the chip carrier 110 (eg PCB, DCB, leadframe, INS or MIS), but rather the cooling fluid as such, so that the power semiconductor chips 120 designed without encapsulation and in a tilted or vertical orientation on the chip carrier 110 can be mounted. It should be noted that the cooling fluid may continue to undergo a phase transition (liquid in gaseous). A phase transition may embody a further cooling mechanism and increase the cooling power provided by the cooling mechanism for convective heat dissipation.
  • The cooling fluid may have a high dielectric strength equal to or greater than 10 or 12 kV / mm. The specific electrical resistance of the cooling fluid may be equal to or greater than 2 or 3 × 10 10 ohm-cm. The cooling fluid can have high chemical inertia and high chemical, physical and thermal stability. By way of example, a cooling fluid, as used herein, may be an organic compound having fluorine as an important component, e.g. As fluoroketones, hydrofluoroethers and fluoropolymers such. Methoxyheptafluoropropane, methoxynonafluorobutane, etc. Exemplary cooling fluids that could be used in the examples described herein are Novec cooling fluids produced by 3M , such as, e.g. B. Novec Engineered Fluid TM 7600.
  • The examples described herein may provide many advantages, e.g. B. effective heat dissipation, cost-effective production (low-cost materials, no encapsulation of the power semiconductor chip 120 ), improved reliability, low thermal stress on the power semiconductor chips 120 during operation, since the temperature gradient between the chip carrier 110 and the power semiconductor chips 120 possibly low, increased maximum operating temperature of the power semiconductor chips 120 (eg equal to or above 175 ° C, 200 °, etc.), increased chip density of the semiconductor power device 100 . 300 . 500 , Simple cooling concept, which relies only on the cooling fluid, increased size scalability of the semiconductor power device 100 . 300 . 500 and double-sided configuration or 3D design (three-dimensional configuration) of the semiconductor power device 100 . 300 . 500 ,
  • Although particular embodiments have been illustrated and described herein, it will be apparent to one of ordinary skill in the art that various alternative and / or equivalent implementations may be substituted for the particular embodiments shown and described without departing from the scope of the present invention. This application is intended to include any adaptations or variations of the specific embodiments discussed herein.

Claims (24)

  1. A semiconductor power device comprising: a chip carrier having a first surface and a second surface opposite the first surface; and a plurality of power semiconductor chips attached to the chip carrier, wherein the power semiconductor chips are inclined to the first and / or the second surface of the chip carrier.
  2. Semiconductor power device according to claim 1, wherein the power semiconductor chips are perpendicular to the first and / or the second surface of the chip carrier.
  3. A semiconductor power device according to claim 1 or 2, wherein the power semiconductor chips are oriented parallel to each other, and wherein a space between adjacent power semiconductor chips is equal to or smaller than 4.0 mm, 3.0 mm, 2.0 mm, 1.5 mm, 1.0 mm, 0.75 mm, 0.5 mm or 0.3 mm.
  4. The semiconductor power device according to any one of the preceding claims, wherein the chip carrier has a plurality of through holes or gaps and the power semiconductor chips pass through the through holes or gaps.
  5. Semiconductor power device according to one of the preceding claims, wherein edges of the power semiconductor chips are mounted on the first surface and / or the second surface of the chip carrier.
  6. The semiconductor power device of any one of the preceding claims, wherein the first surface and / or the second surface are provided with a plurality of trenches, and edges of the power semiconductor chips are inserted into the trenches.
  7. A semiconductor power device according to any one of the preceding claims, wherein the power semiconductor chips are bonded to the chip carrier by a solder material, a sintered material or a plating material.
  8. Semiconductor power device according to one of the preceding claims, wherein the power semiconductor chips are nude chips.
  9. Semiconductor power device according to one of the preceding claims, wherein the power semiconductor chips comprise electrodes, wherein the electrodes are connected to the chip carrier either directly or via metal interconnects, which run over the power semiconductor chips.
  10. Semiconductor power device according to one of the preceding claims, wherein the power semiconductor chips are each attached to a located on a first side and / or located on a second side metal foil.
  11. The semiconductor power device of claim 10, wherein the metal foil on the first side and / or the metal foil on the second side are attached to the chip carrier.
  12. The semiconductor power device according to claim 10, wherein the metal foil located on the first side and / or the metal foil located on the second side are configured to hold the power semiconductor chip in place.
  13. The semiconductor power device according to any one of claims 10 to 12, wherein the metal foil located on the first side and / or the metal foil located on the second side extend through a through hole or a gap in the chip carrier.
  14. The semiconductor power device of claim 1, wherein the chip carrier comprises a PCB, a ceramic plate covered by a patterned metallization to form the first and second surfaces thereof, a lead frame, an insulated metal substrate, or an injection molded circuit substrate.
  15. A semiconductor power device according to any one of the preceding claims, wherein the chip carrier comprises an electrical wiring and an electrical connector electrically connected to the electrical wiring.
  16. A semiconductor power device according to any one of the preceding claims, further comprising: a housing configured to receive the chip carrier and the plurality of power semiconductor chips.
  17. Semiconductor power module comprising: a chip carrier having a first surface and a second surface opposite the first surface; a plurality of power semiconductor chips attached to the chip carrier, the power semiconductor chips being inclined to the first and / or second surfaces of the chip carrier; a housing configured to receive the chip carrier and the plurality of power semiconductor chips; and a cooling fluid provided in the housing, wherein the plurality of power semiconductor chips are immersed in the cooling fluid.
  18. The semiconductor power module of claim 17, wherein the power semiconductor chips are perpendicular to the first and / or second surfaces of the chip carrier.
  19. The semiconductor power module according to claim 17 or 18, wherein the power semiconductor chips are oriented parallel to each other, and wherein a space between adjacent power semiconductor chips is equal to or smaller than 4.0 mm, 3.0 mm, 2.0 mm, 1.5 mm, 1.0 mm, 0.75 mm, 0.5 mm or 0.3 mm.
  20. A method of fabricating a semiconductor power device, the method comprising: Attaching a plurality of power semiconductor chips to a chip carrier, the chip carrier having a first surface and a second surface opposite the first surface, wherein the power semiconductor chips are inclined to the first and / or second surfaces of the chip carrier.
  21. The method of claim 20, wherein the power semiconductor chips are arranged perpendicular to the first and / or the second surface of the chip carrier.
  22. The method of claim 20 or 21, further comprising: Inserting the power semiconductor chips through through holes or in gaps in the chip carrier.
  23. The method of claims 20 to 22, further comprising: Inserting edges of the power semiconductor chips into trenches provided in the first surface and / or the second surface of the chip carrier.
  24. The method of claims 20 to 23, further comprising: Attaching each of the power semiconductor chips to a first side and / or a second side metal foil; and Attaching the metal foil located on the first side and / or the metal foil located on the second side to the chip carrier.
DE102015108909.2A 2015-06-05 2015-06-05 Arrangement of a plurality of power semiconductor chips and method for producing the same Pending DE102015108909A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE102015108909.2A DE102015108909A1 (en) 2015-06-05 2015-06-05 Arrangement of a plurality of power semiconductor chips and method for producing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102015108909.2A DE102015108909A1 (en) 2015-06-05 2015-06-05 Arrangement of a plurality of power semiconductor chips and method for producing the same
US15/171,364 US10049962B2 (en) 2015-06-05 2016-06-02 Arrangement of multiple power semiconductor chips and method of manufacturing the same

Publications (1)

Publication Number Publication Date
DE102015108909A1 true DE102015108909A1 (en) 2016-12-08

Family

ID=57352198

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102015108909.2A Pending DE102015108909A1 (en) 2015-06-05 2015-06-05 Arrangement of a plurality of power semiconductor chips and method for producing the same

Country Status (2)

Country Link
US (1) US10049962B2 (en)
DE (1) DE102015108909A1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001097286A2 (en) * 2000-06-13 2001-12-20 Mcnc High density three dimensional chip package assembly systems and methods
US20040164406A1 (en) * 2003-02-26 2004-08-26 Chih-Liang Hu Discrete circuit component having an up-right circuit die with lateral electrical connections

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4266282A (en) * 1979-03-12 1981-05-05 International Business Machines Corporation Vertical semiconductor integrated circuit chip packaging
JP2845926B2 (en) * 1989-03-20 1999-01-13 株式会社日立製作所 Man-machine system
US5239447A (en) * 1991-09-13 1993-08-24 International Business Machines Corporation Stepped electronic device package
JP2560974B2 (en) * 1993-06-04 1996-12-04 日本電気株式会社 Semiconductor device
JP3253765B2 (en) * 1993-06-25 2002-02-04 富士通株式会社 Semiconductor device
US5545924A (en) * 1993-08-05 1996-08-13 Honeywell Inc. Three dimensional package for monolithic microwave/millimeterwave integrated circuits
US5362986A (en) * 1993-08-19 1994-11-08 International Business Machines Corporation Vertical chip mount memory package with packaging substrate and memory chip pairs
US5661901A (en) * 1995-07-10 1997-09-02 Micron Technology, Inc. Method for mounting and electrically interconnecting semiconductor dice
US5604377A (en) * 1995-10-10 1997-02-18 International Business Machines Corp. Semiconductor chip high density packaging
US5817530A (en) * 1996-05-20 1998-10-06 Micron Technology, Inc. Use of conductive lines on the back side of wafers and dice for semiconductor interconnects
US6342731B1 (en) * 1997-12-31 2002-01-29 Micron Technology, Inc. Vertically mountable semiconductor device, assembly, and methods
US5940277A (en) * 1997-12-31 1999-08-17 Micron Technology, Inc. Semiconductor device including combed bond pad opening, assemblies and methods
US6191474B1 (en) * 1997-12-31 2001-02-20 Micron Technology, Inc. Vertically mountable interposer assembly and method
US6140696A (en) * 1998-01-27 2000-10-31 Micron Technology, Inc. Vertically mountable semiconductor device and methods
US6147411A (en) * 1998-03-31 2000-11-14 Micron Technology, Inc. Vertical surface mount package utilizing a back-to-back semiconductor device module
US6418033B1 (en) * 2000-11-16 2002-07-09 Unitive Electronics, Inc. Microelectronic packages in which second microelectronic substrates are oriented relative to first microelectronic substrates at acute angles
US6958533B2 (en) * 2002-01-22 2005-10-25 Honeywell International Inc. High density 3-D integrated circuit package
US20040084211A1 (en) * 2002-10-30 2004-05-06 Sensonix, Inc. Z-axis packaging for electronic device and method for making same
EP1471778A1 (en) * 2003-04-24 2004-10-27 Infineon Technologies AG Memory module having space-saving arrangement of memory chips and memory chip therefor
KR100586698B1 (en) * 2003-12-23 2006-06-08 삼성전자주식회사 Semiconductor Module having semiconductor chip package which is vertically mounted on module board
US20090072823A1 (en) * 2007-09-17 2009-03-19 Honeywell International Inc. 3d integrated compass package
US8053891B2 (en) * 2008-06-30 2011-11-08 Alpha And Omega Semiconductor Incorporated Standing chip scale package
US8703543B2 (en) * 2009-07-14 2014-04-22 Honeywell International Inc. Vertical sensor assembly method
US8004080B2 (en) * 2009-09-04 2011-08-23 Freescale Smeiconductor, Inc. Edge mounted integrated circuits with heat sink

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001097286A2 (en) * 2000-06-13 2001-12-20 Mcnc High density three dimensional chip package assembly systems and methods
US20040164406A1 (en) * 2003-02-26 2004-08-26 Chih-Liang Hu Discrete circuit component having an up-right circuit die with lateral electrical connections

Also Published As

Publication number Publication date
US10049962B2 (en) 2018-08-14
US20160358886A1 (en) 2016-12-08

Similar Documents

Publication Publication Date Title
US8237260B2 (en) Power semiconductor module with segmented base plate
US20040119148A1 (en) Semiconductor device package
US20100155915A1 (en) Stacked power converter structure and method
US9490200B2 (en) Semiconductor device
US20080054298A1 (en) Power module with laminar interconnect
US20070165376A1 (en) Three phase inverter power stage and assembly
EP1389820B1 (en) Low inductance circuit arrangement for power semiconductor modules
US6946740B2 (en) High power MCM package
US8324726B2 (en) Semiconductor device, electrode member and electrode member fabrication method
KR100881776B1 (en) - bond wireless power module with double-sided single device cooling and immersion bath cooling
US7301235B2 (en) Semiconductor device module with flip chip devices on a common lead frame
US5705848A (en) Power semiconductor module having a plurality of submodules
US8987777B2 (en) Stacked half-bridge power module
US8736043B2 (en) Power device having a specific range of distances between collector and emitter electrodes
WO2000042654A1 (en) Electronic semiconductor module
TWI430428B (en) High efficiency module
US8514579B2 (en) Power semiconductor module including substrates spaced from each other
JP5259016B2 (en) Power semiconductor module
US8705257B2 (en) Switching module including a snubber circuit connected in parallel to a series-connected unit of flowing restriction elements
US8208260B2 (en) Semiconductor device
JP6188902B2 (en) Power semiconductor module and power conversion device
EP2804212A1 (en) Semiconductor device
US20130181228A1 (en) Power semiconductor module and method of manufacturing the same
EP2164100A2 (en) Leaded semiconductor power module with direct bonding and double sided cooling
US8787003B2 (en) Low inductance capacitor module and power system with low inductance capacitor module

Legal Events

Date Code Title Description
R012 Request for examination validly filed
R016 Response to examination communication