DE102013102052B4 - Chip arrangement - Google Patents

Abstract

A chip assembly, comprising: a chip (300), the chip (300) comprising: a carrier (302) a metal layer (306) applied flat on a surface (304) of the carrier (302); Carrier (302) comprises a rectifier circuit (406) electrically coupled to the metal layer (306); wherein a portion of the carrier (302) forms an electrically conductive structure (412) which together with the metal layer (306) forms a capacitor for injecting an electrical signal into the rectifier circuit (406), or wherein an additional metal layer (410) is applied to an opposite surface to the surface (304) of the carrier (302) which together with the metal layer (306) forms a capacitor a booster antenna structure capacitively coupled to the carrier (302), the booster antenna structure ei a first part (502) and a second part (504), the chip (300) being arranged between the first part (502) and the second part (504), the booster antenna structure having an antenna; the first part (502) and the second part (504) of the booster antenna structure each have a first section (506, 508) and a second section (510, 512), wherein the respective first section (506, 508) is adapted to capacitive coupling with the carrier (302); and wherein the respective second portion (510, 512) is adapted for inductive coupling to a chip device external device.

Description

The invention relates to a chip arrangement.

A conventional booster antenna is typically used with a so-called coil on module, in other words a module, for example a chip, on which a coil monolithically integrated with the module is provided. In this case, for example, a small module, which has, for example, a communication chip and a matching antenna or conductor loop, operated by the booster antenna. As a result, the achievable read or write distance is usually increased significantly.

DE 10 2007 046 679 A1 describes an RFID transponder in which an antenna module is capacitively coupled to an electronic module.

DE 10 2005 017 655 A1 describes a multilayer composite body with electronic function comprising a plurality of organic electronic components. It is a structure of an entire assembly disclosed as an RFID tag, the entire day with all components in a manufacturing process is feasible.

EP 2 102 799 B1 describes a radio frequency identification tag that is foldable such that contacts disposed adjacent to a chip are capacitively coupled capacitively to these opposing contacts folded over it.

The invention is based on the problem to provide a chip arrangement with a booster antenna, which makes it possible to read even small chips by means of capacitive coupling.

The problem is solved by a chip arrangement having the features according to independent claim 1.

A chip arrangement comprising a chip is provided. The chip has a carrier; and a metal layer applied flat on a surface of the carrier; wherein the carrier has a rectifier circuit electrically coupled to the metal layer. The chip assembly further includes a booster antenna structure capacitively coupled to the carrier. The booster antenna structure has a first part and a second part, wherein the carrier is arranged between the first part and the second part. The booster antenna structure has an antenna. The first part and the second part of the booster antenna structure each have a first portion and a second portion, the respective first portion being adapted for capacitive coupling with the carrier; and wherein the respective second portion is adapted for inductive coupling to a chip device external device.

Illustratively, instead of inductive coupling in various embodiments, capacitive coupling to a reader is provided for capacitive coupling of a signal (a data signal or a power signal) into the carrier. The signal is, for example, an alternating voltage (AC) signal, which may have a single frequency or a plurality of frequencies, for example a carrier frequency and a plurality of frequencies modulated on the carrier frequency. The carrier is in various embodiments free of external contact pads (except for the surface applied metal layer).

In one embodiment, a part of the carrier may form an electrically conductive structure, which together with the metal layer form one or more capacitors for the reading device, designed for coupling an electrical signal into the rectifier circuit.

In yet another embodiment, the rectifier circuit may be configured to process signals in a frequency range of at least 25% relative to a given carrier frequency.

In yet another embodiment, the carrier frequency may be in the range of about 13.56 MHz, or about 433 MHz, or about 868 MHz, or about 2.4 GHz. For example, the coupling in a frequency range for operation according to the RF standard or the UHF standard or even higher frequency can thus be provided. Thus, the chip can clearly be part of a chip module or a chip card module and thus a chip card.

In yet another embodiment, the chip assembly may further include an electrical circuit electrically coupled to an output of the rectifier circuit.

In yet another embodiment, the chip assembly may further include a contact structure extending partially through the carrier and electrically coupling the metal layer to the rectifier circuit.

In yet another embodiment, the carrier may comprise a chip substrate and a wiring structure.

In yet another embodiment, the carrier may be a chip substrate and a wiring structure exhibit; and the contact structure may extend at least partially through the wiring structure.

In yet another embodiment, the chip assembly may further include an additional metal layer deposited on a surface opposite the surface of the carrier.

In yet another embodiment, the antenna may comprise a dipole antenna and / or a loop antenna.

In various embodiments, a method for operating a chip arrangement is provided. The method may include: capacitive coupling of a signal into a carrier by means of a metal layer applied flat on a surface of the carrier; and rectifying the coupled signal by means of a rectifier circuit electrically coupled to the metal layer.

Embodiments of the invention are illustrated in the figures and are explained in more detail below.

• 1 eine konventionelle Booster-Antenne mit einem Chip mit monolithisch integrierter Antenne;
• 2 ein elektrisches Ersatzschaltbild der Booster-Antenne aus 1;
• 3 einen Chip gemäß verschiedenen Ausführungsbeispielen;
• 4 eine Querschnittsdarstellung eines Chips gemäß verschiedenen Ausführungsbeispielen;
• 5 eine Booster-Antenne gemäß verschiedenen Ausführungsbeispielen;
• 6 eine vergrößerte Darstellung eines ersten Teils der Booster-Antenne aus 5 gemäß verschiedenen Ausführungsbeispielen;
• 7 eine Darstellung, in der zwei Teile der Booster-Antenne aus 5 aufeinander angeordnet werden gemäß verschiedenen Ausführungsbeispielen;
• 8 eine Querschnittansicht eines Ausführungsbeispiels eines Transpondersystems gemäß verschiedenen Ausführungsbeispielen;
• 9 ein Ablaufdiagramm, in dem ein Verfahren zum Betreiben einer Chip-Anordnung gemäß verschiedenen Ausführungsbeispielen dargestellt ist;
• 10 eine Querschnittsdarstellung eines Chips gemäß verschiedenen Ausführungsbeispielen; und
• 11 eine Implementierung eines Gleichrichterschaltkreises gemäß verschiedenen Ausführungsbeispielen.

Show it

• 1 a conventional booster antenna with a chip with monolithically integrated antenna;
• 2 an electrical equivalent circuit diagram of the booster antenna off 1 ;
• 3 a chip according to various embodiments;
• 4 a cross-sectional view of a chip according to various embodiments;
• 5 a booster antenna according to various embodiments;
• 6 an enlarged view of a first part of the booster antenna 5 according to various embodiments;
• 7 a representation in which two parts of the booster antenna off 5 arranged one on another according to various embodiments;
• 8th a cross-sectional view of an embodiment of a transponder system according to various embodiments;
• 9 a flowchart illustrating a method of operating a chip arrangement according to various embodiments;
• 10 a cross-sectional view of a chip according to various embodiments; and
• 11 an implementation of a rectifier circuit according to various embodiments.

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "front", "rear", etc. is used with reference to the orientation of the described figure (s). Because components of embodiments can be positioned in a number of different orientations, the directional terminology is illustrative and is in no way limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It should be understood that the features of the various exemplary embodiments described herein may be combined with each other unless specifically stated otherwise. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

As used herein, the terms "connected," "connected," and "coupled" are used to describe both direct and indirect connection, direct or indirect connection, and direct or indirect coupling. In the figures, identical or similar elements are provided with identical reference numerals, as appropriate.

Clearly, a new development of a booster antenna is provided in various embodiments. Various embodiments make it possible to read even very small communication modules and / or chips by means of capacitive coupling. Various embodiments have a simple structure of the chip capacitance surfaces, which is why it is not necessary to carry out optimization processes on the substrate material, for example silicon.

The chip capacitance surfaces are connected in various embodiments by means of a capacitive coupling with a larger antenna structure, which allows the conventional use as an RFID tag. Due to the simple capacitance structure of the type, a broadband signal, In various embodiments, a signal of substantially any frequency, be fed and thus any type of booster antenna can be used.

1 shows a conventional booster antenna 100 with a chip with a monolithically integrated antenna (coil on module) 102.

Illustratively, it is the conventional booster antenna 100 around a simple resonant circuit. This will be a large conductor loop 104 used for inductive coupling of energy. To achieve a so-called booster effect is a small part 106 the conductor loop 100 which also serves as a coupling area 106 is designated so pronounced that this is the coil on module 102 essentially encloses. By means of the coupling area 106 a further inductive coupling is formed, in this case with the coil on module 102 , so that by means of this inductive coupling communication with the coil on module 102 is possible.

Through the geometric approach of the coil on module 102 and a part of the conductor loop, ie the coupling region 106 , a very good coupling is achieved. Generally, the more similar and the closer the conductor loops are to each other, the better is their inductive coupling.

As in the equivalent circuit diagram 200 in 2 is shown is the booster antenna 202 formed by a resonant circuit, on the one hand, a first inductive coupling (symbolized in 2 by means of a first double arrow 204 ) with a reader (not shown) and, on the other hand, a second inductive coupling (symbolized in FIG 2 by means of a second double arrow 206 ) with the coil on module 102 , The big part 104 the conductor loop 100 has a first inductor 208 on, which has a first (large) inductance, a capacitor 210 , as well as an ohmic resistance 212 , and provides inductive coupling with the reader. The smaller part 106 the conductor loop 100 has a second inductor 214 which has a second (smaller) inductance and provides an inductive coupling with the coil on module 102 ready.

• • jede Booster-Antenne benötigt mindestens ein Kontaktloch;
• • das Coil on Module (CoM) bzw. Coil on Chip (CoC) 102 benötigt mindestens zwei Metallisierungsebenen für die Realisierung der Spule, wobei viele herkömmliche Coil on Module und Coil on Chips 102 sogar mehr Metallisierungsebenen vorsehen, um den Widerstand zu reduzieren.
• • Durch eine Spule am Chip oder am Modul wird üblicherweise eine einzige Betriebsfrequenz bzw. Resonanzfrequenz vorgegeben. Andere Frequenzen können in diesem Fall dann nicht mehr effizient eingekoppelt werden.

However, this structure may have various disadvantages, for example:

• Each booster antenna needs at least one contact hole;
• The Coil on Module (CoM) or Coil on Chip (CoC) 102 requires at least two metallization levels for the realization of the coil, many conventional coil on modules and coil on chips 102 even provide more metallization levels to reduce the resistance.
• • A coil on the chip or on the module usually specifies a single operating frequency or resonance frequency. Other frequencies can then no longer be efficiently coupled in this case.

Illustratively, in various embodiments, the conventional monolithically integrated coil in a coil on module 102 replaced by one or more on a surface of a carrier, such as a chip, flat metal layer (s), which forms a capacitor or form for capacitive coupling a signal (power supply signal and / or data signal) in the carrier.

3 shows a chip 300 according to various embodiments and 4 shows a cross-sectional view 400 of the chip 300 according to various embodiments.

The chip 300 indicates a carrier 302 , on and one on a surface 304 of the carrier 302 flat applied metal layer 306 ,

The carrier 302 can be a chip substrate 402 and a wiring structure 404 exhibit.

The chip substrate 402 may comprise a wafer substrate. The chip substrate 402 may be made of one or more semiconductor materials, for example silicon, germanium, one or more semiconductor materials of main groups III to V or the like, or of one or more polymers, although in other embodiments other suitable materials may also be used. In various embodiments, the chip substrate 402 may be made of silicon (doped or doped), in alternative embodiments, the chip substrate 402 a silicon on insulator (SOI) substrate. In other embodiments, any other suitable semiconductor material may be used for the chip substrate 402 be provided, for example, a semiconductor composite material such as gallium arsenide (GaAs), indium phosphide (InP), but also any suitable ternary or quaternary semiconductor composite material such as indium gallium arsenide (InGaAs).

On the chip substrate 402 can be a wiring structure 404 may be applied with a metallization or with several levels of metallization, wherein between the metallization levels so-called intermediate dielectric (for example, an oxide, for example, silicon oxide, a nitride, for example, silicon nitride, or a low-k dielectric or a high-k dielectric) may be provided. The plurality of metallization planes may be connected by means of one or more contact holes (in 4 not shown) to be electrically connected to each other.

In the carrier 302 , for example in the chip substrate 402 (Alternatively, however, also (completely or partially) in the wiring structure 404 ), is a rectifier circuit 406 (implemented, for example, in the form of a full-bridge circuit or a half-bridge circuit).

The rectifier circuit 406 Further, a rectifier circuit 406 which is arranged to rectify (generally to process) wideband signals, in other words signals over a wide frequency range.

A first input of the rectifier circuit 406 can with the metal layer 306 be electrically conductively connected, for example by means of one or more contact holes (vias) and / or by means of one or more Metallisierungsebenen. In various embodiments, the top layer of the carrier 302 illustratively be formed as a metal layer forming a capacitor surface. For example, the uppermost layer of the wiring structure 404 (For example, the topmost metallization) as a full-surface metal layer (in a chip, for example, also referred to as AllPad) be set up.

Illustratively forms the metal layer 306 a first capacitor plate of the coupling capacitor for coupling electrical energy, for example, from an external reader. Thus, in various embodiments, there are no additional metallization levels in the carrier, for example in the wiring structure 404 Required to realize a monolithic integrated coil.

A second capacitor plate of the coupling capacitor for coupling electrical energy may be of an optional further metal layer 410 be formed. The optional further metal layer 410 may be on the exposed surface (ie, bottom surface) of the carrier and thus the chip substrate 402 be upset. Alternatively, the second capacitor plate may be from the chip substrate 402 itself formed, for example, from a lower area 412 of the chip substrate which is free of the one or more electronic circuits 408 , The metal layer 106 and / or the optional further metal layer 410 may include one or more metals or one or more metal alloys, for example, copper, silver, gold, platinum, aluminum, or the like.

A second input of the rectifier circuit 406 can with the second capacitor plate 410 . 412 be electrically connected.

So-called HF tags usually have contact vias. Due to the many coil windings in a conventional coil on module 102 these are required for a galvanic connection. Through the capacitive coupling according to various embodiments, the booster antenna can be designed so that it clearly covers the chip from two sides (for example, the two main processing surfaces of the chip), thus clearly enclosing substantially. In this case, as will be explained in more detail below, the booster antenna have two parts, wherein a first part of the booster antenna on or above the metal layer 306 is arranged (in other words, on or above the upper surface of the chip 300 ) and a second part of the booster antenna underneath the chip 300 is arranged (in other words, below the lower surface of the chip 300 ).

Further, in the carrier may or may 302 , for example in the chip substrate 402 , one or more electronic circuits 408 be arranged. Even if in 4 a simple electronic circuits 408 in the wiring structure 404 is shown, this is to be understood symbolically; In various embodiments, the electronic circuit 408 at least partially in the chip substrate 402 educated.

An output of the rectifier circuit 406 can with the one or more electronic circuits 408 be coupled. The rectifier circuit 406 is arranged, an externally supplied electric field 414, by means of the capacitor (formed by the metal layer 106 and the second capacitor plate 410 or 412) is received (in other words received) to receive by means of its first input and its second input and to rectify the thus received AC voltage into a DC voltage. The rectified voltage becomes at its output for the one or more electronic circuits 408 provided.

The rectifier circuit 406 may be arranged to process signals in a frequency range of at least 25% relative to a given carrier frequency, for example in a frequency range of at least 30%, for example at least 35%, for example at least 40%, for example at least 45%, for example at least 50%, for example of at least 55%, for example of at least 60%, for example of at least 65%, for example of at least 70%, for example, at least 75%, for example at least 80%, for example at least 85%, for example at least 90%, for example at least 95%, for example at least 100% or more. The carrier frequency may be in the range of about 13.56 MHz (RF standard), or about 433 MHz, or about 868 MHz, or about 2.4 GHz (UHF standard). The signal with the carrier frequency can, for example, to power the chip 300 and a signal modulated onto the carrier frequency can be used for (bidirectional) communication with the chip, for example by means of load modulation.

In various embodiments, the rectifier circuit may be configured to process signals in a frequency range greater than 100 MHz (for example greater than 200 MHz, 300 MHz, 400 MHz, 500 MHz, 600 MHz, 700 MHz, 800 MHz, 900 MHz, 1 GHz, 1.5 GHz, 2 GHz, or even greater) by a carrier frequency (of course depending on the carrier frequency), for example in a frequency direction (for example, a frequency range greater or less than the carrier frequency) or in both frequency direction (for example, a frequency range greater and smaller as the carrier frequency) from the carrier frequency.

The rectifier circuit 406 may be arranged such that it has no AC coupling and already starts to work from 0 Hz, and it may be arranged, signals having a frequency up to a maximum switching frequency of the transistors (for example, metal oxide semiconductor transistors (MOS). : metal oxide semiconductor), for example PMOS transistors and / or NMOS transistors) of the rectifier circuit 406 to process. A possible implementation of the rectifier circuit 406 will be explained in more detail below.

As will be explained in more detail below, the capacitively designed chip 300 between two parts of a booster antenna 500 (please refer 5 ) and be capacitively coupled with them. The booster antenna 500 So clearly the chip 300 enclose and, for example, a series resonant circuit is formed, for example an RFID series resonant circuit (English: radio frequency identification, radio frequency identification).

The booster antenna 500 can be a first part 502 and a second part 504 have, wherein the first part 502 and the second part 504 can be folded on each other, with the chip 300 and optionally a dielectric between the two parts 502 . 504 the booster antenna 500 can be arranged and with the two parts 502 . 504 the booster antenna 500 capacitively coupled. It should be noted that both the first part 504 as well as the second part 502 the booster antenna to each other and to the chip 300 are galvanically separated from each other or can be.

The first part 502 and the second part 504 the booster antenna 500 have a booster antenna structure, each with a plurality or a plurality of metal turns, each illustratively forming a loop antenna. Both loop antennas have a first section 506 . 508 with a large capacitive metal surface that provides most of the electric field for capacitive coupling to the chip 300. Furthermore, both loop antennas have a second section 510 . 512 formed by a plurality or a plurality of antenna turns of metal structures. The second section 510 . 512 are used for inductive coupling with an external device, such as an external reader. Alternatively or additionally, the first part 502 and / or the second part 504 of the booster antenna 500 have a dipole antenna.

Generally, the booster antenna structure may be capacitively coupled to the carrier.

The chip 300 may be on the substrate of the first part 502 or alternatively also on the carrier material of the second part 504 of the booster antenna 500 be arranged and attached to it.

In 5 is an example of the chip 300 on the carrier material of the first part 502 the booster antenna 500 arranged. The chip 300 can be capacitive with the first part 502 the booster antenna 500 and / or the second part 502 be coupled to the booster antenna 500.

As in 5 is shown, the respective coil turns 510 . 512 offset from each other (if the two parts 502 . 504 folded on each other), so that no additional disturbing capacity arises.

The two parts 502 . 504 the booster antenna 500 can be capacitively coupled to each other or alternatively ohmic.

6 shows an enlarged view of the first part 502 the booster antenna 500 according to various embodiments.

7 shows a representation 700 in which the two parts 502 , 504 of the booster antenna 500 be arranged on each other according to various embodiments.

If the two parts 502 . 504 the booster antenna 500 the chip 300 enclose, together with the chip 300, a fully functional transponder system.

8th shows a cross-sectional view of an embodiment of a transponder system 800 according to various embodiments.

In this exemplary transponder system 800 is or is one or more chips 300 embedded in a paper support (or other flexible backing material such as a foil, such as a plastic foil) 802. Furthermore, a first part 804 a booster antenna, such as those related to above 5 is shown provided, and a second part 806 , The paper carrier 802 with the chip 300 is between the two parts 804 . 806 sandwiched the booster antenna.

Thus, the chip can 300 by means of the booster antenna with the first part 804 and the second part 806 be read, programmed, and / or controlled.

In one embodiment, placing the substrate in which the chip 300 embedded, which is a hard material such as glass, may be no via possible. In such a case, or if no via is desired for other reasons, an advantage of the various embodiments comes into play, namely that no via (vias) are required.

It should also be pointed out that the booster antenna structure, that is, for example, the electrically conductive structures of the first section 506 . 508 and / or the second of the second section 510 . 512 can be printed in a simple manner on the respective carrier material, for example by means of a so-called ink printing method (ink-jet method).

9 shows a representation 900 in which the two parts 902 , 904 of the booster antenna 500 be arranged on each other according to various embodiments.

If the two parts 902 . 904 the booster antenna 500 the chip 300 enclose, together with the chip 300, a fully functional transponder system.

10 shows a flowchart 1000 in which a method for operating a chip arrangement according to various embodiments is shown. The method may include, at 1002, capacitively injecting a signal into a carrier by means of a metal layer applied flatly to a surface of the carrier, and, in 1004, rectifying the injected signal by means of a rectifier circuit electrically coupled to the metal layer, and at 1006 , the supply of an integrated circuit by means of the energy obtained by the rectified signal, and, in 1008, the influence of the energy field by means of an integrated circuit for the transmission of data.

11 shows an implementation of a variant of a possible rectifier circuit 1100 according to various embodiments.

This variant can have a shunt resistor and / or a modulator 1108 which regulates the voltage or modulates an incoming or received signal. Furthermore, the rectifier circuit 1100 a short circuit 1106 which regulates the potential of the carrier to the electrically negative point.

Furthermore, the rectifier circuit 1100 a rectifier 1104 arranged to rectify the respective half-wave of the (for example) sinusoidal input signal 1110 so that a rectified signal 1112 is formed.

Due to the surface-applied metal layer 306 on the carrier 302 results in a parasitic capacitance proportional to the span area 1102 ,

In various embodiments, the chip arrangement can be used in a chip card module and / or a chip card.

Claims (8)

A chip assembly comprising: a chip (300), the chip (300) comprising: • a carrier (302); A metal layer (306) applied flat on a surface (304) of the carrier (302); Wherein the carrier (302) has a rectifier circuit (406) electrically coupled to the metal layer (306); Wherein a part of the carrier (302) forms an electrically conductive structure (412) which together with the metal layer (306) forms a capacitor, arranged to couple an electrical signal into the rectifier circuit (406), or wherein an additional metal layer (410) is deposited on a surface opposite the surface (304) of the carrier (302) which together with the metal layer (306) forms a capacitor, configured to inject an electrical signal into the rectifier circuit (406); a booster antenna structure capacitively coupled to the carrier (302), the booster antenna structure having a first portion (502) and a second portion (504), the chip (300) being sandwiched between the first portion (502) and the second part (504) is arranged, wherein the booster antenna structure comprises an antenna; Wherein the first part (502) and the second part (504) of the booster antenna structure each have a first section (506, 508) and a second section (510, 512), wherein the respective first section (506, 508) is arranged for capacitive coupling with the carrier (302); and wherein the respective second portion (510, 512) is adapted for inductive coupling to a chip device external device. Chip arrangement according to Claim 1 wherein the rectifier circuit (406) is arranged to process signals in a frequency range of at least 25% relative to a given carrier frequency. Chip arrangement according to Claim 1 or 2 , wherein the carrier frequency is in a range of about 13.56 MHz or about 433 MHz or about 868 MHz or about 2.4 GHz. Chip arrangement according to one of Claims 1 to 3 , further comprising: an electrical circuit (408) electrically coupled to an output of the rectifier circuit (406). Chip arrangement according to one of Claims 1 to 4 , further comprising: a contact structure extending partially through the carrier (302) and coupling the metal layer (306) to the rectifier circuit (406). Chip arrangement according to one of Claims 1 to 5 wherein the carrier (302) comprises a chip substrate (402) and a wiring structure (404). Chip arrangement according to Claim 5 • wherein the carrier (302) comprises a chip substrate (402) and a wiring structure (404); and wherein the contact structure extends at least partially through the wiring structure (404). Chip arrangement according to one of Claims 1 to 7 wherein the antenna comprises a dipole antenna and / or a loop antenna.

Images