DE102012221396A1 - Electronic arrangement for use in electronic assembly in e.g. motor vehicle electronics, has metallic sintered layer applied by dispensing or ink jet method, and connecting layer including gradient structure and/or rounding in corner region - Google Patents
Electronic arrangement for use in electronic assembly in e.g. motor vehicle electronics, has metallic sintered layer applied by dispensing or ink jet method, and connecting layer including gradient structure and/or rounding in corner region Download PDFInfo
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- DE102012221396A1 DE102012221396A1 DE201210221396 DE102012221396A DE102012221396A1 DE 102012221396 A1 DE102012221396 A1 DE 102012221396A1 DE 201210221396 DE201210221396 DE 201210221396 DE 102012221396 A DE102012221396 A DE 102012221396A DE 102012221396 A1 DE102012221396 A1 DE 102012221396A1
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- layer
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- sintered
- gradient structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K35/00—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting
- B23K35/02—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape
- B23K35/0222—Rods, electrodes, materials, or media, for use in soldering, welding, or cutting characterised by mechanical features, e.g. shape for use in soldering, brazing
- B23K35/0244—Powders, particles or spheres; Preforms made therefrom
- B23K35/025—Pastes, creams, slurries
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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- B23K35/30—Selection of soldering or welding materials proper with the principal constituent melting at less than 1550 degrees C
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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- B23K35/3006—Ag as the principal constituent
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- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
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Abstract
Description
Die vorliegende Erfindung betrifft eine Anordnung für elektronische Baugruppen umfassend eine Verbindungsschicht, insbesondere eine Sinterverbindungsschicht für Halbleiter, mit einer Gradientenstruktur und/oder mit Abrundungen im der Eckbereich gemäß den Merkmalen des Anspruchs 1, ein Verfahren zur Herstellung einer elektronischen Baugruppe mit einer solchen Verbindungsschicht gemäß den Merkmalen des Anspruchs 6 sowie die Verwendung einer solchen Anordnung bevorzugt in hoch temperaturbelasteten Elektroniken. The present invention relates to an assembly for electronic assemblies comprising a connection layer, in particular a sintered connection layer for semiconductors, with a gradient structure and / or with rounded corners in the corner region according to the features of claim 1, a method for producing an electronic assembly with such a connection layer according to the Features of claim 6 and the use of such an arrangement preferably in high-temperature-loaded electronics.
Stand der TechnikState of the art
Die heute am meisten eingesetzte Aufbau- und Verbindungstechnik bei der „Die Attach“-Montage in der Mikroelektronik ist die Lotverbindung. Aufgrund der Forderungen nach Verwendung von bleifreien Verbindungstechniken werden hierzu häufig Zinn-Silber-Lote verwendet. Die Anforderungen an die thermischen und thermomechanischen Eigenschaften an die Verbindungstechnik steigen jedoch stetig. Beispielsweise liegen die dauerhaften Temperaturbelastungen in der Leistungselektronik heute schon bei rund 175°C. Aufgrund der verwendeten Lotverbindungen und der hohen Einsatztemperaturen bis 245 °C, nahe ihrem Schmelzpunkt, zeigen die Lotverbindungsschichten abnehmende mechanische Eigenschaften. Ein häufiges Problem stellen die unterschiedlichen Ausdehnungskoeffizienten der Fügepartner und das daraus resultierende Kriechen des Lotes während des aktiven und passiven Betriebs dar. Eine Folgeerscheinung ist ein mögliches Risswachstum in der Lotschicht, resultierende Kurzschlüsse in der Baugruppe und somit ein Ausfall der Baugruppe. The most commonly used assembly and connection technology in "Die Attach" assembly in microelectronics is the solder connection. Due to the demands for the use of lead-free bonding techniques, tin-silver solders are often used for this purpose. However, the demands on the thermal and thermomechanical properties of the connection technology are increasing steadily. For example, the permanent temperature loads in power electronics are already around 175 ° C today. Due to the solder joints used and the high operating temperatures up to 245 ° C, close to their melting point, the solder joint layers show decreasing mechanical properties. A common problem is the different coefficients of expansion of the joining partners and the resulting creep of the solder during active and passive operation. A consequence is a possible crack growth in the solder layer, resulting short circuits in the assembly and thus a failure of the assembly.
Der Einsatz einer Sinterverbindung als Verbindungspartner könnte dieses Problem der Zerrüttung der Lotschicht lösen. Dieser Werkstoff wird bei einer unter dem Schmelzpunkt liegenden Temperatur verarbeitet. Die Paste besteht hauptsächlich aus edlen Metallpartikeln und/oder Metallverbindungen. Beim Erreichen der Verarbeitungstemperatur werden unter Temperatur- und Druckbeaufschlagung bestehende Metallverbindungen aufgebrochen und somit kann ein Kontakt mit den Fügepartnern, wie zum Beispiel Substrat und Halbleiter, stattfinden. Eine hochtemperaturstabile Sinterverbindung bildet sich als Verbindungsschicht aus. Bei solchen Verbindungsschichten beispielsweise aus Silber können im Vergleich zu Weichlotverbindungen Kriechvorgänge vernachlässigt werden. Thermomechanische Spannungen, wie sie aufgrund der CTE unterschiede zwischen Substrat, Sinterschicht und Bauelement auftreten, können daher nicht innerhalb der Sinterschicht abgebaut oder aufgefangen werden. The use of a sintered compound as a connection partner could solve this problem of dislocation of the solder layer. This material is processed at a temperature below the melting point. The paste consists mainly of noble metal particles and / or metal compounds. Upon reaching the processing temperature, existing metal compounds are broken under the action of temperature and pressure, and thus contact with the joining partners, such as, for example, substrate and semiconductor, can take place. A high-temperature-stable sintered compound forms as a connecting layer. In such connecting layers, for example made of silver, creep processes can be neglected in comparison to soft solder joints. Thermo-mechanical stresses, as they occur due to the CTE differences between substrate, sintered layer and component, therefore, can not be degraded or collected within the sintered layer.
Der derzeitige Prozess für das Aufbringen einer Sinterpaste zur Ausbildung einer Verbindungsschicht ist der Schablonendruck. Die dadurch erzeugte Oberflächenstruktur ist jedoch in sich und auch zur Substratoberfläche nicht planar. Ein nachträgliches Andrücken des Grünlings der Sinterschicht erzeugt ebenfalls keine ebene Strukturebene und somit ist eine komplette vollflächige Anbindung des Halbleiters mittels geringem Druck nicht möglich.The current process for applying a sintering paste to form a tie layer is stencil printing. However, the surface structure produced thereby is not planar in itself and also to the substrate surface. A subsequent pressing of the green compact of the sintered layer also does not produce a planar structural plane and thus a complete full-surface connection of the semiconductor by means of low pressure is not possible.
Offenbarung der ErfindungDisclosure of the invention
Gegenstand der vorliegenden Erfindung ist eine Anordnung für elektronische Baugruppen, welche mindestens ein elektronisches Bauteil, insbesondere ein Halbleiterbauteil, mindestens einen Fügepartner und dazwischen mindestens eine Verbindungsschicht umfasst. Erfindungsgemäß ist die Verbindungsschicht eine metallische Sinterschicht, welche durch ein Dispens- oder InkJet-Verfahren aufgebracht ist, und welche eine Gradientenstruktur und/oder eine Abrundung in mindestens einem Eckbereich aufweist.The subject matter of the present invention is an arrangement for electronic assemblies which comprises at least one electronic component, in particular a semiconductor component, at least one joining partner and at least one connecting layer therebetween. According to the invention, the bonding layer is a metallic sintered layer, which is applied by a dispensing or inkjet method, and which has a gradient structure and / or a rounding in at least one corner region.
Als Abrundung in mindestens einem Eckbereich wird gemäß der vorliegenden Erfindung insbesondere eine regelmäßige oder unregelmäßige Flächenstruktur verstanden, wobei die Sinterschicht mindestens zwei benachbarte Seitenlinien umfasst, welche über mindestens einen gebogenen Verlauf miteinander verbunden sind. Hierbei kann der Radius des gebogenen Verlaufs entweder negativ oder positiv sein. In dem Fall, dass der Radius negativ ist, weist die Seitenlinie vor dem Zusammentreffen mit der benachbarten Seitenlinie im Eckbereich eine Einbuchtung auf im Sinne einer Materialausnehmung. In dem Fall eines bogenförmigen Verlaufs der Seitenlinie mit positivem Radius weist genau der Eckbereich des Zusammentreffens mit der benachbarten Seitenlinie eine Abrundung auf. Diese kann auch im Sinne einer Ausbuchtung des Eckbereichs ausgestaltet sein.As a rounding in at least one corner region is understood according to the present invention, in particular a regular or irregular surface structure, wherein the sintered layer comprises at least two adjacent side lines, which are connected to each other via at least one curved course. In this case, the radius of the curved course can be either negative or positive. In the event that the radius is negative, the side line before the meeting with the adjacent side line in the corner region has a recess in the sense of a material recess. In the case of an arcuate course of the positive radius sideline, just the corner area of the clash with the adjacent sideline will have a rounding. This can also be designed in the sense of a bulge of the corner.
Als Gradientenstruktur der Verbindungsschicht wird gemäß der vorliegenden Erfindung insbesondere eine regelmäßige oder unregelmäßige, bevorzugt eine geschlossene, Flächenstruktur verstanden, wobei die Schichtdicke und/oder die longitudinale Ausdehnung der Schicht in mindestens einem Bereich, insbesondere in einem Randbereich, graduiert abnehmend und/oder graduiert ansteigend ausgestaltet ist. According to the present invention, the gradient structure of the connecting layer is understood in particular to be a regular or irregular, preferably closed, surface structure, wherein the layer thickness and / or the longitudinal extent of the layer increases in at least one region, in particular in an edge region, decreasing in a graduated and / or graduated manner is designed.
Mit anderen Worten ist ein optimierter Kantenverlauf Kernpunkt der erfindungsgemäßen Sinterschicht, der durch Abrundungen bzw. Schichtdickegradienten erreicht wird, um dadurch die nachfolgend genannten Vorteile insbesondere hinsichtlich der thermomechanischen Eigenschaften der Sinterverbindung zu erzielen. In other words, an optimized edge course is the core point of the sintering layer according to the invention, which is achieved by rounding off or layer thickness gradients, in order to achieve the following advantages, in particular with regard to the thermomechanical properties of the sintered connection.
Durch die Gradientenstruktur, insbesondere in den Randbereichen, und/oder die spezielle Geometrie der Eckbereiche der Sinterverbindungsschicht ist eine Optimierung der Gestaltung der Sinterschicht in Bezug auf die auch innerhalb der Sinterschicht unterschiedlich auftretenden Spannungsspitzen möglich. Es wurde beobachtet, dass sich sowohl die Temperaturwechselbelastungen als auch die dadurch induzierten Spannungszustände gerade in den Eck- und Randbereichen anders verhalten können bzw. auftreten als in den übrigen Bereichen einer Sinterverbindungsschicht. Dies ist zusätzlich auch noch abhängig von vielen anderen Einflussgrößen, beispielsweise von dem Layout der Bestückung in einer ganzen Baugruppe. Durch eine spezielle Geometrie bzw. Gestaltung der Sinterschicht, wie sie durch die Gradientenstruktur und/oder durch die Abrundungen erfindungsgemäß als Reaktion auf diese unterschiedlich auftretenden Spannungen innerhalb der Verbindungsschicht vorgesehen sind, kann beispielsweise ein an die Fügefläche und das Bauteil-Layout optimierter Kantenverlauf vorgesehen werden. Damit kann die Lebensdauer des gesamten elektronischen Bauteils erhöht werden. Im Zentrum der vorliegenden Erfindung liegt daher mit anderen Worten der Gedanke, insbesondere den Kantenverlauf der Sinterverbindungsschicht derart zu gestalten, dass im Bereich von stark auftretenden Spannungsspitzen, welche thermomechanisch induziert sind, die Richtungsänderungen des Kantenverlaufs keine Sprünge bzw. keine großen Sprünge aufweisen. Dies wird durch Abrundungen und/oder durch die Gradientenstruktur realisiert, so dass in den Bereichen der Sinterschicht mit Spannungsspitzen der Kantenverlauf entschärft wird und der Übergang der Flächen in diesen Bereichen sanfter verläuft. Dies kann bei entsprechender Geometrie auch auf den Flächenübergang im Rand- bzw. Kantenbereich zum angebundenen Substrat oder Fügepartner angewendet werden, so dass auch hier ein reduzierter Belastungszustand für diesen Bereich und damit für die gesamte Anordnung entsteht. The gradient structure, in particular in the edge regions, and / or the special geometry of the corner regions of the sintered compound layer makes it possible to optimize the design of the sintered layer with respect to the voltage peaks that also occur differently within the sintered layer. It has been observed that both the thermal cycling stresses and the stress states induced thereby can behave differently in the corner and edge areas than in the remaining areas of a sintered compound layer. In addition, this is also dependent on many other factors, for example, the layout of the assembly in a whole assembly. By a special geometry or design of the sintered layer, as provided by the gradient structure and / or by the rounding according to the invention in response to these different voltages occurring within the bonding layer, for example, an optimized to the joint surface and the component layout edge profile can be provided , Thus, the life of the entire electronic component can be increased. In other words, in the center of the present invention, the idea is to design, in particular, the edge course of the sintered connection layer in such a way that in the region of strongly occurring stress peaks, which are thermomechanically induced, the changes in direction of the edge course have no jumps or no large jumps. This is realized by rounding and / or by the gradient structure, so that in the areas of the sintered layer with stress peaks the edge profile is defused and the transition of the surfaces in these areas runs more smoothly. With a corresponding geometry, this can also be applied to the surface transition in the edge or edge region to the connected substrate or joining partner, so that here too a reduced load condition is created for this region and thus for the entire assembly.
Mit der vorliegenden Erfindung ist es möglich, eine vollflächige Anbindung einer dünnen Sinterschicht beispielsweise an die Top-Metallisierung und/oder an die unbehandelte Oberfläche des Halbleiters herstellen zu können. Dadurch können unterschiedliche Strukturen auf einem Wafer und/oder einem anderen elektronischen Bauteil erzeugt werden und somit beispielsweise mehr Chipoberfläche effektiv genutzt werden. With the present invention, it is possible to be able to produce a full surface connection of a thin sintered layer, for example, to the top metallization and / or to the untreated surface of the semiconductor. As a result, different structures can be produced on a wafer and / or another electronic component, and thus, for example, more chip surface can be used effectively.
Insgesamt können durch die Kombination der Maßnahmen der vorliegenden Erfindung beispielsweise durch Reduzierung des Sinterdrucks und durch Inline-Fähigkeit und Schnelligkeit von Dispens- und/oder InkJet-Verfahren die Prozesskosten gesenkt werden.Overall, by combining the measures of the present invention, for example, by reducing the sintering pressure and by inline capability and speed of dispensing and / or inkjet process, the process costs can be reduced.
In einer Ausführungsform der Erfindung weist die Gradientenstruktur einen Gradienten der Dicke der Schicht derart auf, dass die Schichtdicke mindestens in Teilen des Randbereichs der Schicht kleiner ist als die Schichtdicke in der Mitte der Schicht.In one embodiment of the invention, the gradient structure has a gradient of the thickness of the layer in such a way that the layer thickness at least in part of the edge region of the layer is smaller than the layer thickness in the middle of the layer.
Diese mittig nach oben gerundete Ausgestaltung der Anbindungsfläche der Sinterschicht kann durch ein Vorsintern „fixiert“ werden, so dass bei einer nachfolgenden Anbindung an einen Fügepartner mittels eines weiteren Sintervorgangs bei nur geringem Sinterdruck die Gradientenstruktur erhalten bleibt. Aufgrund der balligen Ausbildung der Sinterschicht kommt es im mittleren Bereich zu einer vollflächigen Anbindung mit dem Fügepartner, während im Randbereich ein zum Randbereich zunehmender Spalt zwischen dem Fügepartner und der Anbindungsfläche der Sinterschicht entstehen kann. Auf diese Weise ergibt sich ein sanfter Übergang der Sinterschicht bis zum angebundenen Fügepartner, mit anderen Worten kein harter Sprung, wodurch wiederum Spannungsspitzen reduziert werden. This centrally upwardly rounded configuration of the connection surface of the sintered layer can be "fixed" by pre-sintering, so that in a subsequent connection to a joining partner by means of a further sintering process with only a low sintering pressure, the gradient structure is maintained. Due to the spherical formation of the sintered layer, a full-surface connection with the joining partner occurs in the middle region, while in the edge region an increasing gap between the joining partner and the bonding surface of the sintered layer can occur. This results in a smooth transition of the sintered layer to the connected joint partner, in other words no hard jump, which in turn reduces voltage spikes.
In einer weiteren Ausführungsform der Erfindung beträgt die Dicke der Verbindungsschicht in mindestens einem Teil des Randbereichs zwischen 300 nm und 600 nm. In a further embodiment of the invention, the thickness of the bonding layer in at least part of the edge region is between 300 nm and 600 nm.
In einer weiteren Ausgestaltung der Erfindung beträgt die Dicke der Verbindungsschicht in mindestens einem Teil der Mitte zwischen 500 nm und 10 µm.In a further embodiment of the invention, the thickness of the connecting layer in at least a part of the middle between 500 nm and 10 microns.
Durch Veränderung der Schichtdicke innerhalb der Sinterschichten, beispielsweise auf der Ober- und Unterseite bei doppelseitiger Anbindung eines Halbleiters, wird die thermische Spannung zusätzlich reduziert, die auf Halbleiter wirkt. Auch ein anderweitig geometrisch angepasstes Sinterschichtlayout, wie zum Beispiel ein runder Underprint mit zusätzlichen Ohren an den Ecken des Halbleiters, kann zu einer Spannungsreduzierung führen.By changing the layer thickness within the sintered layers, for example on the top and bottom in double-sided connection of a semiconductor, the thermal stress is additionally reduced, which acts on semiconductors. An otherwise geometrically adapted sintered layer layout, such as a round underprint with additional ears at the corners of the semiconductor, can lead to a reduction in stress.
Mittels der Ausführungsvarianten können die unterschiedlichen Ausdehnungskoeffizienten der Anordnung nicht verändert werden, da sie Materialkonstanten darstellen. Jedoch kann Einfluss darauf genommen werden, in welcher Art und in welcher Intensität sich deswegen Spannungsspitzen innerhalb der Anordnung und vor Allem innerhalb der einzelnen Schichten bilden können. Alle Ausführungsalternativen und auch die Kombination der Ausführungsalternativen tragen daher dazu bei, die Spannungsspitzen durch eine optimierte geometrische Ausführung der Sinterschicht zu reduzieren und die Anordnung zu entlasten. By means of the design variants, the different coefficients of expansion of the arrangement can not be changed since they represent material constants. However, it is possible to influence the type and intensity in which stress peaks can therefore form within the arrangement and, above all, within the individual layers. All alternative embodiments and also the combination of the alternative embodiments therefore contribute to reducing the voltage peaks by an optimized geometric design of the sintered layer and to relieve the arrangement.
In einer weiteren Ausführungsform der Erfindung ist das elektronische Substrat ein ungesägter oder gesägter Halbleiter oder ein abgepickter Halbleiter oder ein Wafer. In a further embodiment of the invention, the electronic substrate is an unswept or sawn semiconductor or a chipped semiconductor or wafer.
Vorteilhafterweise kann man einen abgepickten Halbleiter oder Wafer auf beiden gegenüberliegenden Seiten mit der erfindungsgemäßen Verbindungsschicht versehen, auch weil sie mittels Dispens- oder InkJet-Verfahren aufgebracht ist. Somit kann hier auf beiden Chipoberflächen jeweils eine definierte strukturierte Sinterschicht erzeugt werden. Advantageously, a chipped semiconductor or wafer can be provided on both opposite sides with the bonding layer according to the invention, also because it is applied by means of dispensing or inkjet methods. Thus, in each case a defined structured sintered layer can be produced here on both chip surfaces.
In einer weiteren Ausführungsform der Erfindung kann der Radius der Abrundung in mindestens einem Eckbereich der Verbindungsschicht zwischen 0,1 mm und 10 mm betragen. In a further embodiment of the invention, the radius of the rounding in at least one corner region of the connecting layer can be between 0.1 mm and 10 mm.
Gegenstand der Erfindung ist weiterhin ein Verfahren zur Herstellung einer Anordnung für elektronische Baugruppen umfassend die Schritte:
- – Bereitstellen mindestens eines elektronischen Bauteils, insbesondere eines Halbleiterbauteils,
- – Aufbringen einer Sinterpastenschicht auf die Fügefläche des elektronischen Bauteils mittels Dispens- oder InkJet-Verfahren und
- – Trocknen der aufgebrachten Sinterschicht und Ausbilden einer Gradientenstruktur und/oder Ausbilden von mindestens einer Abrundung im Eckbereich in der Verbindungsschicht,
- – Aufbringen eines Fügepartners auf die getrocknete Verbindungsschicht, und
- – Sintern der Verbindungsschicht unter endgültiger Ausbildung einer Gradientenstruktur und/oder einer Abrundung im Eckbereich der Verbindungsschicht.
- Providing at least one electronic component, in particular a semiconductor component,
- - Applying a sintered paste layer on the joining surface of the electronic component by means of dispensing or inkjet method and
- Drying the applied sintered layer and forming a gradient structure and / or forming at least one rounding in the corner region in the connecting layer,
- - Applying a joining partner on the dried compound layer, and
- Sintering of the bonding layer to finally form a gradient structure and / or a rounding in the corner region of the bonding layer.
Der Sinterprozess findet erfindungsgemäß in zwei aufeinanderfolgenden Schritten statt. Ein Trocknungsschritt dient zum Fixieren der Gradientenstruktur und/oder der Abrundung in mindestens einem Eckbereich der Verbindungsschicht. Hierbei ist ein Entweichen des Lösungsmittels aus der Sinterschicht vorgesehen. Die Trocknung wird bevorzugt unterhalb der Sintertemperatur, insbesondere bevorzugt unterhalb von 185 °C durchgeführt. Ein endgültiger Sinterschritt, bevorzugt mit vergleichsweise geringem Sinterdruck, beispielsweise kleiner als 5 MPa, dient der eigentlichen Versinterung des The sintering process according to the invention takes place in two successive steps. A drying step serves to fix the gradient structure and / or the rounding off in at least one corner region of the connecting layer. In this case, an escape of the solvent from the sintered layer is provided. The drying is preferably carried out below the sintering temperature, in particular preferably below 185 ° C. A final sintering step, preferably with a comparatively low sintering pressure, for example less than 5 MPa, serves for the actual sintering of the
Mittels des Ink-Jet-Verfahrens können sowohl gesägte und ungesägte Wafer als auch einzelne Halbleiterbauteile, zum Beispiel Dioden, IGBTs, Thyristoren, bestehend aus Silizium, Galliumnitrid oder Siliziumcarbid, mit einer Sinterpaste besprüht werden. Bei abgepickten oder losen Halbleiterbauteilen kann somit auf beiden Chipoberflächen jeweils eine definierte Sinterschicht erzeugt werden. By means of the ink-jet method, both sawn and unsized wafers as well as individual semiconductor components, for example diodes, IGBTs, thyristors consisting of silicon, gallium nitride or silicon carbide, can be sprayed with a sintering paste. In the case of chiped or loose semiconductor components, a defined sintered layer can thus be produced on both chip surfaces.
In einer Ausgestaltung des Verfahrens wird die Viskosität der Sinterpaste für einen Auftrag mittels Dispensverfahren bei einer Scherrate von 10 1/s und bei einer Temperatur von 23°C zwischen 160 Pa·s und 500 Pa·s, insbesondere zwischen 160 Pa·s und 250 Pa·s, eingestellt. In one embodiment of the method, the viscosity of the sintering paste for application by dispensing method at a shear rate of 10 1 / s and at a temperature of 23 ° C between 160 Pa · s and 500 Pa · s, in particular between 160 Pa · s and 250 Pa · s, set.
In einer weiteren Ausgestaltung des Verfahrens wird die Viskosität der Sinterpaste für einen Auftrag mittels InkJet-Verfahren bei einer Scherrate von 1000 1/s und bei einer Temperatur von 25°C kleiner als 110 mPa·s, insbesondere kleiner als 50 mPa·s, eingestellt. In a further embodiment of the method, the viscosity of the sintering paste for an application by means of inkjet method at a shear rate of 1000 1 / s and at a temperature of 25 ° C is less than 110 mPa · s, in particular less than 50 mPa · s adjusted ,
Die Einstellung der vorgenannten Viskositäten kann durch an sich bekannte Maßnahmen erfolgen. Bevorzugt wird die Viskosität durch Zugabe von Lösungsmittel, wie beispielsweise Terpineol, Stearinsäure, Ölsäure, und/oder durch Auswahl der mittleren Partikeldurchmesser der Metallpartikel der Sinterpaste vorgenommen. Die Viskositätsmessung kann insbesondere derart ausgeführt werden, dass sie der
Die mittleren Partikeldurchmesser (d50) können in diesem Zusammenhang insbesondere < 20 µm betragen. The average particle diameter (d 50 ) may be in this context in particular <20 microns.
In einer weiteren Ausgestaltung des Verfahrens wird das Aufbringen einer Sinterpastenschicht auf die Fügefläche des elektronischen Bauteils durch ein vorher festgelegtes Computerprogramm gesteuert. In a further embodiment of the method, the application of a sintered paste layer to the joining surface of the electronic component is controlled by a predetermined computer program.
In einer weiteren Ausgestaltung des Verfahrens erfolgt das Aufbringen einer Sinterpastenschicht auf die Fügefläche des elektronischen Bauteils durch eine vorher gefertigte Schablone. In a further embodiment of the method, the application of a sintered paste layer to the joining surface of the electronic component takes place by means of a previously produced template.
Mit den vorgenannten Maßnahmen wird vorteilhafterweise eine automatisierte Massenverarbeitung ermöglicht, die einen hohen Qualitätsstandart erreicht und zugleich durch vorherige Testbestimmungen optimierte Strukturen der Verbindungsschicht reproduzierbar auf die Fügefläche aufbringt. With the aforementioned measures, an automated mass processing is advantageously made possible, which achieves a high quality standard and at the same time applies reproducible structures of the connecting layer to the joining surface by means of previous test determinations.
In einer weiteren Ausgestaltung des Verfahrens erfolgt das Aufbringen einer Sinterpastenschicht auf die Fügefläche des elektronischen Bauteils in einer Nassschichtdicke zwischen 50 nm und 10 µm. In a further embodiment of the method, the application of a sintered paste layer to the joining surface of the electronic component takes place in a wet layer thickness between 50 nm and 10 μm.
In einer weiteren Ausgestaltung des Verfahrens erfolgt das Einstellen der Viskosität durch Zugabe von Lösungsmittel bis zu einem Gewichtsanteil von 83 %, insbesondere bis zu einem Gewichtsanteil von 40 %. In a further embodiment of the method, the viscosity is adjusted by adding solvent up to a weight fraction of 83%, in particular up to a weight fraction of 40%.
Geeignete Lösungsmittel sind beispielsweise Terpineol, Stearinsäure und/oder Ölsäure. Suitable solvents are, for example, terpineol, stearic acid and / or oleic acid.
Ein weiterer Gegenstand der Erfindung ist eine elektronische Baugruppe enthaltend mindestens ein elektronisches Bauteil insbesondere ein Halbleiterbauteil, mindestens einen Fügepartner und mindestens eine erfindungsgemäße Verbindungsschicht mit einer Gradientenstruktur und/oder Abrundungen in mindestens einem Eckbereich. Another object of the invention is an electronic assembly containing at least one electronic component in particular Semiconductor component, at least one joining partner and at least one bonding layer according to the invention having a gradient structure and / or rounding off in at least one corner region.
Ein weiterer Gegenstand der Erfindung ist die Verwendung einer erfindungsgemäßen Verbindungsschicht in der Mikroelektronik, insbesondere in der Fahrzeugelektronik und in der Solarelektronik, bevorzugt in hoch temperaturbelasteten Elektroniken.Another object of the invention is the use of a compound layer according to the invention in microelectronics, in particular in vehicle electronics and in solar electronics, preferably in high-temperature-loaded electronics.
Zeichnungen und BeispieleDrawings and examples
Weitere Vorteile und vorteilhafte Ausgestaltungen der erfindungsgemäßen Gegenstände werden durch die Zeichnungen veranschaulicht und in der nachfolgenden Beschreibung erläutert. Dabei ist zu beachten, dass die Zeichnungen nur beschreibenden Charakter haben und nicht dazu gedacht sind, die Erfindung in irgendeiner Form einzuschränken. Es zeigtFurther advantages and advantageous embodiments of the subject invention are illustrated by the drawings and explained in the following description. It should be noted that the drawings have only descriptive character and are not intended to limit the invention in any way. It shows
Die
ZITATE ENTHALTEN IN DER BESCHREIBUNG QUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.
Zitierte Nicht-PatentliteraturCited non-patent literature
- DIN 53018-1 (1976-03) [0026] DIN 53018-1 (1976-03) [0026]
Claims (14)
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DE201210221396 DE102012221396A1 (en) | 2012-11-22 | 2012-11-22 | Electronic arrangement for use in electronic assembly in e.g. motor vehicle electronics, has metallic sintered layer applied by dispensing or ink jet method, and connecting layer including gradient structure and/or rounding in corner region |
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DE201210221396 DE102012221396A1 (en) | 2012-11-22 | 2012-11-22 | Electronic arrangement for use in electronic assembly in e.g. motor vehicle electronics, has metallic sintered layer applied by dispensing or ink jet method, and connecting layer including gradient structure and/or rounding in corner region |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016071079A1 (en) * | 2014-11-07 | 2016-05-12 | Danfoss Silicon Power Gmbh | Power semiconductor contact structure and method for the production thereof |
WO2016071233A3 (en) * | 2014-11-07 | 2016-06-30 | Danfoss Silicon Power Gmbh | Electronic sandwich structure with two parts joined together by means of a sintering layer with alternating regions of higher and lower density and corresponding manufacturing method |
DE102016108000B3 (en) * | 2016-04-29 | 2016-12-15 | Danfoss Silicon Power Gmbh | Method for materially connecting a first component of a power semiconductor module to a second component of a power semiconductor module |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060267218A1 (en) * | 2004-06-29 | 2006-11-30 | Hitachi, Ltd. | Electronic part mounting method, semiconductor module, and semiconductor device |
DE102008055137A1 (en) * | 2008-12-23 | 2010-07-01 | Robert Bosch Gmbh | Electrical or electronic composite component and method for producing an electrical or electronic composite component |
DE102009020733A1 (en) * | 2009-05-11 | 2010-11-18 | Danfoss Silicon Power Gmbh | Process for the contact sintering of band-shaped contact elements |
DE102011016034A1 (en) * | 2011-04-04 | 2012-10-04 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Metal-containing composition, useful e.g. to produce contact structure, comprises electrically conductive metal powder and/or their alloy and/or organometallic compound of the conductive metal, first oxide material, and oxidizing agent |
-
2012
- 2012-11-22 DE DE201210221396 patent/DE102012221396A1/en not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060267218A1 (en) * | 2004-06-29 | 2006-11-30 | Hitachi, Ltd. | Electronic part mounting method, semiconductor module, and semiconductor device |
DE102008055137A1 (en) * | 2008-12-23 | 2010-07-01 | Robert Bosch Gmbh | Electrical or electronic composite component and method for producing an electrical or electronic composite component |
DE102009020733A1 (en) * | 2009-05-11 | 2010-11-18 | Danfoss Silicon Power Gmbh | Process for the contact sintering of band-shaped contact elements |
DE102011016034A1 (en) * | 2011-04-04 | 2012-10-04 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Metal-containing composition, useful e.g. to produce contact structure, comprises electrically conductive metal powder and/or their alloy and/or organometallic compound of the conductive metal, first oxide material, and oxidizing agent |
Non-Patent Citations (1)
Title |
---|
DIN 53018-1 (1976-03) |
Cited By (8)
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---|---|---|---|---|
WO2016071079A1 (en) * | 2014-11-07 | 2016-05-12 | Danfoss Silicon Power Gmbh | Power semiconductor contact structure and method for the production thereof |
WO2016071233A3 (en) * | 2014-11-07 | 2016-06-30 | Danfoss Silicon Power Gmbh | Electronic sandwich structure with two parts joined together by means of a sintering layer with alternating regions of higher and lower density and corresponding manufacturing method |
CN107112303A (en) * | 2014-11-07 | 2017-08-29 | 丹佛斯硅动力有限责任公司 | Power semiconductor contact structures and its production method |
US10079219B2 (en) | 2014-11-07 | 2018-09-18 | Danfoss Silicon Power Gmbh | Power semiconductor contact structure and method for the production thereof |
US10332858B2 (en) | 2014-11-07 | 2019-06-25 | Danfoss Silicon Power Gmbh | Electronic sandwich structure with two parts joined together by means of a sintering layer |
CN107112303B (en) * | 2014-11-07 | 2019-08-27 | 丹佛斯硅动力有限责任公司 | Power semiconductor contact structures and its production method |
DE102016108000B3 (en) * | 2016-04-29 | 2016-12-15 | Danfoss Silicon Power Gmbh | Method for materially connecting a first component of a power semiconductor module to a second component of a power semiconductor module |
US10438924B2 (en) | 2016-04-29 | 2019-10-08 | Danfoss Silicon Power Gmbh | Method for cohesively connecting a first component of a power semiconductor module to a second component of a power semiconductor module |
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