DE102011083684B3 - Barrier layer field effect transistor arrangement comprises node which is provided as drain terminal of arrangement, where another node is provided as source terminal of arrangement, where third node is provided as gate terminal - Google Patents

Barrier layer field effect transistor arrangement comprises node which is provided as drain terminal of arrangement, where another node is provided as source terminal of arrangement, where third node is provided as gate terminal Download PDF

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DE102011083684B3
DE102011083684B3 DE201110083684 DE102011083684A DE102011083684B3 DE 102011083684 B3 DE102011083684 B3 DE 102011083684B3 DE 201110083684 DE201110083684 DE 201110083684 DE 102011083684 A DE102011083684 A DE 102011083684A DE 102011083684 B3 DE102011083684 B3 DE 102011083684B3
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node
effect transistor
field effect
arrangement
terminal
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DE201110083684
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German (de)
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Ashot Melkonyan
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Siemens AG
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Siemens AG
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Priority to PCT/EP2012/067291 priority patent/WO2013045241A1/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/10—Modifications for increasing the maximum permissible switched voltage
    • H03K17/102—Modifications for increasing the maximum permissible switched voltage in field-effect transistor switches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/74—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/06—Modifications for ensuring a fully conducting state
    • H03K2017/066—Maximizing the OFF-resistance instead of minimizing the ON-resistance
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K2017/6875—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors using self-conductive, depletion FETs

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  • Power Conversion In General (AREA)
  • Electronic Switches (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The barrier layer field effect transistor arrangement (100) comprises a node (101) which is provided as a drain terminal of the arrangement. Another node (102) is provided as a source terminal of the arrangement. Third node (103) is provided as a gate terminal of the arrangement. A capacitor (30) is arranged between the fourth node (104) and the third node. A field effect transistor (20) is a metal-oxide-semiconductor field-effect transistor.

Description

Die Erfindung betrifft einen Aufbau zur Ansteuerung eines JFET-Bauteils sowie ein JFET-Bauteil mit einer integrierten Ansteuerung.The invention relates to a structure for driving a JFET device and a JFET device with an integrated drive.

Unipolare Feldeffekttransistoren wie JFETs (junction field effect transistors) und SITs (static induction transistors) mit kurzem Kanal und extrem hoher Dynamik werden zunehmend in Hochspannungs- und Hochleistungsanwendung eingesetzt. Speziell SiC-JFETs (siliziumkarbidbasierte JFETs) erfahren einen zunehmenden Einsatz in der Hochspannungstransformation.Unipolar field-effect transistors such as junction field effect transistors (JFETs) and short-channel SITs (static induction transistors) are becoming increasingly popular in high-voltage and high-power applications. Specifically, SiC JFETs (silicon carbide based JFETs) are increasingly being used in high voltage transformation.

Klassische JFETs sind stets selbstleitend, leiten also bei spannungsfreiem Gate den Strom zwischen Source-Anschluss und Drain-Anschluss. In manchen Anwendungen ist das problematisch, vor allem aus Sicherheitsgründen. Bei Situationen, in denen das Gate-Signal nicht vorhanden ist, beispielsweise beim Anschalten und Abschalten eines Geräts, aber vor allem bei Gerätefehlern ist die Verwendung von selbstsperrenden Schaltern kaum zu umgehen.Classic JFETs are always self-conducting, so when the gate is de-energized, they conduct the current between the source and drain. In some applications this is problematic, especially for security reasons. In situations where the gate signal is not present, for example, when turning on and off a device, but especially in case of device errors, the use of self-locking switches is hard to avoid.

Eine bekannte Lösung ist die Kaskodenschaltung. Allerdings kann diese Schaltung Probleme bei der Ansteuerung des Gates des Schalters erzeugen. Eine weitere Lösung ist aus der DE 10 2006 029 928 B3 bekannt. Bei der dortigen Schaltung wird der sich ergebende Transistor allerdings mit vier Pins betrieben, d. h. seine Ansteuerung entspricht nicht der „normalen” Ansteuerung eines Transistors mit drei Pins für Gate-, Drain- und Source-Anschluss.A known solution is the cascode circuit. However, this circuit can create problems in driving the gate of the switch. Another solution is from the DE 10 2006 029 928 B3 known. In the local circuit, however, the resulting transistor is operated with four pins, ie its control does not correspond to the "normal" driving a transistor with three pins for gate, drain and source connection.

Es ist Aufgabe der vorliegenden Erfindung, einen Aufbau zur Ansteuerung eines JFET-Bauteils anzugeben. Diese Aufgabe wird durch eine Anordnung mit den Merkmalen von Anspruch 1 gelöst.It is an object of the present invention to provide a structure for driving a JFET device. This object is achieved by an arrangement having the features of claim 1.

Die erfindungsgemäße Sperrschicht-Feldeffekttransistor-Anordnung umfasst

  • – einem ersten Knoten, der als Drain-Anschluss der Anordnung verwendbar ist,
  • – einem zweiten Knoten, der als Source-Anschluss der Anordnung verwendbar ist,
  • – einem dritten Knoten, der als Gate-Anschluss der Anordnung verwendbar ist,
  • – einem vierten Knoten, umfassend
  • – einen Sperrschicht-Feldeffekttransistor, dessen Drain-Anschluss mit dem ersten Knoten verbunden ist,
  • – einen weiteren Feldeffekttransistor in Serienschaltung zum Sperrschicht-Feldeffekttransistor, wobei der Source-Anschluss des weiteren Feldeffekttransistors mit dem zweiten Knoten verbunden ist,
  • – eine erste Diode, die zwischen dem zweiten und vierten Knoten angeordnet ist,
  • – eine zweite Diode, die zwischen dem vierten Knoten und dem Gate-Anschluss des weiteren Feldeffekttransistors angeordnet ist,
  • – einen Kondensator, der zwischen dem vierten Knoten und dem dritten Knoten angeordnet ist,
The junction field effect transistor arrangement according to the invention comprises
  • A first node usable as the drain of the device,
  • A second node usable as the source terminal of the device,
  • A third node usable as a gate terminal of the device,
  • A fourth node comprising
  • A junction field effect transistor whose drain terminal is connected to the first node,
  • A further field effect transistor connected in series with the junction field effect transistor, wherein the source terminal of the further field effect transistor is connected to the second node,
  • A first diode arranged between the second and fourth nodes,
  • A second diode, which is arranged between the fourth node and the gate terminal of the further field-effect transistor,
  • A capacitor arranged between the fourth node and the third node,

Die Knoten sind Schaltungsknoten der Sperrschicht-Feldeffekttransistor-Anordnung, die sich jeweils auf einem elektrischen Potential befinden. Die Knoten können auch elektrische Leiterabschnitte umfassen, sofern die elektrischen Widerstände dieser Leiterabschnitte vernachlässigbar sind.The nodes are circuit nodes of the junction field effect transistor arrangement, each of which is at an electrical potential. The nodes may also comprise electrical conductor sections, provided that the electrical resistances of these conductor sections are negligible.

Die Sperrschicht-Feldeffekttransistor-Anordnung bildet zusammengenommen vorteilhaft ein Bauteil, das wie ein Transistor angeschlossen und verwendet werden kann; dabei bildet der erste Knoten den Drain-Anschluss dieses Transistors, der zweite Knoten den Source-Anschluss dieses Transistors und der dritte Knoten den Gate-Anschluss. Das Bauteil basiert auf einem Sperrschicht-Feldeffekttransistor, agiert dabei aber vorteilhaft – im Gegensatz zum eigentlichen Sperrschicht-Feldeffekttransistor – selbstsperrend.The junction field effect transistor arrangement, taken together, advantageously forms a component which can be connected and used like a transistor; In this case, the first node forms the drain terminal of this transistor, the second node forms the source terminal of this transistor and the third node forms the gate terminal. The component is based on a junction field-effect transistor, but it acts advantageous - in contrast to the actual junction field effect transistor - self-locking.

Bevorzugt ist der weitere Feldeffekttransistor ein MOSFET ist. Weiterhin kann vorteilhaft zwischen dem Gate-Anschluss des weiteren Feldeffekttransistors und dem zweiten Knoten eine Parallelschaltung aus einem Widerstand und einem zweiten Kondensator angeordnet sein. Der Widerstand ermöglicht vorteilhaft ein schnelles Entladen der Gate-Kapazität des weiteren Feldeffekttransistors.Preferably, the further field effect transistor is a MOSFET. Furthermore, a parallel circuit comprising a resistor and a second capacitor can advantageously be arranged between the gate terminal of the further field effect transistor and the second node. The resistor advantageously makes it possible to rapidly discharge the gate capacitance of the further field effect transistor.

Ein bevorzugtes, jedoch keinesfalls einschränkendes Ausführungsbeispiel für die Erfindung wird nunmehr anhand der Figur näher erläutert. Dabei sind die Merkmale schematisiert dargestellt. 1 zeigt eine beispielhafte Sperrschicht-Feldeffekttransistor-Anordnung 100. Diese umfasst einen ersten bis vierten Knoten 101...104. Dabei stellen der erste bis dritte Knoten 101...103 Verbindungen nach außen dar. Der erste Knoten 101 ist als Drain-Anschluss der Sperrschicht-Feldeffekttransistor-Anordnung 100 verwendbar, der zweite Knoten 102 als Source-Anschluss der Sperrschicht-Feldeffekttransistor-Anordnung 100 und der dritte Knoten 103 als Gate-Anschluss.A preferred, but by no means limiting embodiment of the invention will now be explained in more detail with reference to FIG. The features are shown schematically. 1 shows an exemplary junction field effect transistor arrangement 100 , This includes a first to fourth node 101 ... 104 , Here are the first to third nodes 101 ... 103 Outward connections. The first node 101 is as a drain terminal of the junction field effect transistor arrangement 100 usable, the second node 102 as the source terminal of the junction field effect transistor arrangement 100 and the third node 103 as gate connection.

Die Beschaltung ist in Figur mit einer beispielhaften allgemeinen Spannungsquelle 200, einer Last 220, die mit der Spannungsquelle 200 und dem ersten Knoten 101 verbunden ist, und einer Steuerspannungsquelle 210 dargestellt. Die Steuerspannungsquelle 210 ist mit dem dritten Knoten 103, also mit dem Gate-Anschluss der Feldeffekttransistor-Anordnung 100 verbunden.The circuitry is shown in FIG. 1 with an exemplary general voltage source 200 , a load 220 connected to the voltage source 200 and the first node 101 is connected, and a control voltage source 210 shown. The control voltage source 210 is with the third node 103 , ie with the gate terminal of the field effect transistor arrangement 100 connected.

Intern umfasst die Feldeffekttransistor-Anordnung 100 einen SiC-basierten Vertical-Junction FET (VJFET) 10. Dieser ist auf Seiten seines Drain-Anschlusses mit dem ersten Knoten 101 verbunden. Seitens des Source-Anschlusses ist der FET 10 mit dem Drain-Anschluss eines MOSFET 20 verbunden. Der Source-Anschluss des MOSFET 20 wiederum ist mit dem zweiten Knoten 102 verbunden, der den Source-Anschluss der Feldeffekttransistor-Anordnung 100 darstellt.Internally includes the field effect transistor arrangement 100 a SiC-based vertical junction FET (VJFET) 10 , This is on the side of its drain connection to the first node 101 connected. On the side of the source terminal is the FET 10 to the drain terminal of a MOSFET 20 connected. The source terminal of the MOSFET 20 turn is with the second node 102 connected to the source terminal of the field effect transistor arrangement 100 represents.

Der Gate-Anschluss des FET 10 ist direkt mit dem dritten Knoten 103 verbunden. Zwischen dem dritten Knoten 103 und dem vierten Knoten ist ein Kondensator 30 angeordnet. Zwischen dem vierten Knoten 104 und dem zweiten Knoten 102 ist eine erste Diode 40 angeordnet, sperrend aus Sicht des vierten Knoten. Zwischen dem vierten Knoten 104 und dem Gate-Anschluss des MOSFET 20 ist eine zweite Diode 50 angeordnet, sperrend aus Sicht des Gate-Anschlusses des MOSFET 20. Zwischen dem Gate-Anschluss des MOSFET 20 und dem zweiten Knoten 102 ist eine Parallelschaltung aus einem Widerstand 60 und einem Kondensator 70 angeordnet. Der Widerstand ermöglicht vorteilhaft ein schnelles Entladen der Gate-Kapazität des MOSFET 20.The gate terminal of the FET 10 is directly to the third node 103 connected. Between the third node 103 and the fourth node is a capacitor 30 arranged. Between the fourth node 104 and the second node 102 is a first diode 40 arranged, blocking from the point of view of the fourth node. Between the fourth node 104 and the gate terminal of the MOSFET 20 is a second diode 50 arranged, blocking as seen from the gate terminal of the MOSFET 20 , Between the gate terminal of the MOSFET 20 and the second node 102 is a parallel connection of a resistor 60 and a capacitor 70 arranged. The resistor advantageously allows a fast discharge of the gate capacitance of the MOSFET 20 ,

Die Steuerspannungsquelle 210 ist eine Pulsspannungsquelle, die eine getaktete Spannung für zumindest eine begrenzte Zeitspanne liefert. Aus der Pulsspannung wird über den Kondensator 30 Energie zum Einschalten des MOSFET 20 bezogen. Nach einigen Zyklen der Pulsspannung ist die Spannung am Gate des MOSFET 20 auf das nötige Schwellniveau angestiegen und der MOSFET 20 wird und bleibt danach leitend. Danach arbeitet Sperrschicht-Feldeffekttransistor-Anordnung 100 im Wesentlichen wie der einzelne FET 10. Bei einem Ausfall der Pulsspannungsquelle oder Abschalten der Pulsspannung fällt die Spannung am Gate des MOSFET 20 wieder zurück auf Null und der MOSFET 20 schaltet ab. Dadurch wird vorteilhaft die selbstsperrende Eigenschaft der gesamten Sperrschicht-Feldeffekttransistor-Anordnung 100 erreicht.The control voltage source 210 is a pulse voltage source that provides a pulsed voltage for at least a limited amount of time. From the pulse voltage is through the capacitor 30 Power to turn on the MOSFET 20 based. After several cycles of the pulse voltage, the voltage is at the gate of the MOSFET 20 increased to the required threshold level and the MOSFET 20 becomes and remains conductive afterwards. Thereafter, the junction field effect transistor arrangement operates 100 essentially like the single FET 10 , If the pulse voltage source fails or the pulse voltage is switched off, the voltage at the gate of the MOSFET drops 20 back to zero and the MOSFET 20 turns off. As a result, the self-blocking characteristic of the entire junction field-effect transistor arrangement becomes advantageous 100 reached.

Vorteilhaft verhält sich die Feldeffekttransistor-Anordnung 100 weitgehend wie der FET 10, wobei jedoch bei Ausfall der Steuerspannung am Gate, d. h. bei spannungsfreiem Gate eine Stromleitung zwischen dem Drain-Anschluss, d. h. dem ersten Knoten 101 und Source-Anschluss, d. h. dem zweiten Knoten 102 unterbunden wird. Mit anderen Worten verhält sich die Feldeffekttransistor-Anordnung 100 vorteilhaft wie ein selbstsperrender („normally-off”) Transistor.Advantageously, the field effect transistor arrangement behaves 100 largely like the FET 10 However, in the case of failure of the control voltage at the gate, ie in a de-energized gate, a power line between the drain terminal, ie the first node 101 and source port, ie the second node 102 is prevented. In other words, the field effect transistor arrangement behaves 100 advantageous as a normally-off transistor.

Claims (3)

Sperrschicht-Feldeffekttransistor-Anordnung (100) mit – einem ersten Knoten (101), der als Drain-Anschluss der Anordnung verwendbar ist, – einem zweiten Knoten (102), der als Source-Anschluss der Anordnung verwendbar ist, – einem dritten Knoten (103), der als Gate-Anschluss der Anordnung verwendbar ist, – einem vierten Knoten (104), umfassend – einen Sperrschicht-Feldeffekttransistor (10), dessen Drain-Anschluss mit dem ersten Knoten (101) verbunden ist, – einen weiteren Feldeffekttransistor (20) in Serienschaltung zum Sperrschicht-Feldeffekttransistor (10), wobei der Source-Anschluss des weiteren Feldeffekttransistors (20) mit dem zweiten Knoten verbunden ist, – eine erste Diode (40), die zwischen dem zweiten und vierten Knoten (102, 104) angeordnet ist, – eine zweite Diode (50), die zwischen dem vierten Knoten (104) und dem Gate-Anschluss des weiteren Feldeffekttransistors (20) angeordnet ist, – einen Kondensator (30), der zwischen dem vierten Knoten (104) und dem dritten Knoten (103) angeordnet ist.Junction Field Effect Transistor Device ( 100 ) with - a first node ( 101 ) usable as the drain of the device, - a second node ( 102 ) usable as the source terminal of the device, - a third node ( 103 ) usable as the gate terminal of the device, - a fourth node ( 104 ), comprising - a junction field effect transistor ( 10 ) whose drain connection to the first node ( 101 ), - another field effect transistor ( 20 ) in series connection to the junction field effect transistor ( 10 ), wherein the source terminal of the further field effect transistor ( 20 ) is connected to the second node, - a first diode ( 40 ) between the second and fourth nodes ( 102 . 104 ), - a second diode ( 50 ) between the fourth node ( 104 ) and the gate terminal of the further field effect transistor ( 20 ), - a capacitor ( 30 ), which is between the fourth node ( 104 ) and the third node ( 103 ) is arranged. Sperrschicht-Feldeffekttransistor-Anordnung (100) gemäß Anspruch 1, wobei der weitere Feldeffekttransistor (20) ein MOSFET ist.Junction Field Effect Transistor Device ( 100 ) according to claim 1, wherein the further field effect transistor ( 20 ) is a MOSFET. Sperrschicht-Feldeffekttransistor-Anordnung gemäß Anspruch 1 oder 2, wobei zwischen dem Gate-Anschluss des weiteren Feldeffekttransistors (20) und dem zweiten Knoten (102) eine Parallelschaltung aus einem Widerstand (60) und einem zweiten Kondensator (70) angeordnet ist.Junction field effect transistor arrangement according to claim 1 or 2, wherein between the gate terminal of the further field effect transistor ( 20 ) and the second node ( 102 ) a parallel connection of a resistor ( 60 ) and a second capacitor ( 70 ) is arranged.
DE201110083684 2011-09-29 2011-09-29 Barrier layer field effect transistor arrangement comprises node which is provided as drain terminal of arrangement, where another node is provided as source terminal of arrangement, where third node is provided as gate terminal Expired - Fee Related DE102011083684B3 (en)

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DE201110083684 DE102011083684B3 (en) 2011-09-29 2011-09-29 Barrier layer field effect transistor arrangement comprises node which is provided as drain terminal of arrangement, where another node is provided as source terminal of arrangement, where third node is provided as gate terminal
PCT/EP2012/067291 WO2013045241A1 (en) 2011-09-29 2012-09-05 Circuit structure for controlling a jfet component

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Cited By (4)

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EP2693639A1 (en) * 2012-07-30 2014-02-05 Nxp B.V. Cascoded semiconductor devices
EP2782134A3 (en) * 2013-03-21 2016-11-30 Kabushiki Kaisha Toshiba Semiconductor device
WO2018096263A1 (en) * 2016-11-25 2018-05-31 Exagan Power circuit switching device having a passive protection circuit
EP3218977A4 (en) * 2014-11-12 2018-06-20 Texas Instruments Incorporated Output discharge techniques for load switches

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CN110546870B (en) 2017-04-28 2021-06-08 Abb瑞士股份有限公司 Power module, control method and use thereof, and power module stack

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DE102006029928B3 (en) * 2006-06-29 2007-09-06 Siemens Ag Electronic switching device for switching high electric current, has isolating unit connected between control connection of switching unit and load supply of another switching unit, where isolation unit decouples switching units

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US7737762B2 (en) * 2006-09-12 2010-06-15 Energate Inc Solid-state switch
DE102008034688B4 (en) * 2008-07-25 2010-08-12 Siemens Aktiengesellschaft Switching device for switching at a high operating voltage

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Publication number Priority date Publication date Assignee Title
DE102006029928B3 (en) * 2006-06-29 2007-09-06 Siemens Ag Electronic switching device for switching high electric current, has isolating unit connected between control connection of switching unit and load supply of another switching unit, where isolation unit decouples switching units

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2693639A1 (en) * 2012-07-30 2014-02-05 Nxp B.V. Cascoded semiconductor devices
US8847235B2 (en) 2012-07-30 2014-09-30 Nxp B.V. Cascoded semiconductor devices
EP2782134A3 (en) * 2013-03-21 2016-11-30 Kabushiki Kaisha Toshiba Semiconductor device
US9653449B2 (en) 2013-03-21 2017-05-16 Kabushiki Kaisha Toshiba Cascoded semiconductor device
EP3218977A4 (en) * 2014-11-12 2018-06-20 Texas Instruments Incorporated Output discharge techniques for load switches
US10187055B2 (en) 2014-11-12 2019-01-22 Texas Instruments Incorporated Output discharge techniques for load switches
WO2018096263A1 (en) * 2016-11-25 2018-05-31 Exagan Power circuit switching device having a passive protection circuit
FR3059490A1 (en) * 2016-11-25 2018-06-01 Exagan DEVICE FOR SWITCHING A POWER CIRCUIT HAVING A PASSIVE PROTECTION CIRCUIT
US11101791B2 (en) 2016-11-25 2021-08-24 Exagan Power circuit switching device having a passive protection circuit

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