DE102010011128A1 - Frequency synthesizer for time base generator of level measuring device, has fractional frequency divider operated with periodical divider factor sequences whose periodical length is shorter in specified range - Google Patents

Abstract

The synthesizer has a phase locked loop including a phase frequency discriminator, a rule oscillator, a fractional frequency divider and a loop filter. The fractional frequency divider is provided between a reference oscillator i.e. quartz oscillator, and the phase locked loop. The fractional frequency divider is operated with periodical divider factor sequences, and periodical length (T) of the divider factor sequences is shorter in range of 10 bit or less than 10bit, such that failure based on the divider factor sequences is restrained by the loop filter.

Description

The invention relates to a frequency synthesizer, in particular for a time base generator of a level gauge, which operates on the radar principle, for outputting a first frequency signal having the frequency f ₁ and a second frequency signal having the frequency f ₂ , wherein the first frequency signal with the frequency f ₁ and the second frequency signal having the frequency f _{2 has} a small difference frequency .DELTA.f, with a reference oscillator, a phase locked loop and a logic element, wherein the phase locked loop comprises a phase frequency discriminator, a control oscillator, a first fractional frequency divider and a loop filter.

Such frequency synthesizers are particularly suitable for a time base generator of a level gauge, which operates on the radar principle. Such a level gauge can, for. B. based on the TDR measurement principle (Time Domain Reflectometry). The TDR measuring principle is z. B. in the field of cable testing known and has similarities with the functioning of radar devices. In a TDR level gauge, an extremely short electrical pulse guided by one or two substantially straight electrical conductors is emitted into a container containing a medium, such as a liquid, powder or granules, the level of which is determined should. The short electrical pulse emitted through the two conductors into the container is reflected at the surface of the medium, and the reflected portion of the short electrical pulse is re-detected by a transmitter of the meter. The reflected portion of the short electrical pulse depends on and increases with the dielectric constant of the medium. The duration of the signal is proportional to the distance of the transmitter to the surface of the medium in the container. Changing environmental conditions, such as increasing or decreasing ambient pressure or increasing or decreasing temperature, will not affect the accuracy of the TDR level gauge. In addition, the duration of the signal is independent of the dielectric constant of the medium at which the reflection takes place.

The TDR measuring principle is thus based on measuring the - under certain circumstances very short - transit times of an electromagnetic signal. If the container is almost completely filled with the medium, so that the surface of the medium, for example, only 15 cm below the transmitter of the TDR level gauge, the total distance of the electromagnetic signal from the transmitter to the surface of the medium and back is only 30 cm, which Runtime of the short electrical pulse of 1 ns corresponds. In order to be able to measure such short transit times, a sampling method is used for which two high-frequency signals are generated which have a predetermined low frequency difference with respect to one another. A measurement is then performed such that the measurement is started at a time 0 at which the two frequency signals oscillate in phase. In this case, the higher-frequency oscillating signal gives the clock for the transmission of the actual measurement signal, d. H. short electric pulse, into the tank. So z. B. always generated at the beginning of a period of the higher frequency oscillating signal, a short electrical pulse and sent out into the container. The lower-frequency oscillating signal lags the higher-frequency oscillating signal by a certain small amount per oscillation period. Thus, a temporal raster is defined which represents a digital time base and with which the transit time of the short electrical pulse emitted into the container and reflected on the surface of the medium is measured.

In the DE 102 44 348 A1 a frequency synthesizer is described in which a reference oscillator generates an input frequency signal which is available to the control oscillator after an integer division as a reference frequency, and the control oscillator is connected with its control frequency to this reference frequency such that the input frequency signal and the control frequency have a small frequency difference to each other without having to accept a small comparison frequency. The phase-locked loop therefore has a comparatively high degree of dynamics. In practice, however, it has been found that the stability achievable with such a frequency synthesizer and the associated noise behavior are still in need of improvement.

From the DE 10 2004 063 935 A1 a frequency synthesizer is known in which the reference oscillator is followed by a first integer frequency divider and the control oscillator is followed by a second integer frequency divider, the frequency divider serving the output of the first frequency signal and the second frequency signal. This ensures that the two oscillators, namely the reference oscillator and the control oscillator, disturb each other significantly less by coupling effects, since the two oscillators can now work with widely different frequencies. At the mixer used for generating a mixed difference frequency signal, which provides an input signal for the phase frequency discriminator used of the phase locked loop of the frequency synthesizer, however, are high Requirements concerning the noise properties. This results in a considerable analog circuit complexity.

Furthermore, from the DE 196 40 071 A1 a frequency synthesizer operating according to the principle of fractional frequency synthesis, in which a fractional frequency divider is used in the feedback path of the phase locked loop.

A fractional frequency divider operates instead of a constant integer divider factor with a time-varying divider factor that is switched between two integer values, commonly denoted N and N + 1. The effective divider factor thus results from the time average of the variable divisor factor and thus lies between these two integer values. The sequence in which the divider factor is switched between the two values is called the divider factor sequence. For the time average N _{means of} the divisor factor, the following relationship arises: N _means = N + y / x. (Equation 1)

Here, y / x represents the relative divider factor and N represents the integer divider factor. The smallest achievable frequency difference Δf between two frequency signals which can be generated by the fractional frequency divider - not simultaneously but successively - results in: Δf = f ₂ -f ₁ = f _ref 1 / x. (Equation 2)

Accordingly, compared to the use of non-fractional frequency dividers, in which the smallest achievable frequency spacing .DELTA.f between two adjacent frequency _signals corresponding to the reference frequency f.sub.ref does not correspond to one another, the advantage that significantly smaller frequency spacings .DELTA.f can be achieved. Likewise, with the same frequency spacing Δf, an x times larger reference frequency f _ref can be selected, as a result of which the phase noise of the frequency synthesizer is markedly improved. In order to achieve the stated advantages, the frequency dividers are usually realized in a fully fractional manner in the prior art. This means that the divider factor sequence must have a very long periodicity. Thus, however, interferences in the frequency range which are dependent on the divider factor sequence come almost as close to the useful signal. This can in turn be compensated for by suppressing these carrier-related disturbances with the aid of multistage delta-sigma filters. However, there are high demands on the linearity of the components of the phase-locked loop, which in turn results in a considerable amount of analog circuitry.

Thus, it is the object of the invention to provide a frequency synthesizer of the aforementioned type, which is easy and inexpensive to produce despite good control behavior and good interference suppression.

The previously derived and indicated object is achieved on the basis of the frequency synthesizer described above in that the frequency synthesizer has a second fractional frequency divider between the reference oscillator and the phase-locked loop. This means that the second fractional frequency divider, the input frequency signal with the frequency f _{01 of} the reference oscillator is provided, the second fractional frequency divider by dividing the frequency of the input frequency signal with the frequency f ₀₁ by the fractional divider factor R generates the reference frequency signal with the frequency f _ref and this feeds the phase frequency discriminator of the phase locked loop. The control oscillator of the phase-locked loop generates a control frequency signal with the frequency f ₀₂ , which is also supplied to the phase frequency discriminator after dividing the frequency by the fractional divider factor L of the first fractional frequency divider. The output of the Phasenfrequenzdiskriminators is processed by a loop filter. The output of the loop filter in turn serves to control the control oscillator, the z. B. can be configured as a voltage-controlled oscillator. The first fractional frequency divider and the second fractional frequency divider are preferably controlled by the same logic element, thereby saving a second logic element. For the smallest achievable frequency difference .DELTA.f between the first frequency signal to be output at the frequency f ₁ and the second frequency signal to be output at the frequency f ₂ , which in the case described above directly to the input frequency signal with the frequency f ₀₁ and the control frequency signal with the frequency f ₀₂ correspond, results in: .DELTA.f = f ₂ - f ₁ = f ₀₁ - f ₀₂ = L / f ₀₁ - f ₀₁ = L - R / Rf _01. (Equation 3)

It should be noted in Equation 3 that, in contrast to Equation 2, this is actually the frequency spacing of regularly generated frequency signals. According to an advantageous A further development of the invention provides for the first fractional frequency divider and the second fractional frequency divider to be operated with periodic divider factor sequences. According to a particularly advantageous development of the invention, it is provided that the period lengths T of the divider factor sequences are short. According to a particularly advantageous development of the invention, it is provided that the period lengths T of the divider factor sequences are so short that the disturbances dependent on the divider factor sequences are suppressed by the loop filter. Short period lengths have the advantage that the interference caused by the divider factor sequences in the frequency range are far away from the carrier signal and thus, for. B. by the loop filter, can be easily suppressed. Many fractional dividers are operated in practice with period lengths of 24 bits to 32 bits. With the frequency synthesizer according to the invention, however, fractional dividers can be used which have period lengths of only 10 bits (or less)

According to an advantageous embodiment of the invention, it is provided that the divider factor sequences during a period as many changes of the divider factor, so that possible high-frequency noise are generated, which are widely spaced from the frequencies of interest of the frequency signals. In principle, however, the frequency synthesizer described here with two fractional frequency dividers can also be operated with divider factor sequences of long period length.

According to an advantageous development of the invention, it is provided that the first fractional frequency divider and the second fractional frequency divider operate with divider factor sequences of the same period length T. This ensures that only disturbances occur at frequencies which correspond to an integer multiple of the first interference frequency f _stub , which is calculated as follows:

In particular, no disturbances occur which are below the first interference frequency f _disturb .

According to an advantageous embodiment of the invention, it is provided that a first frequency divider is provided, wherein the first frequency divider for supplying the input frequency signal with the frequency f _{01 is} connected to the reference oscillator and the first frequency divider is used to output the first frequency signal with the frequency f ₁ . According to a particularly advantageous embodiment of the invention, it is provided that a second frequency divider is provided, wherein the second frequency divider for supplying the control frequency signal with the frequency f _{02 is} connected to the control oscillator and the second frequency divider is used to output the second frequency signal with the frequency f ₂ , According to a particularly advantageous development of the invention, it is provided that the first frequency divider and / or the second frequency divider are operated in integers. In the event that both a first integer frequency divider with the divider factor V ₁ and a second integer frequency divider are provided with the divider factor V ₂ , results for the smallest achievable frequency difference .DELTA.f between the first output frequency signal with the frequency f ₁ and the second output frequency signal with the frequency f _{2 the} following relationship:

By a sufficiently small choice of the counter and a sufficiently large choice of the denominator, thus an extremely small frequency spacing .DELTA.f can be achieved.

According to an advantageous development of the invention, it is provided that the reference oscillator is a quartz oscillator.

In particular, there are now a variety of ways to design and further develop the frequency synthesizer according to the invention. Reference is made to the claims subordinate to claim 1 and to the following detailed description of preferred embodiments of the invention with reference to the drawings.

In the drawing shows

1 schematically a divider factor sequence of the frequency synthesizer according to the invention according to a preferred embodiment and

2 schematically the circuit construction of the frequency synthesizer according to the invention with reference to another preferred embodiment.

1 shows a periodic divisor factor sequence with the period length T. The time is plotted on the abscissa and the divisor factor is plotted on the ordinate. By way of example, the period starting at time T and ending at time 2T is considered. At the beginning of this period the divisor factor is N and at the end of the period the divider factor is N + 1. Within this period, the divider factor is switched once from N to N + 1. The time period in which the divider factor N is + 1 with y, so that the relative time proportion in which the divider factor N + 1 is given to the quotient of y and x, where x denotes the total length of the period.

The 2 shows schematically the circuit construction of the frequency synthesizer according to the invention. The frequency synthesizer has a reference oscillator 1 for generating an input frequency signal with the frequency f ₀₁ , a phase locked loop 2 and a logic element 3 on. The phase locked loop 2 includes a phase frequency discriminator 4 , a control oscillator 5 , a first fractional frequency divider 6 and a loop filter 7 , The output signal of the Phasenfrequenzdiskriminators 4 serves as input to the loop filter 7 whose output signal in turn is the control oscillator 5 controls. At the output of the control oscillator 5 results in the control frequency signal with the frequency f ₀₂ . This control frequency signal with the frequency f ₀₂ is via the first fractional frequency divider 6 which divides the frequency of the control frequency signal f ₀₂ by the fractional divider factor L, the phase frequency discriminator 4 provided as input signal. Another input signal is the phase frequency discriminator 4 the reference frequency signal with the frequency f _ref provided. This reference frequency signal with the frequency f _ref is through the second fractional frequency divider 8th generates the frequency of the input frequency signal with the frequency f _{01 of} the reference oscillator 1 divided by the fractional divisor factor R. The first fractional frequency divider 6 and the second fractional frequency divider 8th be through the logic element 3 controlled. The first frequency divider 9 generated from the input frequency signal with the frequency f _{01 of} the reference oscillator 1 by dividing by the divider factor V _1, the first output signal with the frequency f ₁ . The second frequency divider 10 generated from the control frequency signal with the frequency f _{02 of} the control oscillator 5 by dividing by the divider factor V ₂ the second output signal with the frequency f ₂ .

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• DE 10244348 A1 [0004]
• DE 102004063935 A1 [0005]
• DE 19640071 A1 [0006]

Claims (10)

Frequency synthesizer, in particular for a Zeitbasisgenerator a level gauge, which operates on the radar principle, for outputting a first frequency signal with the frequency f ₁ and a second frequency signal with the frequency f ₂ , wherein the first frequency signal with the frequency f ₁ and the second frequency signal with the Frequency f _{2 have} a low difference frequency .DELTA.f, with a reference oscillator ( 1 ), a phase locked loop ( 2 ) and a logic element ( 3 ), the phase locked loop ( 2 ) a phase frequency discriminator ( 4 ), a control oscillator ( 5 ), a first fractional frequency divider ( 6 ) and a loop filter ( 7 ) characterized in that the frequency synthesizer comprises a second fractional frequency divider ( 8th ) between the reference oscillator ( 1 ) and the phase locked loop ( 2 ) having. Frequency synthesizer according to claim 1, characterized in that the first fractional frequency divider ( 6 ) and the second fractional frequency divider ( 8th ) are operated with periodic divider factor sequences. Frequency synthesizer according to claim 2, characterized in that the period lengths T of the divider factor sequences are short, in particular 10 bits or less than 10 bits. Frequency synthesizer according to Claim 3, characterized in that the period lengths T of the divider factor sequences are so short that the errors dependent on the divider factor sequences are limited by the loop filter (15). 7 ) are suppressed. Frequency synthesizer according to one of claims 2 to 4, characterized in that the divider factor sequences have as many changes of the divider factor during a period. Frequency synthesizer according to one of claims 2 to 5, characterized in that the first fractional frequency divider ( 6 ) and the second fractional frequency divider ( 8th ) are operated with divider factor sequences of the same period. Frequency synthesizer according to one of Claims 1 to 6, characterized in that a first frequency divider ( 9 ), the first frequency divider ( 9 ) for supplying the input frequency signal with the frequency f ₀₁ to the reference oscillator ( 1 ) and the first frequency divider ( 9 ) is used to output the first frequency signal at the frequency f ₁ . Frequency synthesizer according to one of claims 1 to 7, characterized in that a second frequency divider ( 10 ), the second frequency divider ( 10 ) for supplying the control frequency signal with the frequency f ₀₂ to the control oscillator ( 5 ) and the second frequency divider ( 10 ) is used to output the second frequency signal at the frequency f ₂ . Frequency synthesizer according to one of claims 7 to 8, characterized in that the first frequency divider ( 9 ) and / or the second frequency divider ( 10 ) are operated in whole numbers. Frequency synthesizer according to one of Claims 1 to 9, characterized in that the reference oscillator ( 1 ) is a quartz oscillator.

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