DE102008046724A1 - Semiconductor device for converting alternating current into direct current produced by alternator arranged in vehicle, has solder connection section connecting part of device with semiconductor element - Google Patents
Semiconductor device for converting alternating current into direct current produced by alternator arranged in vehicle, has solder connection section connecting part of device with semiconductor element Download PDFInfo
- Publication number
- DE102008046724A1 DE102008046724A1 DE102008046724A DE102008046724A DE102008046724A1 DE 102008046724 A1 DE102008046724 A1 DE 102008046724A1 DE 102008046724 A DE102008046724 A DE 102008046724A DE 102008046724 A DE102008046724 A DE 102008046724A DE 102008046724 A1 DE102008046724 A1 DE 102008046724A1
- Authority
- DE
- Germany
- Prior art keywords
- layer
- semiconductor device
- semiconductor element
- solder
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/325—Material
- H01L2224/32505—Material outside the bonding interface, e.g. in the bulk of the layer connector
- H01L2224/32506—Material outside the bonding interface, e.g. in the bulk of the layer connector comprising an eutectic alloy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/325—Material
- H01L2224/32505—Material outside the bonding interface, e.g. in the bulk of the layer connector
- H01L2224/32507—Material outside the bonding interface, e.g. in the bulk of the layer connector comprising an intermetallic compound
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83399—Material
- H01L2224/834—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/83438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/83455—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
- H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01012—Magnesium [Mg]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01015—Phosphorus [P]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01028—Nickel [Ni]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0103—Zinc [Zn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19043—Component type being a resistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
Description
Die vorliegende Erfindung betrifft eine Halbleitervorrichtung, bei der zum Auflöten von Elementen ein bleifreies Lot verwendet wird. Insbesondere betrifft die vorliegende Erfindung eine Halbleitervorrichtung für eine Hochtemperaturumgebung wie zum Beispiel eine Halbleitervorrichtung, die dazu verwendet wird, den von einem in einem Fahrzeug angeordneten Wechselstromgenerator (Drehstromgenerator) erzeugten Wechselstrom in einen Gleichstrom umzuwandeln.The The present invention relates to a semiconductor device in which used to solder elements a lead-free solder becomes. In particular, the present invention relates to a semiconductor device for a high-temperature environment such as a semiconductor device, which is used by the one arranged in a vehicle Alternator (alternator) generated alternating current to convert into a direct current.
Hinsichtlich
einer Halbleitervorrichtung für einen Betrieb bei hohen
Temperaturen, etwa einer Halbleitervorrichtung, die dazu verwendet
wird, den von dem in einem Fahrzeug befindlichen Wechselstromgenerator mit
einem vom Motor des Fahrzeugs in Drehung versetzten Anker erzeugten
Wechselstrom in einen Gleichstrom umzuwandeln, ist ein Aufbau bekannt,
bei dem darauf geachtet wird, die thermischen Spannungen aufgrund
des Unterschieds zwischen dem thermischen Ausdehnungskoeffizient
eines Halbleiterelements und dem einer Elektrode zu verringern,
damit das Halbleiterelement Temperaturzyklen mit stark wechselnden
Temperaturen aushält (
Aus Umweltschutzgründen werden jedoch Halbleitervorrichtungen bevorzugt, bei denen das Verbindungsmaterial kein Blei enthält, das die Umwelt stark belastet. Es gibt zwar bleifreies Lot mit einem Schmelzpunkt in der Nähe des Schmelzpunktes eines hoch bleihaltigen Lots, es sind dies Lote auf Goldbasis wie Au-20Sn (eutektisch, 280°C), Au-12Ge (eutektisch, 356°C), Au-3,15Si (eutektisch, 363°C). Diese Lote sind jedoch extrem teuer. Au-20Sn mit dem kleinsten Goldgehalt ist ein Hartlot und daher nicht dafür geeignet, Spannungen auszugleichen, wenn ein Halbleiterelement mit einer großen Fläche befestigt wird, so daß die Gefahr besteht, daß das Halbleiterelement bricht.Out Environmental concerns, however, are semiconductor devices preferred in which the bonding material contains no lead, which heavily pollutes the environment. There is unleaded solder with one Melting point near the melting point of a high lead-containing lots, these are gold-based solders such as Au-20Sn (eutectic, 280 ° C), Au-12Ge (eutectic, 356 ° C), Au-3.15Si (eutectic, 363 ° C). These solders are extremely expensive. Au-20Sn with the smallest gold content is a braze and therefore not suitable for compensating voltages when a semiconductor element is fastened with a large surface, so that the There is a risk that the semiconductor element breaks.
Zum Anbringen von Bauteilen auf einem Substrat wird oft ein Lot auf Sn-Basis für mittlere Temperaturen verwendet, das einen Schmelzpunkt von 200°C oder darüber aufweist. In einer Umgebung mit Temperaturen bis zu 150°C ergibt sich damit eine zuverlässige Verbindung. Wenn sich ein derart angelötetes Bauteil im Betrieb für längere Zeit in einer Umgebung mit einer Temperatur von 200°C und mehr befindet, treten jedoch an der Verbindungsfläche Grenzflächenreaktionen auf, und die Zuverlässigkeit der Verbindung nimmt durch das Entstehen von Hohlräumen, dem Entstehen von intermetallischen Verbindungen und dergleichen ab. Es ist bekannt, daß in Hochleistungsmodulen wie LEDs und dergleichen das Entstehen von Hohlräumen an der Grenzfläche aufgrund der Wärmeerzeugung durch den fließenden Strom die Zuverlässigkeit der Verbindung herabsetzt.To the Attaching components to a substrate often becomes a solder Sn base used for medium temperatures, the one Melting point of 200 ° C or above. In an environment with temperatures up to 150 ° C results thus a reliable connection. When there is a such soldered component in operation for longer Time in an environment with a temperature of 200 ° C and is more, but interfacial reactions occur at the interface on, and the reliability of the connection decreases through the Formation of cavities, the emergence of intermetallic Connections and the like. It is known that in High power modules such as LEDs and the like, the emergence of Cavities at the interface due to heat generation by the flowing current the reliability minimizes the connection.
Zum
Unterdrücken der Grenzflächenreaktionen bei einem
Lot auf Sn-Basis schlägt die
Bei diesen bekannten Vorgehensweisen ergeben sich jedoch die im folgenden angeführten Nachteile, weshalb die jeweiligen Anordnungen nicht für Halbleitervorrichtungen geeignet sind, die in einer Umgebung mit hoher Temperatur betrieben werden oder die aufgrund des Erzeugens von Wärme durch den durch die Halbleitervorrichtung fließenden Strom sehr heiß werden. Insbesondere sind die bekannten Anordnungen nicht für Halbleitervorrichtungen oder Hochleistungsmodule geeignet, die in einem in einem Fahrzeug angeordneten Wechselstromgenerator (Drehstromgenerator) verwendet werden.at However, these known procedures are given below mentioned disadvantages, which is why the respective arrangements are not suitable for semiconductor devices that are in operating in a high temperature environment or due to generating heat by the semiconductor device flowing electricity get very hot. Especially The known arrangements are not for semiconductor devices or high performance modules suitable in one in a vehicle arranged alternator (alternator) used become.
Bei
der Anordnung nach der
Im
Falle der
Wenn
wie im Fall einer Drehstromgeneratordiode durch diese beim Schalten
des elektrischen Stroms ein Strom von einigen zehn Ampere fließt,
entstehen im Verbindungsabschnitt des Halbleiterelements Hohlräume
der in der
Aufgabe der vorliegenden Erfindung ist es, eine Halbleitervorrichtung mit einem bleifreien Lot zu schaffen, das keine großen Umweltprobleme verursacht, mit geringen Kosten hergestellt werden kann und bei dem die Zuverlässigkeit der Verbindungen hoch ist, auch wenn die Halbleitervorrichtung für lange Zeit bei einer hohen Temperatur von 200°C und mehr verwendet wird. Es sollen keine Hohlräume im Verbindungsabschnitt eines Halbleiterelements der Halbleitervorrichtung entstehen, wenn ein großer elektrischer Strom fließt.task The present invention is a semiconductor device with To create a lead-free solder that does not cause major environmental problems caused, can be manufactured at low cost and at the reliability of the links is high, too When the semiconductor device for a long time at a high temperature of 200 ° C and more is used. It should no cavities in the connecting portion of a semiconductor element of the semiconductor device arise when a large electrical Electricity flows.
Diese Aufgabe wird mit der Halbleitervorrichtung nach Patentanspruch 1 bzw. 8 gelöst. Die Unteransprüche beschreiben vorteilhafte Ausgestaltungen der erfindungsgemäßen Halbleitervorrichtung.These Task is with the semiconductor device according to claim 1 or 8 solved. Describe the dependent claims advantageous embodiments of the invention Semiconductor device.
Die vorliegende Erfindung umfaßt somit (1) eine Halbleitervorrichtung mit einem Bestandteil mit einem darauf ange ordneten Halbleiterelement und mit einem ersten Verbindungsabschnitt, der den Bestandteil der Halbleitervorrichtung mit dem Halbleiterelement verbindet, wobei der erste Verbindungsabschnitt umfaßt: Eine erste Schicht auf Ni-Basis, die auf dem Bestandteil der Halbleitervorrichtung ausgebildet ist; eine erste intermetallische Verbindungsschicht, die auf der ersten Schicht auf Ni-Basis ausgebildet ist und die als Hauptkomponente eine Cu-Ni-Sn-Verbindung enthält; und eine Schicht aus einem Lot auf Sn-Basis zwischen der ersten intermetallischen Verbindungsschicht und dem Halbleiterelement.The The present invention thus comprises (1) a semiconductor device with a component having a semiconductor element disposed thereon and a first connection portion forming part of the semiconductor device connects to the semiconductor element, wherein the first connecting portion comprises: a first Ni-based layer deposited on the component the semiconductor device is formed; a first intermetallic Bonding layer formed on the first Ni-based layer and containing as the main component a Cu-Ni-Sn compound; and a Sn-based solder layer between the first intermetallic Connection layer and the semiconductor element.
Bei der Halbleitervorrichtung mit diesem Aufbau verbindet der erste Verbindungsabschnitt die erste Schicht auf Ni-Basis auf dem Bestandteil der Halbleitervorrichtung und das Halbleiterelement mit einem Lot aus Sn mit 1 bis 10 Massen-% Cu und 0,05 bis 0,5 Massen Ni.at the semiconductor device having this structure connects the first one Connecting portion The first Ni-based layer on the component of the semiconductor device and the semiconductor element with a solder Sn with 1 to 10 mass% Cu and 0.05 to 0.5 mass Ni.
Die vorliegende Erfindung umfaßt desgleichen (2) eine Halbleitervorrichtung mit einem Halbleiterelement; mit einem Elektrodenkörper, der über ein erstes Ausgleichsmaterial mit einer ersten Oberfläche des Halbleiterelements verbunden ist; mit einer Zuleitungselektrode, die über ein zweites Ausgleichsmaterial mit einer zweiten Oberfläche des Halbleiterelements verbunden ist; und mit einem ersten Verbindungsabschnitt, der die erste Oberfläche des Halbleiterelements mit dem ersten Ausgleichsmaterial verbindet. Das erste Ausgleichsmaterial umfaßt eine erste Schicht auf Ni-Basis, die auf der ersten Oberfläche des Halbleiterelements ausgebildet ist; eine erste intermetallische Verbindungsschicht, die auf der ersten Schicht auf Ni-Basis ausgebildet ist und die als Hauptkomponente eine Cu-Ni-Sn-Verbindung enthält; und eine Lotschicht auf Sn-Basis zwischen der ersten intermetallischen Verbindungsschicht und dem ersten Ausgleichsmaterial.The The present invention also includes (2) a semiconductor device with a semiconductor element; with an electrode body, the first over a first compensation material with a first Surface of the semiconductor element is connected; with a Supply electrode, which has a second compensation material connected to a second surface of the semiconductor element is; and a first connecting portion having the first surface of the semiconductor element connects to the first compensating material. The first compensating material comprises a first layer Ni-base formed on the first surface of the semiconductor element is; a first intermetallic compound layer on the first Ni-base layer is formed and as the main component a Cu-Ni-Sn compound; and a solder layer Sn basis between the first intermetallic compound layer and the first balancing material.
Bei der Halbleitervorrichtung mit diesem Aufbau verbindet der erste Verbindungsabschnitt die erste Schicht auf Ni-Basis, die auf der ersten Oberfläche des Halbleiterelements ausgebildet ist, und das erste Ausgleichsmaterial mit einem Lot aus Sn mit 1 bis 10 Massen Cu und 0,05 bis 0,5 Massen-% Ni.at the semiconductor device having this structure connects the first one Connecting portion of the first Ni-based layer, which on the first surface of the semiconductor element is formed, and the first balance material with a solder of Sn with 1 to 10 masses of Cu and 0.05 to 0.5 mass% of Ni.
Bei der Halbleitervorrichtung mit diesem Aufbau ist der Verbindungsabschnitt des Elektrodenkörpers mit dem ersten Ausgleichsmaterial durch ein Lot auf Sn-Basis verbunden, das bei einer Temperatur von 200°C eine Cu6Sn5-Phase enthält.at The semiconductor device having this structure is the connecting portion of the electrode body with the first compensating material connected by a Sn-based solder at a temperature of 200 ° C contains a Cu6Sn5 phase.
Bei der Halbleitervorrichtung mit diesem Aufbau kann der Bestandteil der Halbleitervorrichtung ein Basissubstrat sein.In the semiconductor device having this structure, the constituent of the semiconductor device may be Ba be sissubstrat.
Bei der Halbleitervorrichtung mit diesem Aufbau kann der Bestandteil der Halbleitervorrichtung ein Leiterrahmen sein, der elektrisch mit dem Halbleiterelement verbunden ist.at The semiconductor device of this structure may be the constituent the semiconductor device may be a lead frame that is electrically is connected to the semiconductor element.
Ausführungsformen der Erfindung werden im folgenden anhand der Zeichnungen näher erläutert. Es zeigen:embodiments The invention will be described below with reference to the drawings explained. Show it:
Zuerst soll nun der Aufbau des Löt-Verbindungsabschnitts erläutert werden, der ein wesentliches Merkmal der beschriebenen Halbleitervorrichtung darstellt.First will now be explained the structure of the solder joint section which is an essential feature of the described semiconductor device represents.
Wie
in der
Es
wird nun die optimale Zusammensetzung für den Löt-Verbindungsabschnitt
Die
Um
bei der Ausbildung der Lötverbindung eine gute Benetzbarkeit
zu erhalten, ist es vorteilhaft, ein Lot mit einer Zusammensetzung
zu wählen, deren Liquiduslinientemperatur gleich der Verbindungstemperatur ist
oder darunter liegt. Wenn jedoch die Cu-Konzentration im Lot größer
ist als 10 Massen-%, liegt die Liquiduslinientemperatur bei 450°C
und mehr, so daß die Gefahr besteht, daß ein aufzubringendes
Halbleiterelement beim Herstellen der Verbindung Schaden nimmt.
Wenn dagegen die Cu-Konzentration im Lot kleiner ist als 1 Massen-%,
wird auf der Ni-Schicht keine Diffusions-Sperrschicht ausgebildet,
so daß wie bei dem in der
Unter dem Gesichtspunkt der Zunahme der Dicke der Ni-Schicht liegt für die optimale Lotzusammensetzung zum Ausbilden des Löt-Verbindungsabschnitts die Cu-Konzentration daher im Bereich von größer 1 Massen-% und kleiner 10 Massen-%. Vorzugsweise liegt die Cu-Konzentration im Bereich von 5 bis 10 Massen-%.Under the viewpoint of the increase in the thickness of the Ni layer is for the optimum solder composition for forming the solder joint portion the Cu concentration therefore in the range of greater 1 mass% and less than 10 mass%. Preferably, the Cu concentration is in the range of 5 to 10 mass%.
Die
Wie
in der
Die
Durch die Zugabe von Ni zu der optimalen Zusammensetzung des Lots zum Ausbilden des Löt-Verbindungsabschnitts kann somit das Entstehen von Hohlräumen unterdrückt werden. Vorzugsweise liegt die Ni-Konzentration im Bereich von 0,05 Massen-% bis 0,5 Massen-%.By the addition of Ni to the optimum composition of the solder Forming the solder joint portion may thus be the Emergence of cavities are suppressed. Preferably the Ni concentration is in the range of 0.05 mass% to 0.5 Mass%.
Es
reicht dabei aus, auf dem anzuschließenden Material nur
die Schicht auf Ni-Basis aus Ni, Ni-P, Ni-B und dergleichen durch
Beschichten, etwa Galvanisieren, aufzubringen. Es ist somit nicht
nötig, wie im Fall der eingangs genannten
Bei
der in der
Wie
in der
Durch das Auskristallisieren, Ausfällen oder Bewegen der Cu-Ni-Sn-Verbindung in dem Lot auf Sn-Basis zum Ausbilden der Sperrschicht hängt die Dicke der Sperrschicht vom Anteil der Verbindung im Lot ab, so daß durch geeignetes Einstellen des Verbindungsanteils leicht eine Sperrschicht mit einer optimalen Dicke hergestellt werden kann.By crystallization, precipitation or agitation of the Cu-Ni-Sn compound in the Sn-based solder for forming the barrier layer the thickness of the barrier layer depends on the proportion of the compound in the solder, so that by appropriately adjusting the connection rate easily a barrier layer can be made with an optimal thickness can.
Das
Lot kann nicht nur durch das Auflegen der Lötfolie
Es wird nun eine erste Ausführungsform der erfindungsgemäßen Halbleitervorrichtung mit einem Löt-Verbindungsabschnitt der beschriebenen Art erläutert.It Now, a first embodiment of the invention Semiconductor device with a solder joint portion explained the type described.
Wie
der
Das
Sn-Lot kann jeweils von einer Lötfolie gebildet werden.
Zur Ausbildung der Verbindungen werden die Lötfolien und
die obigen Elemente in der beschriebenen Reihenfolge in eine Positionierlehre
eingesetzt. In einem Ofen werden bei einer Temperatur von 380°C
für 4 Minuten in einer reduzierenden Atmosphäre,
bei der zu Stickstoff 50% Wasserstoff zugemischt wird, die Elemente
des Stapels miteinander verbunden. Dann wird am Umfang des Verbindungsabschnitts
Silikongummi
An
jedem Löt-Verbindungsabschnitt
Bei
der ersten Ausführungsform der
Wenn
bei dem Verbindungsabschnitt des Halbleiterelements ein Sn-Lot mit
(1–10) Massen Cu und (0,05 bis 0,5) Massen-% Ni verwendet
wird, in dem auch bei großen elektrischen Strömen
so gut wie keine Hohlräume entstehen, und für
die anderen Verbindungsabschnitte ein Lot auf Sn-Basis verwendet
wird, das einen großen Anteil an Cu6-Sn5-Phase enthält,
etwa die in der
Bei der vorliegenden Ausführungsform wurde die ganze Struktur in einem Zug hergestellt. Die Struktur kann jedoch auch in einzelne Teile aufgeteilt werden. Wenn im Temperaturbereich von Raumtemperatur bis 200°C sowohl Lot auf Sn- Basis, das die Cu6Sn5-Phase enthält, als auch das Sn-Lot mit (1–10) Massen-% Cu und (0,05 bis 0,5) Massen-% Ni verwendet werden, wird der Verbindungsprozeß vorteilhaft im Temperaturbereich von 220°C bis 450°C und in einer reduzierenden Atmosphäre oder einer inerten Atmosphäre ausgeführt. Dadurch wird die bevorzugte Verbindung erhalten, ohne daß ein Fließen auftritt. Wenn die Verbindung in einer inerten Atmosphäre erhalten wird, kann eine Oxidation des Lots und der einzelnen Bauteile verhindert werden, so daß eine gute Verbindung entsteht.at In the present embodiment, the whole structure made in a train. However, the structure can also be individual Parts are split. When in the temperature range of room temperature up to 200 ° C both Sn-based solder, the Cu6Sn5 phase contains, as well as the Sn solder with (1-10) mass% Cu and (0.05 to 0.5) mass% Ni are used, the bonding process is advantageous in the temperature range from 220 ° C to 450 ° C and in a reducing atmosphere or an inert atmosphere executed. This gives the preferred compound without a flow occurs. If the connection obtained in an inert atmosphere, oxidation may occur the solder and the individual components are prevented, so that a good connection arises.
Bei
der vorliegenden Ausführungsform wurde zwischen dem Halbleiterelement
Für
das Augleichsmaterial
Als
thermisches Ausgleichsmaterial
Die
in der
Die
in der
Durch
das Anwenden der Löt-Verbindungsstruktur bei der Verbindung
des Halbleiterelements wird bei der vorliegenden Ausführungsform
eine Grenzflächenreaktion in einer Umgebung, die sich auf
hoher Temperatur befindet, verhindert und das Entstehen von Hohlräumen
im Verbindungsabschnitt durch die Wärme, die der fließende
Strom erzeugt, unterdrückt. Es reicht dabei aus, wenn die
Löt-Verbindungsstruktur der
Die
vierte Ausführungsform der Halbleitervorrichtung ist wie
in der
Außer
bei den beschriebenen Ausführungsformen kann der Löt-Verbindungsabschnitt,
der mit der eine Cu-Ni-Sn-Verbindung als Hauptkomponente enthaltenden
Verbindung eine Sperrschicht zwischen der Schicht aus einem Lot
auf Sn-Basis und der Schicht auf Ni-Basis bildet, auch bei verschiedenen
anderen Halbleitervorrichtungen angewendet werden. Zum Beispiel
kann bei der Halbleitervorrichtung der
Bei allen Ausführungsformen kann die Schicht auf Ni-Basis aus Ni, Ni-P oder Ni-B bestehen, und auf der Schicht auf Ni-Basis kann sich wenigstens eine weitere Schicht aus Au, Ag oder Pd befinden. Das Au, Ag oder Pd diffundiert bei der Herstellung der Lötverbindung vollständig in das Lot, so daß die Benetzbarkeit erhöht wird, ohne daß die Ausbildung der Verbindungsschicht auf der Schicht auf Ni-Basis davon beeinträchtigt wird.at In all embodiments, the Ni-based layer may be made Ni, Ni-P or Ni-B can exist, and on the Ni-based layer At least one further layer of Au, Ag or Pd are located. The Au, Ag or Pd diffuses in the production of the solder joint completely in the solder, so that the wettability is increased without the formation of the compound layer on the Ni-based layer thereof.
In der Tabelle 1 sind die Ergebnisse hinsichtlich der Zuverlässigkeit des Löt-Verbindungsabschnitts an experimentellen Beispielen und Vergleichsbeispielen aufgelistet, wobei die Verbindungsfestigkeit zwischen dem Halbleiterelement und dem jeweils damit verbundenen Bestandteil der Halbleitervorrichtung nach einem Temperaturzyklustest und nach einer bestimmen Verweilzeit bei hoher Temperatur an der Halbleitervorrichtung der ersten Ausführungsform gemessen wurden. Wenn die Verbindungsfestigkeit nach dem Test 80% oder mehr der Verbindungsfestigkeit vor dem Test entspricht, wird sie mit "G" für "Gut" bezeichnet, und wenn die Verbindungsfestigkeit nach dem Test weniger als 80% beträgt, wird sie mit "B" für "Bad" oder "Schlecht" bezeichnet. Hinsichtlich des thermischen Ermüdungstests wird die thermische Widerstandsfluktuation, wenn sie 200% oder weniger der thermischen Widerstandsfluktuation zu Beginn beträgt, mit "G" bezeichnet, und wenn die thermische Widerstandsfluktuation größer ist als 200% der thermischen Widerstandsfluktuation zu Beginn, wird sie mit "B" bezeichnet.In Table 1 shows the results in terms of reliability of the solder joint section on experimental examples and Comparative Examples, wherein the bond strength between the semiconductor element and the respectively connected thereto Component of the semiconductor device after a temperature cycle test and after a certain residence time at high temperature at the Semiconductor device of the first embodiment measured were. When the bond strength after the test is 80% or more the connection strength before the test, it is with "G" for "good", and if the connection strength less than 80% after the test, it is labeled "B" for "Bad" or "Bad". Regarding the thermal fatigue tests, the thermal resistance fluctuation, if it is 200% or less of the thermal resistance fluctuation is at the beginning, denoted by "G", and when the thermal Resistance fluctuation is greater than 200% of thermal resistance fluctuation at the beginning, it is called "B".
Experimentelle Beispiele 1 bis 4:Experimental Examples 1 to 4:
In den experimentellen Beispielen 1 bis 4 wurde nach dem Temperaturzyklustest, bei dem ein Temperaturzyklus von –40°C (30 min) und 200°C (30 min) 500 mal wiederholt wurde, festgestellt, daß der Löt-Verbindungsabschnitt eine Verbindungsfestigkeit aufweist, die 80% oder mehr der Verbindungsfestigkeit zu Beginn der Untersuchung beträgt. Auch nach einer Verweilzeit von 1000 Stunden bei 200°C weisen alle Halbleitervorrichtungen der Beispiele 1 bis 4 eine Verbindungsfestigkeit auf, die 80% oder mehr der Verbindungsfestigkeit zu Beginn beträgt. Die thermische Widerstandsfluktuation vor dem Test und nach dem Test liegt im Bereich von 10%. Nach dem thermischen Ermüdungstest, bei dem das Halbleiterelement durch Zuführen eines elektrischen Stroms von 35 A auf 200°C aufgeheizt und durch Abschalten des elektrischen Stroms wieder auf 50°C abgekühlt wird und der 10.000 mal wiederholt wird, liegt die thermische Widerstandsfluktuation innerhalb von 200% der thermischen Widerstandsfluktuation zu Beginn.In the Experimental Examples 1 to 4, after the temperature cycle test in which a temperature cycle of -40 ° C (30 min) and 200 ° C (30 min) was repeated 500 times, it was found that the soldering coupler has a bond strength which is 80% or more of the bond strength at the beginning of the test. Even after a residence time of 1000 hours at 200 ° C, all the semiconductor devices of Examples 1 to 4 have a bonding strength which is 80% or more of the bonding strength at the beginning. The thermal resistance fluctuation before the test and after the test is in the range of 10%. After the thermal fatigue test in which the semiconductor element is heated by supplying an electric current of 35 A to 200 ° C and cooled by switching off the electric current to 50 ° C and repeated 10,000 times, the thermal resistance fluctuation is within 200%. the thermal resistance fluctuation at the beginning.
Experimentelle Beispiele 5 bis 8:Experimental Examples 5 to 8:
In den experimentellen Beispielen 5 bis 8 wurde nach dem Temperaturzyklustest, bei dem ein Temperaturzyklus von –40°C (30 min) und 200°C (30 min) 500 mal wiederholt wurde, ebenfalls festgestellt, daß der Löt-Verbindungsabschnitt eine Verbindungsfestigkeit aufweist, die 80% oder mehr der Verbindungsfestigkeit zu Beginn der Untersuchung beträgt. Auch nach einer Verweilzeit von 1000 Stunden bei 200°C weisen alle Halbleitervorrichtungen der Beispiele 5 bis 8 eine Verbindungsfestigkeit auf, die 80% oder mehr der Verbindungsfestigkeit zu Beginn beträgt. Die thermische Widerstandsfluktuation vor dem Test und nach dem Test liegt im Bereich von 10%. Nach dem thermischen Ermüdungstest, bei dem das Halbleiterelement durch Zuführen eines elektrischen Stroms von 35 A auf 200°C aufgeheizt und durch Abschalten des elektrischen Stroms wieder auf 50°C abgekühlt wird und der 10.000 mal wiederholt wird, liegt die thermische Widerstandsfluktuation innerhalb von 200% der thermischen Widerstandsfluktuation zu Beginn.In Experimental Examples 5 to 8 after the temperature cycling test, where a temperature cycle of -40 ° C (30 min) and 200 ° C (30 min) was repeated 500 times, also found that the solder joint section has a bonding strength that is 80% or more of the bonding strength The beginning of the investigation is. Even after a stay 1000 hours at 200 ° C, all semiconductor devices Examples 5-8 have a bond strength that is 80% or more of the bond strength at the beginning is. The thermal Resistance fluctuation before the test and after the test is in the range of 10%. After the thermal fatigue test, in which the Semiconductor element by supplying an electric current heated from 35 A to 200 ° C and by switching off the cooled electric current back to 50 ° C. and repeated 10,000 times, the thermal resistance fluctuation is within of 200% of the thermal resistance fluctuation at the beginning.
Experimentelles Beispiel 9:Experimental Example 9:
In dem experimentellen Beispiel 9 wurde nach dem Temperaturzyklustest, bei dem ein Temperaturzyklus von –40°C (30 min) und 200°C (30 min) 500 mal wiederholt wurde, auch festgestellt, daß der Löt-Verbindungsabschnitt eine Verbindungsfestigkeit aufweist, die 80% oder mehr der Verbindungsfestigkeit zu Beginn der Untersuchung beträgt. Auch nach einer Verweilzeit von 1000 Stunden bei 200°C weist die Halbleitervorrichtung des Beispiels 9 eine Verbindungsfestigkeit auf, die 80% oder mehr der Verbindungsfestigkeit zu Beginn beträgt. Die thermische Widerstandsfluktuation vor dem Test und nach dem Test liegt im Bereich von 10%. Nach dem thermischen Ermüdungstest, bei dem das Halbleiterelement durch Zuführen eines elektrischen Stroms von 35 A auf 200°C aufgeheizt und durch Abschalten des elektrischen Stroms wieder auf 50°C abgekühlt wird und der 10.000 mal wiederholt wird, liegt die thermische Widerstandsfluktuation innerhalb von 200% der thermischen Widerstandsfluktuation zu Beginn.In Experimental example 9, after the temperature cycle test, where a temperature cycle of -40 ° C (30 min) and 200 ° C (30 min) was repeated 500 times, also noted the solder joint portion has a bonding strength which has 80% or more of the joining strength at the beginning of Examination is. Even after a residence time of 1000 Hours at 200 ° C, the semiconductor device of the example 9 has a bonding strength that is 80% or more of joint strength at the beginning amounts to. The thermal resistance fluctuation before the test and after the test is in the range of 10%. After this thermal fatigue test, in which the semiconductor element by supplying an electric current of 35 A to 200 ° C heated up and by switching off the electric power back on 50 ° C is cooled and repeated 10,000 times is, the thermal resistance fluctuation is within 200% of the thermal resistance fluctuation at the beginning.
Experimentelle Beispiele 10 bis 12:Experimental Examples 10 to 12:
In den experimentellen Beispielen 10 bis 12 wurde nach dem Temperaturzyklustest, bei dem ein Temperaturzyklus von –40°C (30 min) und 200°C (30 min) 500 mal wiederholt wurde, wiederum festgestellt, daß der Löt-Verbindungsabschnitt eine Verbindungsfestigkeit aufweist, die 80% oder mehr der Verbindungsfestigkeit zu Beginn der Untersuchung beträgt. Auch nach einer Verweilzeit von 1000 Stunden bei 200°C weisen alle Halbleitervorrichtungen der Beispiele 10 bis 12 eine Verbindungsfestigkeit auf, die 80% oder mehr der Verbindungsfestigkeit zu Beginn beträgt. Die thermische Widerstandsfluktuation vor dem Test und nach dem Test liegt im Bereich von 10%. Nach dem thermischen Ermüdungstest, bei dem das Halbleiterelement durch Zuführen eines elektrischen Stroms von 35 A auf 200°C aufgeheizt und durch Abschalten des elektrischen Stroms wieder auf 50°C abgekühlt wird und der 10.000 mal wiederholt wird, liegt die thermische Widerstandsfluktuation innerhalb von 200% der thermischen Widerstandsfluktuation zu Beginn.In Experimental Examples 10 to 12 after the temperature cycling test, where a temperature cycle of -40 ° C (30 min) and 200 ° C (30 min) was repeated 500 times, again found the solder joint portion has a bonding strength which has 80% or more of the bond strength at the beginning the investigation is. Even after a residence time of 1000 hours at 200 ° C have all semiconductor devices Examples 10 to 12 have a bond strength that is 80% or more of the bond strength at the beginning is. The thermal resistance fluctuation before and after the test Test is in the range of 10%. After the thermal fatigue test, wherein the semiconductor element by supplying an electrical Current from 35 A to 200 ° C heated and shutdown the electric current cooled back to 50 ° C. which is repeated 10,000 times, the thermal resistance fluctuation is within 200% of the thermal resistance fluctuation at the beginning.
Vergleichsbeispiele 1 bis 3:Comparative Examples 1 to 3:
In
den Vergleichsbeispielen 1 bis 3 wurde nach dem Temperaturzyklustest,
bei dem ein Temperaturzyklus von –40°C (30 min)
und 200°C (30 min) 500 mal wiederholt wurde, festgestellt,
daß der Löt-Verbindungsabschnitt eine Verbindungsfestigkeit
aufweist, die 80% oder mehr der Verbindungsfestigkeit zu Beginn der
Untersuchung beträgt. Nach einer Verweilzeit von 1000 Stunden
bei 200°C wird an den Vergleichsbeispielen 1 und 2 jedoch
festgestellt, daß die Verbindungsfestigkeit des Löt-Verbindungsabschnitts
weniger als 80% der Verbindungsfestigkeit zu Beginn beträgt.
Bei einer Untersuchung des Verbindungsquerschnitts wurde festgestellt,
daß sich an der Grenzfläche zwischen der Lotschicht
und der intermetallischen Verbindungsschicht
Vergleichsbeispiele 4 und 5:Comparative Examples 4 and 5:
In
den Vergleichsbeispielen 4 und 5 wurde nach dem Temperaturzyklustest,
bei dem ein Temperaturzyklus von –40°C (30 min)
und 200°C (30 min) 500 mal wiederholt wurde, sowie nach
einer Verweilzeit von 1000 Stunden bei 200°C festgestellt,
daß der Löt-Verbindungsabschnitt eine Verbindungsfestigkeit
aufweist, die 80% oder mehr der Verbindungsfestigkeit zu Beginn
der Untersuchung beträgt. Nach einer 10.000-fachen Wiederholung
des Zyklusses des thermischen Ermüdungstests steigt jedoch
die thermische Widerstandsfluktuation auf einen Wert an, der über
200% der thermischen Widerstandsfluktuation zu Beginn liegt. Es
wird angenommen, daß die Wärmefestigkeit wegen
der Erzeugung einer großen Anzahl von Hohlräumen
im Verbindungsabschnitt des Halbleiterelements im thermischen Ermüdungstest
wie in der
Vergleichsbeispiel 6:Comparative Example 6:
Im
Vergleichsbeispiel 6 wurde nach dem Temperaturzyklustest, bei dem
ein Temperaturzyklus von –40°C (30 min) und 200°C
(30 min) 500 mal wiederholt wurde, sowie nach einer Verweilzeit
von 1000 Stunden bei 200°C festgestellt, daß der
Löt-Verbindungsabschnitt eine Verbindungsfestigkeit aufweist,
die 80% oder mehr der Verbindungsfestigkeit zu Beginn der Untersuchung
beträgt. Nach einer 10.000-fachen Wiederholung des Zyklusses
des thermischen Ermüdungstests steigt jedoch die thermische
Widerstandsfluktuation auf einen Wert an, der über 200%
der thermischen Widerstandsfluktuation zu Beginn liegt. Es wird
angenommen, daß die Wärmefestigkeit wegen der
Erzeugung einer großen Anzahl von Hohlräumen im
Verbindungsabschnitt des Halbleiterelements im thermischen Ermüdungstest
wie in der
Wie beschrieben kann somit eine Halbleitervorrichtung erhalten werden, die eine gute Zuverlässigkeit ihrer Verbindungen aufweist, auch wenn sie bei einer Temperatur betrieben wird, die knapp unter dem Schmelzpunkt des Lots auf Sn-Basis liegt, bei der die Diffusionsgeschwindigkeit hoch ist, da eine Verbindungsschicht ausgebildet wird, die über der Schicht auf Ni-Basis liegt und die als Hauptkomponente eine Cu-Ni-Sn-Verbindung enthält. Diese Verbindungsschicht bildet eine Sperrschicht zwischen dem Lot auf Sn-Basis und der Ni-Beschichtung, so daß, wenn große Ströme fließen und sich das Halbleiterelement stark erwärmt, die Verbindung an der Grenzfläche nicht wächst und das Entstehen von Hohlräumen im Verbindungsabschnitt des Halbleiterelements vermieden wird.As Thus, a semiconductor device can be obtained as described above. which has a good reliability of their connections, even if it is operated at a temperature that is just under is the melting point of the Sn-based solder at which the diffusion rate is high, since a connection layer is formed over the Ni-based layer and the main component is a Cu-Ni-Sn compound contains. This bonding layer forms a barrier layer between the Sn-based solder and the Ni coating, so that when large currents are flowing and the Semiconductor element strongly heated, the connection to the Interface does not grow and the emergence of Cavities in the connecting portion of the semiconductor element is avoided.
ZITATE ENTHALTEN IN DER BESCHREIBUNGQUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.
Zitierte PatentliteraturCited patent literature
- - JP 7-221235 A [0002] JP 7-221235 A [0002]
- - JP 7-161877 A [0002] JP 7-161877 A [0002]
- - JP 2002-142424 A [0002] - JP 2002-142424 A [0002]
- - JP 2002-261210 A [0002] - JP 2002-261210 A [0002]
- - JP 2002-359328 A [0002] - JP 2002-359328 A [0002]
- - JP 3152945 [0005, 0007] - JP 3152945 [0005, 0007]
- - JP 2002-280417 A [0005, 0008, 0026, 0027, 0051, 0052] - JP 2002-280417 A [0005, 0008, 0026, 0027, 0051, 0052]
Claims (17)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007-243218 | 2007-09-20 | ||
JP2007243218A JP5331322B2 (en) | 2007-09-20 | 2007-09-20 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
DE102008046724A1 true DE102008046724A1 (en) | 2009-04-02 |
DE102008046724B4 DE102008046724B4 (en) | 2014-09-25 |
Family
ID=40384648
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE102008046724.3A Active DE102008046724B4 (en) | 2007-09-20 | 2008-09-11 | Semiconductor device |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP5331322B2 (en) |
CN (1) | CN101393901B (en) |
DE (1) | DE102008046724B4 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102017119344A1 (en) * | 2017-08-24 | 2019-02-28 | Osram Opto Semiconductors Gmbh | Carrier and component with buffer layer and method for producing a component |
DE102017119346A1 (en) * | 2017-08-24 | 2019-02-28 | Osram Opto Semiconductors Gmbh | Component with buffer layer and method for producing a component |
EP2940720B1 (en) * | 2012-12-25 | 2021-04-14 | Mitsubishi Materials Corporation | Power module |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102110605B (en) * | 2009-12-24 | 2012-06-06 | 北大方正集团有限公司 | Method and device for manufacturing insulated gate bipolar transistor (IGBT) chip |
TWI476878B (en) * | 2012-05-10 | 2015-03-11 | Univ Nat Chiao Tung | Electric connecting structure comprising preferred oriented cu5sn5 grains and method of fabricating the same |
US9642275B2 (en) | 2012-12-25 | 2017-05-02 | Mitsubishi Materials Corporation | Power module |
US9676047B2 (en) | 2013-03-15 | 2017-06-13 | Samsung Electronics Co., Ltd. | Method of forming metal bonding layer and method of manufacturing semiconductor light emitting device using the same |
JP7180392B2 (en) | 2019-01-11 | 2022-11-30 | 株式会社デンソー | Semiconductor device and its manufacturing method |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03152945A (en) | 1989-11-09 | 1991-06-28 | Fuji Electric Co Ltd | Wire bonding of semiconductor chip |
JPH07161877A (en) | 1993-12-08 | 1995-06-23 | Sanken Electric Co Ltd | Semiconductor device |
JPH07221235A (en) | 1994-02-04 | 1995-08-18 | Sanken Electric Co Ltd | Semiconductor device |
JP2002142424A (en) | 2000-11-02 | 2002-05-17 | Hitachi Ltd | Alternator for vehicle |
JP2002261210A (en) | 2001-02-28 | 2002-09-13 | Hitachi Ltd | Semiconductor device |
JP2002280417A (en) | 2001-01-15 | 2002-09-27 | Nec Corp | Semiconductor device, its manufacturing method, and its manufacturing equipment |
JP2002359328A (en) | 2001-03-29 | 2002-12-13 | Hitachi Ltd | Semiconductor device |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69918758T2 (en) * | 1998-03-26 | 2004-11-25 | Nihon Superior Sha Co., Ltd., Suita | Lead-free solder alloy |
JP3036636B1 (en) * | 1999-02-08 | 2000-04-24 | 日本アルミット株式会社 | Lead-free solder alloy |
JP3866880B2 (en) * | 1999-06-28 | 2007-01-10 | 株式会社日立製作所 | Resin-sealed electronic device |
US6602777B1 (en) * | 2001-12-28 | 2003-08-05 | National Central University | Method for controlling the formation of intermetallic compounds in solder joints |
JP2003303842A (en) * | 2002-04-12 | 2003-10-24 | Nec Electronics Corp | Semiconductor device and manufacturing method therefor |
JP4034107B2 (en) * | 2002-04-17 | 2008-01-16 | 株式会社ルネサステクノロジ | Semiconductor device |
US7193326B2 (en) * | 2003-06-23 | 2007-03-20 | Denso Corporation | Mold type semiconductor device |
JP2005236019A (en) * | 2004-02-19 | 2005-09-02 | Fuji Electric Holdings Co Ltd | Manufacturing method of semiconductor device |
JP4275005B2 (en) * | 2004-05-24 | 2009-06-10 | 株式会社日立製作所 | Semiconductor device |
JP2006066716A (en) * | 2004-08-27 | 2006-03-09 | Fuji Electric Holdings Co Ltd | Semiconductor device |
JP4882229B2 (en) * | 2004-09-08 | 2012-02-22 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
JP4604641B2 (en) * | 2004-10-18 | 2011-01-05 | 株式会社デンソー | Semiconductor device |
JP4343117B2 (en) * | 2005-01-07 | 2009-10-14 | 株式会社ルネサステクノロジ | Semiconductor device and manufacturing method thereof |
JP4569423B2 (en) * | 2005-08-31 | 2010-10-27 | 株式会社日立製作所 | Manufacturing method of semiconductor device |
-
2007
- 2007-09-20 JP JP2007243218A patent/JP5331322B2/en active Active
-
2008
- 2008-09-08 CN CN2008102134946A patent/CN101393901B/en active Active
- 2008-09-11 DE DE102008046724.3A patent/DE102008046724B4/en active Active
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03152945A (en) | 1989-11-09 | 1991-06-28 | Fuji Electric Co Ltd | Wire bonding of semiconductor chip |
JPH07161877A (en) | 1993-12-08 | 1995-06-23 | Sanken Electric Co Ltd | Semiconductor device |
JPH07221235A (en) | 1994-02-04 | 1995-08-18 | Sanken Electric Co Ltd | Semiconductor device |
JP2002142424A (en) | 2000-11-02 | 2002-05-17 | Hitachi Ltd | Alternator for vehicle |
JP2002280417A (en) | 2001-01-15 | 2002-09-27 | Nec Corp | Semiconductor device, its manufacturing method, and its manufacturing equipment |
JP2002261210A (en) | 2001-02-28 | 2002-09-13 | Hitachi Ltd | Semiconductor device |
JP2002359328A (en) | 2001-03-29 | 2002-12-13 | Hitachi Ltd | Semiconductor device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2940720B1 (en) * | 2012-12-25 | 2021-04-14 | Mitsubishi Materials Corporation | Power module |
DE102017119344A1 (en) * | 2017-08-24 | 2019-02-28 | Osram Opto Semiconductors Gmbh | Carrier and component with buffer layer and method for producing a component |
DE102017119346A1 (en) * | 2017-08-24 | 2019-02-28 | Osram Opto Semiconductors Gmbh | Component with buffer layer and method for producing a component |
US11183621B2 (en) | 2017-08-24 | 2021-11-23 | Osram Oled Gmbh | Component having a buffer layer and method for producing a component |
US11450794B2 (en) | 2017-08-24 | 2022-09-20 | Osram Oled Gmbh | Carrier and component with a buffer layer, and method for producing a component |
Also Published As
Publication number | Publication date |
---|---|
CN101393901B (en) | 2011-06-01 |
DE102008046724B4 (en) | 2014-09-25 |
CN101393901A (en) | 2009-03-25 |
JP5331322B2 (en) | 2013-10-30 |
JP2009076611A (en) | 2009-04-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE102008046724B4 (en) | Semiconductor device | |
DE4110373C2 (en) | Electronic circuitry and method of making the same | |
DE102006011232B4 (en) | Substrate for mounting an electronic component and electronic component | |
DE60034418T2 (en) | Use of a soldering material and method of making an electrical or electronic device | |
DE102005028951B4 (en) | Arrangement for the electrical connection of a semiconductor circuit arrangement with an external contact device | |
DE102009045181A1 (en) | Power semiconductor module and method for operating a power semiconductor module | |
EP2283714A2 (en) | Method for producing a printed circuit board and use and printed circuit board | |
DE3446780A1 (en) | METHOD AND JOINING MATERIAL FOR METALLICALLY CONNECTING COMPONENTS | |
DE112017000184T5 (en) | solder | |
EP2481083B1 (en) | Method for fabricating an electronic device and device fabricated with this method | |
EP2760613A1 (en) | Laminated composite made up of an electronic substrate and an arrangement of layers comprising a reaction solder | |
DE112013003902T5 (en) | Semiconductor device and method for its production | |
DE102013103081A1 (en) | Method for connecting joining partners and arrangement of joining partners | |
WO2018192987A1 (en) | Method for fastening a semiconductor chip on a lead frame, and electronic component | |
DE102019135860A1 (en) | Semiconductor device and manufacturing method therefor | |
DE102006012007B4 (en) | Power semiconductor module with surface-mountable flat external contacts and method of making the same and its use | |
DE102008011265A1 (en) | Solder layer and substrate for bonding devices using them, and methods of making such a substrate | |
DE102014206606A1 (en) | Method for mounting an electrical component on a substrate | |
DE3740773A1 (en) | Method for producing electroconductive bonds | |
DE102018207537A1 (en) | Composite arrangement of three stacked joining partners | |
DE10339462A1 (en) | Process for fixing a rigid connecting loop or leg to a connecting surface of a semiconductor chip in the manufacture of semiconductor components | |
DE102020130638A1 (en) | SOLDER MATERIAL, LAYERED STRUCTURE, CHIP HOUSING, METHOD FOR FORMING A LAYERED STRUCTURE, METHOD FOR FORMING A CHIP HOUSING, CHIP ARRANGEMENT AND METHOD FOR FORMING A CHIP ARRANGEMENT | |
DE102012216546A1 (en) | SEMICONDUCTOR CHIP, METHOD FOR PRODUCING A SEMICONDUCTOR CHIP AND METHOD FOR REMOVING A SEMICONDUCTOR CHIP WITH A SUPPORT | |
DE112010003600T5 (en) | Bonding material, semiconductor device and method of manufacturing the semiconductor device | |
DE102019217061A1 (en) | Arrangement with a substrate for receiving at least one semiconductor component for a power converter and method for diffusion soldering of at least one semiconductor component with a substrate for a power converter |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
R016 | Response to examination communication | ||
R016 | Response to examination communication | ||
R018 | Grant decision by examination section/examining division | ||
R082 | Change of representative |
Representative=s name: PATENTANWAELTE STREHL, SCHUEBEL-HOPF & PARTNER, DE |
|
R081 | Change of applicant/patentee |
Owner name: HITACHI POWER SEMICONDUCTOR DEVICE, LTD., HITA, JP Free format text: FORMER OWNER: HITACHI, LTD., TOKIO/TOKYO, JP Effective date: 20140708 Owner name: HITACHI POWER SEMICONDUCTOR DEVICE, LTD., HITA, JP Free format text: FORMER OWNER: HITACHI , LTD., TOKIO/TOKYO, JP Effective date: 20140708 |
|
R082 | Change of representative |
Representative=s name: STREHL SCHUEBEL-HOPF & PARTNER MBB PATENTANWAE, DE Effective date: 20140708 Representative=s name: PATENTANWAELTE STREHL, SCHUEBEL-HOPF & PARTNER, DE Effective date: 20140708 |
|
R020 | Patent grant now final |