DE102008009924B4 - Method for generating frequencies - Google Patents

Abstract

The claim extends to a method for producing adjustable frequencies from an original clock, characterized by a counter A which is operated directly at the original clock and addresses a table which controls a clock gate for a counter B, and a counter B which gates through the clock gate Clocks counts, whereby the desired frequency arises in counter B and can be tapped.

Description

1 Introduction

Often one faces the problem of having to establish an adjustable frequency from a fixed reference frequency.

The prior art has long been the interconnection of a counter and a function generator or memory. Arrangements of this type have been disclosed, inter alia, in the patents US 3,110,802 A. (from the year 1957), DE 38 88 421 T2 . DE 600 02 426 T2 (from 1999). The author has also used arrangements of this kind in the eighties of the last century for the production of test pattern generators. These arrangements are often used to generate fixed functions at fixed frequencies. Also known arrangements of adjustable counters, as in the patent US 2004/0000 939 A1 described. An interesting solution is also in the patent DE 38 41 431 A1 (from 1988). There is described an arrangement of a counter and a comparator which outputs a defined adjustable number of clocks in a counting cycle. The described solutions do not lead to the goal of producing an arbitrarily adjustable frequency of high accuracy and with low jitter.

The patent US 3,105,911 A (from the year 1959) concerns the electronic commutation (today one says multiplexer) of telemetry signals, and not the generation of arbitrarily adjustable frequencies.

Known solutions to this problem are PLL loops and also the DDS. The PLL has the disadvantage that analog control loops are required whose transient response and stability significantly affect the properties of the overall system PLL. As a result, frequency changes are always problematic, even if the frequency transition is fixed. These disadvantages do not have the DDS. However, the DDS is quite expensive, wide and fast adder circuits are necessary, and the known circuits in which a DDS is integrated produce a maximum of 12-bit sinusoidal oscillations.

These disadvantages do not have the solution presented here. In one application, an adjustable sinusoidal generator with 16 bit accuracy for the frequency range of 0.1 Hz to 10 kHz with 2 ROMs, a GAL in which less than 64 macrocells were occupied, a 40 MHz quartz generator and a digital / analog converter realized. The necessary procedure should be explained and protected here.

2. Description - Explanation of the procedure

This method of frequency synthesis requires a master clock generator, a counter A, a counter B, a set of tables and a clock gate. The counter A counts original clocks and thus generates addresses for the table set. Each table of the table set has as many values as the counter A can address. The addressed values are read from a table of the table set. These values switch the clock gate. This means that the table shows whether the original clock is passed from the clock gate to the counter B or not. With the counter B these pieced original clocks are counted. At the output of counter B, the desired frequency is available. At the output of the counter B you can also connect a function table and generate arbitrary functions in this way. Because of its operation, this method would baptize table-oriented frequency synthesis (TFS). The necessary structure for carrying out the method is in the shown

Different frequencies generally require different tables. In order to limit the number of required tables, it makes sense to place only a variation of 1: 2 in the tables, and to control everything else about changes in counter B. These changes in counter B may be, for example, the addition of further counts or the change of count to further reduce the output frequency. It is also possible to realize switchable preservers in the original clock in order to increase the variability of the output frequency. Due to relatively long tables and defined (uneven) distribution of the clocks in the table, it is also possible to achieve certain modulations of the output frequency. The principle can also be cascaded.

3. Description - mathematical consideration of the procedure

In this method, a clock conversion is performed with a table. In a time interval, given by the counter A, only the clocks clocked by the table are forwarded to the counter B. As a result, the counter B receives in the same time interval less (at most just as much) clocks and it arises at the counter B a clock that is in a rational relationship to the Urtakt. The generated frequency results from the following equation: generated frequency = (original clock) · (number of clocks from the table) / (count A) · (count B)

All multiples of the frequency Urtakt / (count A · count B) can be generated. By suitable choice of the Urtaktes and the counter scopes of counter A and counter B suitable for the application screening of the adjustable frequencies can be generated

Disadvantage of all digital methods for frequency synthesis is a phase jitter. This phase jitter also occurs in this method, but can be effectively suppressed if one observes certain design guidelines. Since the counter B substantially contributes to the suppression of the phase jitter, the count amount of the counter B should be at least equal to the maximum number of clocks in the clock table. It makes no sense to make the counter B too small, otherwise not only the phase but also the output frequency jitters and always umump around the setpoint. If the count of the counter B corresponds to the maximum number of cycles in the table or even multiples thereof, then exact stable frequencies are generated which have only one phase jitter, which is within the temporal resolution of the original clock. It is clear from this that the original beat should be as high as possible and stable.

It is important that not only the number of clocked clocks in the clock table is correct, but the clocks are also evenly distributed in the clock table, so that the Phasenjittern is as low as possible. Therefore, it makes sense to create these clock tables with a suitable program. The fact that the frequency generated is usually well below the Urtakt, the phase jitter can be very easily eliminated by filtering. With correct generation of the clock tables, the phase jitter is less than half a period length of the original clock.

4. Description - Example

In this example, a simple adjustable sine wave generator for frequencies between 0.1 Hz and 10 kHz will be presented. The amplitude should be 16 bit accurate, the phase should in any case be better than 0.1% accurate, the frequency should be precisely adjustable to 0.1%. The output clock for this is made with a standard 40 MHz quartz generator. The counter A has a count of 4000, accordingly each clock table has 4000 values (500 bytes). It should be generated from the clock table between 1000 and 2000 clock edges (500 to 1000 clocks). For this purpose, 1000 clock tables per 4000 values (500 bytes) were generated and stored in a ROM. With this, all frequencies between 5 kHz and 10 kHz can be set exactly to 2.5 Hz, with counter B delivering exactly every frequency divisible by 5. Counter B is usually operated (without prescaler) with a frequency between 5 MHz and 10 MHz. The counter B has a variable count between 1000 and 100000, depending on the frequency to be set. At an output frequency of 10 kHz, the count of the counter B is 1000, at frequencies below 100 Hz, the count of the counter B is 100000, below 50 Hz prescaler are inserted in front of plate B.

To generate the sinusoidal shape of the output frequency, sine tables are stored in a ROM. This ROM is addressed by counter B. Connected to the ROM with the function table is a D / A converter, where the sinusoidal curve is generated.

At 10 kHz, a sine curve consists of 1000 values, the number of values increases until at 100 Hz the sine consists of 100000 values. By clever structuring of the counter B, it was only necessary to store 3 function tables in the ROM, a total of significantly less than 256 kWorte.

The entire logic of the generator (counter A, clock gate, counter B, prescaler, auxiliary functions such as registers, parallel / serial conversion of the bytes of the ROM of the clock table) was programmed in a GAL, thereby less than 64 macrocells were needed. The ROM of the clock table only needs an access time of 200 ns, the ROM of the sine table needs an access time of 100 ns. Modern EPROM's, FLASHROM's or even RAM's fulfill this requirement without problems. The schematic representation is in shown.

The jitter of the output frequency is ± 12.5 ns at the used 40 MHz clock, which is so far away from the useful bandwidth, so that this jitter can be easily filtered away with simple means.

Claims (1)

The claim extends to a method for producing adjustable frequencies from an originating clock characterized by a counter A which operates directly at the originating clock and addresses a table controlling a clock gate for a counter B and a counter B which punctures those through the clock gate Counts counts, with the desired frequency in the counter B is created and can be tapped.

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