DE102007004794A1 - Controller block with monitoring by a watchdog - Google Patents

Abstract

The invention relates to a controller module with monitoring by a watchdog, wherein the controller module includes an arithmetic unit and an addressable port module, each of which is connected to an internal controller address bus and to a controller internal data bus, wherein within a component of the controller module at least one arithmetic task is stored the result being the address of the port block, the arithmetic unit calculating the arithmetic task cyclically and outputting the result value to the address bus and the arithmetic unit giving a data value to the data bus which appears as a signal for resetting the watchdog if the port block is correctly addressed at the port block output ,

Description

The The present invention relates to a controller module with a monitor by a watchdog, wherein the controller module is a computing unit and an addressable port block, both each with an internal controller address bus and with a controller internal Data bus are connected.

From the Japanese Patent Abstract JP 02281343 A An arrangement is known in which a computing unit is connected via an address bus and a data bus to a comparison circuit, which compares values on the address and the data bus with reference values, and resets a watchdog timer on successful comparison.

Lots Facilities of daily life are today with one Microcontroller provided. For particularly important or safety-critical Facilities will perform the correct function of the microcontroller ensure special measures, such as through a multiple and thus redundant installation of safety-critical components. This creates a relatively high cost.

frequently is a so-called for monitoring a controller module Watchdog provided. It is one by hardware or software realized counters or timers that are within regular Timing is reset by a signal, and, if the signal fails, triggers a safety function, for example, by resetting the controller module or by switching off more or less large parts of the monitored Facility.

One Watchdog thus checks whether a resetting Signal occurs regularly. How reliable with it Mistakes are recognized, depends on the type and See how the reset signal is obtained. This can be done with an otherwise regular program a computing unit are often not recognized when the arithmetic unit Performing operations incorrectly. To such errors often uncover two independently working arithmetic units are provided which mutually check their calculation results. However, this requires a considerable cost.

It set itself the task of creating a controller module, in the arithmetic occurring in particular in a computing unit Error in a simple and cost-effective manner reliable can be recognized.

These The object is achieved according to the invention that within a component of the controller module at least a calculation task is stored, the result being the address of the port block indicates that the arithmetic unit is the arithmetic task cyclically calculated and the result value is on the address bus and that the arithmetic unit gives a data value to the data bus, the with correctly addressed port block at the output of the port block appears as a signal to reset the watchdog.

Of the Controller module according to the invention leads thus arithmetic tasks, in particular numerical arithmetic tasks through, their results to verify the correct Function of the arithmetic unit are used.

advantageous Embodiments and developments of the invention are in the dependent Claims cited. The following is an embodiment of the invention illustrated with reference to the drawing and closer explained. The single figure shows a greatly simplified Block diagram of a controller module according to the invention.

Of the Controller module (CB) has at least one processor unit (CPU) and a port block (IO). The port block (IO) can do this for example, a serial or parallel input / output module be. The arithmetic unit (CPU) and the port block (IO) are over an address bus (AB) and a data bus (DB) with each other, wherein the arithmetic unit (CPU) the port block (IO) via the Address bus (AB) can address. Via the data bus (DB) can data values from the processing unit (CPU) to the port block (IO), and vice versa.

Of Furthermore, the controller module (CB) has an internal component (SP) realized, for example, as a memory device (SP), in the at least one computational task (RA) and preferably several computational tasks (RA) are stored. The term mathematical problem (RA) stands generally for an algorithmic process executed by the computing unit (CPU) and returns a numeric result value as the result. The at least one calculation task (RA) is specified in this way, that it supplies the address of the port block (IO) as the result value.

Intended is also a hardware or software watchdog (WD), which contains a resettable counter or timer. The watchdog (WD), shown here as an external device is, alternatively, as one in the controller module (CB) be executed integrated component.

If the watchdog is reset (WD) not regularly within a time window or before a maximum time expires, it generates an output signal, which is supplied to a reset input (RESET) of the controller module (CB) and a restart of the controller module (CB) or the processing unit (CPU) with defined initial conditions causes. Alternatively, the output signal of the watchdog (WD) can also switch off the device controlled by the controller module (CB).

Of the The structure described in particular has the purpose of functioning the controller module (CB) and especially the processing unit (CPU), to check regularly and to ensure that. It is essential that especially the arithmetic functions, ie the "correct arithmetic" the computing unit (CPU) to be monitored.

For checking Edits the arithmetic unit (CPU) within the usual Program execution arithmetic tasks (RA), for example, in an internal Memory module (SP) are stored and the computing unit (CPU) from this memory block (SP) retrieves. The computing unit (CPU) calculates a numeric result value from this.

The However, the processing unit (CPU) can not do this result itself reliably check for correctness, because at a faulty result value it at least not be ruled out is that checking the result value is also buggy would.

The Solution to this problem is to externalize the result, So outside of the arithmetic unit (CPU) to check. For this purpose, a calculation of the same calculation task by a second, independent arithmetic unit or a retrieval of the stored result, and a comparison of the two result values be provided. Such a structure would be very expensive.

Instead of whose external verification is done by the result value for addressing a port block (IO) is used. The at least one stored in the memory module (SP) Computational task (RA) is formed so that they are the result of the Address of the port block (IO) returns. The computing unit (CPU) then returns the result of the calculation to the address bus (AB). If the calculation result is correct, the port block (IO) is addressed. A subsequent from the arithmetic unit (CPU) to the data bus (DB) given data value thus reaches the port block (IO), which thereupon a signal corresponding to this data value at its Output outputs, which is a reset of the watchdog (WD) causes.

Calculated however, the arithmetic unit (CPU) faulty the result, so the port block (IO) is not addressed and the port block (IO) Accordingly, there is no signal for resetting the watchdog (WD) off. In this case, the watchdog (WD) generates an output signal for the reset input (RESET) of the controller block (CB).

The Security of verification can be further increased are, even if the data value, the processing unit (CPU) on the data bus (DB), previously from the arithmetic unit (CPU) as a result a calculation task (RA) is determined.

In In this regard, it is also advantageous if the computing unit (CPU) not always the same arithmetic problem (RA) for determination the address of the port block (IO) triggers, but several different computing tasks (RA) in succession, preferably in random order. This will cause the arithmetic unit (CPU) tested to a greater extent, so that with greater security also smaller and More specific errors of the arithmetic unit (CPU) can be revealed.

FROM

address

CB

controller chip

CPU

computer unit

DB

bus

IO

port module

RA

Calculation (n)

RESET

Reset input

SP

component (Memory block)

WD

Watchdog

QUOTES INCLUDE IN THE DESCRIPTION

This list The documents listed by the applicant have been automated generated and is solely for better information recorded by the reader. The list is not part of the German Patent or utility model application. The DPMA takes over no liability for any errors or omissions.

Cited patent literature

• - JP 02281343 A [0002]

Claims (9)

Controller module with monitoring by a watchdog, wherein the controller module includes a computing unit and an addressable port module, both of which are each connected to an internal controller address bus and a controller internal data bus, characterized in that within a component (SP) of the controller module (CB) at least a computational task (RA) is stored, which results in the address of the port block (IO), that the arithmetic unit (CPU) calculates the arithmetic task (RA) cyclically and outputs the result value to the address bus (AB) and that the arithmetic unit (CPU) gives a data value to the data bus (DB), which appears as a signal for resetting the watchdog (WD) at the correctly addressed port block (IO) at the output of the port block (IO). Controller module according to Claim 1, characterized that within a component of the controller module (CB) several Arithmetic tasks (RA) are stored, the computing unit (CPU) cyclically calculated one after the other. Controller module according to Claim 1, characterized that within a component (SP) of the controller module (CB) several arithmetic tasks (RA) are stored that the arithmetic unit (CPU) calculated in random order one after the other. Controller module according to one of the preceding claims, characterized in that the arithmetic unit (CPU) the data value also determined by calculating a calculation task (RA). Controller module according to Claim 1, characterized that the watchdog (WD) is a controller-internal component or a controllerexterne device is. Controller module according to Claim 1, characterized that the controller module (CB) is connected to several watchdogs is. Controller module according to claim 6, characterized that at least one watchdog is a controller-internal component and at least one watchdog (WD) is a controllerexterne device. Controller module according to Claim 1, characterized that at least one watchdog (WD) resets the Controller block (CB) can perform. Controller module according to Claim 1, characterized that at least one watchdog switches off one by the controller module controlled device can perform.