DE102006062024A1 - Multi port semiconductor memory device, has test mode control device executing core test by converting serial data communication into parallel data communication during selected core test mode, where control device has mode adjusting unit - Google Patents

Abstract

The device has ports (PORT0-3) for execution of serial data communication with external devices by pads. A set of banks (BANK0-7) is provided for the execution of parallel data communication with the number of ports. A set of global data buses (GIOin, GIOout) supports/assists the parallel data communication between the ports and the banks. A test mode control device executes a core test by converting the serial data communication into the parallel data communication during a selected core test mode, where the mode control device has a mode adjusting unit (91).

Description

AREA OF INVENTION

The The present invention relates to a semiconductor memory device; and more particularly to a semiconductor memory device including Data communication with external devices using a parallel input / output (I / O) interface during a core test mode.

DESCRIPTION STATE OF THE ART

in the Generally, most memory devices have memory random access (RAM) a single port with a variety of input / output porting groups on. The single port is for provided a data exchange with an external chipset. The Storage device with the single port uses a parallel I / O interface for one simultaneous data transmission of different bits by signal lines connected to a plurality connected by I / O connector pins. That is, data be connected to an external device through a variety of I / O connector pins exchanged in parallel.

The I / O interface is an electrical and mechanical arrangement for the precise transmission of I / O data by adding individual devices with different functions are connected by signal lines. I / O interfaces, which to be further described below, should be designed to be have the same meaning as the I / O interface described above. additionally the signal lines represent buses for the transmission of signals, such as address signals, data signals and control signals. The signal lines are referred to as buses for ease of explanation.

There the parallel I / O interface data from different bits through transmits different buses simultaneously, it has a data processing efficiency (speed) on. This is why the parallel I / O interface is largely the same during a transmission used at a short distance, requiring a high speed becomes. Because the parallel I / O interface but a big one Number of buses for transmission of I / O data, manufacturing costs increase when the distance increases. In terms of hardware of a multimedia system must be a variety be configured so independently of memory devices that they different multimedia functions due to the limitation supported by the single port. Furthermore, another function can not be performed simultaneously, when a certain function is executed.

Around to overcome these problems Many attempts have been made to use the memory devices the parallel I / O interface through the memory devices with the serial I / O interface. An I / O environment the semiconductor memory device must go into the serial I / O interface changed with the extension being compatible with other devices serial I / O interface must be observed. Besides, they are Application devices, such as audio or video processors, installed in display devices, such as high-definition televisions resolution (HDTV) and Liquid Crystal Display (LCD) TVs. This one Application devices independent Data processing, there is an increasing demand for multiport memory devices with a serial I / O interface to data through a variety of To transfer ports.

When Reference has been proposed to a semiconductor memory device, that in a the applicant belonging pending Registration, US Ser. 11 / 528,970, which is on 27. September 2006 entitled "MULTI-PORT MEMORY DEVICE WITH SERIAL INPUT / OUTPUT INTERFACE ".

1 FIG. 10 is a conceptual diagram of a conventional multi-port memory device. FIG. In 1 the multi-port memory device with four ports and eight banks is illustrated. The multiport memory device has a 16-bit data frame and performs a 64-bit prefetch operation.

The multi-port memory device has first to fourth ports PORT0 to PORT3; first to eighth banks BANK0 to BANK3 and BANK4 to BANK7; first global data buses GIO_OUT, second global data buses GIO_IN; and first to eighth bank controllers BC0 to BC7. The first to fourth ports PORT0 to PORT3 are arranged in the central portion of the core area in a row direction to independently perform serial data communication with different external target devices. The first to eighth banks BANK0 to BANK3 and BANK4 to BANK7 are arranged above and below the ports PORT0 to PORT3 in a row direction. The first global data buses GIO_OUT are arranged between the first to fourth banks BANK0 to BANK3 and the first to fourth ports PORT0 to PORT3 in a row direction to transmit output data in parallel. The second global data buses GIO_IN are arranged between the fifth to eighth banks BANK4 to BANK7 and the first to fourth ports PORT0 to PORT3 in the row direction to transmit output data in parallel. The first to eighth bank controllers BCO to BC7 steu The signal transmission between the first and second global I / O buses GIO_OUT and GIO_IN and the banks BANK0 to BANK7.

In particular, as in 2 is illustrated, each of the first to eighth banks BANK0 to BANK7 comprises: a memory cell array 10 ; a row decoder 11 ; a column decoder 12 ; an equalizer (not shown); a write driver 13 ; and a data bus sense amplifier 14 , The storage cell array 10 has a plurality of memory cells arranged in an N × M matrix (where M and N are positive integers). The first to eighth banks BANK0 to BANK7 halve the core area. That is, the first to eighth banks BANK0 to BANK7 are arranged symmetrically in such a manner that the first to fourth banks BANK0 to BANK3 are arranged via the ports PORT0 to PORT3 in a row direction, and the fifth to eighth banks BANK4 to BANK7 below the ports PORT4 to BANK7 are arranged in a row direction. The data buses are bit lines which correspond to column lines.

The first to fourth ports PORT0 to PORT3 are arranged in the central portion of the core area and arranged with the first and second global data buses GIO_OUT and GIO_IN in such a manner that they can access all of the banks BANK0 to BANK7. In addition, as in 3 is illustrated, each of the ports PORT0 to PORT3 independently has a receiving part 41 for receiving the input signals through the reception pad RX and a transmission part 42 for transmitting the output signals through a transfer pad TX to the external device such that the input signals input from an external device (an application device) through a receive pad RX and the output signals output from the banks BANK0 to BANK7 through the first global data buses GIO_OUT are simultaneously transferred can.

The Receiving section 41 converts the input signal of a 20-bit frame which is serially input from the external device through the reception pad RX becomes, in parallel valid 26-bit signals around, for the operation of the DRAM are suitable. The valid 26-bit signals exist of 8-bit port / bank selection signals Pi_BK <0: 7> (where i a positive integer corresponding to the number of ports and takes values from 0 to 3) and valid 18-bit input data signals Pi_RX <0:17> (where i is values of 0 to 3). additionally exists the valid 18-bit input data signals Pi_RX <0:17> from a command flag signal, a row address strobe (RAS) / data mask (DM) signal and 16-bit command / address / data signals. in this connection For example, the 16-bit command / address / data signals are signals which as a command, address or data can be detected.

4A to 4F illustrate frame formats of the signals as a protocol for signal transmission. In particular, illustrate 4A to 4F a basic frame format, a write command frame format, a write data frame format, a read command frame format, a read data frame format, and a command frame format, respectively.

As an example, the write command / data frame format of 4B and 4C explained below.

With reference to 4B For example, the write command frame format has a 20-bit serial signal input from the external device. The 19th and 18th bits "PHY" are physical link coding bits, the 17th bit is a "CMD" signal, and the 16th through 14th bits are "ACT" (active) and "WT" (write). and "PCG" (precharge) signals. "ACT", "WT", and "PCG" respectively represent an internal active signal, an internal write command signal, and an internal inactive signal. For example, the 17th through 14th bits are in a normal write, "1010" and "1011" in an auto precharge write. The 13th through the 10th bits "UDM" are used as a top-byte write data mask of write data applied over four clocks, and the 9th through the 6th bits "BANK" are bank data written in a write operation. The 5th to the 0th bits "COLUMN ADDRESS" are column addresses.

In the write data frame of 4C 16-bit write data is input over four clocks after the in 4B Write command frame shown has been entered. In the write data frame format, the 17th bit "CMD" must be LOW (0), and the 16th bit "LDM" means a lower byte write data mask of the input data. The 15th to 8th bits "UPPER BYTE" and the 7th to the 0th bits "LOWER BYTE" respectively mean the upper byte and the lower byte of the write data.

A structure of the receiving part 41 will be referring below 3 described.

With reference to 3 the receiving part 41 has a parallelizer 411 , a command generator 412 , a bank address generator 413 , a bank address issuing unit 414 and an output unit 415 for valid input data.

The parallelizer 411 receives 20-bit input signals (one frame) inputted from the external devices through the reception pad RX as serial signals, and converts the 20-bit input signals into parallel 20-bit signals.

Which operation the input signal carries out is set by the command generator 412 using the 17th bit (command flag) among those of the parallelizer 411 output 20-bit frame input signals. That is, if the 17th bit in the frame after 4B When the 17th bit is "1", the input signal is set as a signal for performing the read operation. In addition, the command generator gives 412 Bits used as bank data between the bits of the inputted signal. Since eight banks are provided, 3 bits are used and the bits are in the frame load of 4 contain.

The bank address generator 413 receives bits (3 bits in this example) from the instruction generator 412 where the bits are used as selection data for selecting the corresponding bank under the banks BANK0 to BANK7, and generates 8-bit bank addresses. For this purpose, the bank address generator 413 equipped with a 3 × 8 decoder for receiving the 3-bit input signal and outputting the 8-bit output signal.

The bank address issuing unit 414 receives the bank addresses from the bank address generator 413 and transmits the 8-bit bank select signals Pi_BK <0: 7> through the second global I / O data buses GIO_IN. The bank address issuing unit 414 is provided with a variety of output drivers. The output drivers are known to the person skilled in the art.

The output unit 415 for valid input signals, the valid 18-bit data signals receives Pi_RX <0:17> from the parallelizer 411 and transmits them through the second global I / O data bus GIO_IN. Like the bank address issuing unit 414 is the output unit 415 for valid input signals equipped with a plurality of output drivers.

The transmission unit 42 serializes the output valid data signals Pi_DATA <0:15> (where i takes values from 0 to 3) which are input from banks BANK0 to BANK7 in parallel through the first global data buses GIO_OUT.

The transmission unit 42 has a serializer 421 and an input unit 422 for valid output data.

The input unit 422 for valid output data, the valid 16-bit data signals receives Pi_DATA <0:15> from the banks BANK0 to BANK7 through the first global data buses GIO_OUT in parallel form, packages the valid output data signals Pi_DATA <0:15> based on the transmission protocol under the control of the command generator 412 (the I / O control of the data signals according to the writing or reading operation), and then generates the output signals with 20-bit frames. The input unit 422 for valid output data is equipped with a variety of input drivers.

The serializer 421 serializes the 20-bit output signals from the input unit 422 for valid output data are inputted in parallel, and outputs the serialized 20-bit output signals through the transfer pad TX one by one.

The first global data buses GIO_OUT have 64 buses (16 (number of Data bits) × 4 (Number of ports)) for independent transmission the one from the benches BANK0 to BANK7 entered valid Output data signals Pi_DATA <0:15> to ports PORT0 to PORT3 in parallel.

The second global data buses GIO_IN have 104 buses (26 (number of data bits) × 4 (number from ports) for independent transmission of the 26-bit signals input from ports PORT0 to PORT3 (valid 18-bit input data signals and 8-bit bank select signals) to the benches BANK0 to BANK7 in parallel.

The first and second global data buses GIO_OUT and GIO_IN are connected to local data buses so as to transfer data to the bank controllers BCO to BC7 or the ports PORT0 to PORT3. That is, the local data buses connect the first and second global data buses GIO_OUT and GIO_IN to the bank controllers BCO to BC7 and the ports PORT0 to PORT3. For convenience of explanation, the first to fourth local data buses LIO_BOUT, LIO_BIN, LIO_P1, and LIO_P2 are in 1 illustrated.

The bank controllers BCO to BC7 are installed in the banks one by one so as to control the respective banks BANK0 to BANK7. The bank control devices BCO to BC7 control the signal transmission between the banks BANK0 to BANK7 and the ports PORT0 to PORT3. As in 5 1, each of the bank controllers BCO to BC7 has a parallelizer 61 , a serializer 62 , a state machine 63 , a state determinator 64 for input signals, a bank voter 65 and a port selector 66 on.

Triggered by or in response to the port / bank selection signal P / B_SELECT, the bank selector dials 65 the signals to be input to the corresponding bank among the valid input data signals Pi_RX <0:17>, which are independent from ports PORT0 to PORT3, and transmits the selected signals to the corresponding bank. The reason for this operation is that the valid input data signals Pi_RX <0:17> can be input simultaneously from all ports PORT0 to PORT3 through the second global data buses GIO_IN. At this time, the port / bank select signal P / B_SELECT has the bank select signal Pi_BK <0: 7>, which is different from the in 3 illustrated bank address dispensing units 414 Bank BANK0 to BANK3 is issued. The bank voter 65 receives the 26-bit signals including the valid 18-bit input data signals Pi_RX <0:17> input from the ports PORT0 to PORT3 through the first global data buses GIO_IN and the 8-bit port bank selection signals Pi_BK <0: 7> Selection of banks BANK0 to BANK7, and outputs the valid 18-bit bank data signals BRX <0:17>.

Among those of the bank voter 65 output valid 18-bit bank data signals BRX <0:17>, 16 bits are used as signals (control signals) for designating data status, address or bank, 1 bit is used as the active flag signal, and 1 bit is used as the control flag signal for determination Whether the 16-bit signals are data signals, address signals or control signals.

As an example, BRX <17> is used as the control flag signal, and BRX <16> is used as the active flag signal. The control flag signal BRX <17> is regarded as the enable signal of the state machine 63 used, and the active flag signal BRX <16> is used as RAS / DM signal, which serves as the operating signal of the DRAM. RAS is a chip enable signal for controlling the entire DRAM and is an initial operating signal of the DRAM.

The state determinator 64 for input signals, the valid 18-bit bank data signals BRX <0:17> are received by the bank selector 65 and determines if the valid 18-bit bank data signals BRX <0:17> are data, address, or command signals. The state determinator 64 For input signals, specifically, using the state (0 or 1) of the command flag signal, which is the most significant bit of the valid 18-bit bank data signals BRX <0:17>, determines whether the 16-bit signals BRX <0:15> with the exception of the seventeenth bit BRX <16>, the data signal, the address signal or the command signal. If the 16-bit signals BRX <0:15> are not the data signal, the state determinator returns 64 for input signals, the 18-bit signals BRX <0:17> to the state machine 63 out. On the other hand, if the 16-bit signals BRX <0:15> are the data signal, the state determinator is 64 for input signals, the 18-bit signals BRX <0:17> to the parallelizer 61 out.

The state machine 63 receives the valid 18-bit bank data signals BRX <0:17> from the state determinator 64 for input signals, and outputs using the received signals address / command signals ADD / COM to control the operation of the DRAM. The internal command signals, the internal address signals and the internal control signals are generated by the address / command signals triggered by ADD / COM. The internal command signals include the internal active command signal ACT, the internal inactive command signal PCG, the internal read command signal READ, and the internal write command signal WRITE. The internal address signals include the row addresses XADD and the column addresses YADD. The internal control signals include: the input data strobe signals DSTROBE16 <0: 3> and DSTROBE64; the control signals DRVEN_P <0: 3>; the pipe input strobe signal PINSTROBE; and the pipe output control signals POUT <0: 3>.

6 is a block diagram of in 5 illustrated state machine 63 ,

The state machine 63 indicates: a command generator 631 ; an input data strobe generator 632 ; a row address generator 633 ; a column address generator 634 ; a read data pipe controller 635 and a data output controller 636 ,

The command generator 631 is enabled by the most significant bit BRX <17> of the valid bank data signals BRX <0:17> and decodes the bits BRX <0:15> to the internal command signals, such as the internal active command signal ACT, the internal inactive command signal PCG to generate the internal read command signal READ and the internal write command signal WRITE. The command generator 631 is equipped with a decoder which receives n digital signals to generate 2 "digital signals.

The input data strobe generator 632 generates the input data strobe signals DSTROBE16 <0: 3> and DSTROBE64 triggered by the most significant bit BRX <17> of the valid bank data signals BRX <0:17> and the write command signal WRITE. The input data strobe signals DSTROBE16 <0: 3> and DSTROBE64 are used as control signals to control the operation of the parallelizer 61 used.

The row address generator 633 generates the valid bank data signals BRX <0: m> (where m is a positive integer) as row addresses XADD <0: m> triggered by (synchronization) the internal active command signal ACT.

The column address generator 634 generated the valid bank data signals BRX <0: n> (where n is a positive integer) as column addresses YADD <0: n> triggered by the write command signal WRITE and the read command signal READ.

The read data pipe controller 635 generates the pipe input strobe signal PINSTROBE and the pipe output control signals POUT <0: 3> triggered by the internal read command signal READ.

The data output controller 636 generates the control signals DRVEN_P <0: 3> using the bank selection signals Pi_BK <0: 7> triggered by the internal read command signal READ. As an example, the signals for selecting the bank BANK0 are specified and indicated by a reference symbol BK0_P <0: 3>. The control signals DRVEN_P <0: 3> are used as control signals for controlling the operation of the port selector 66 used.

The parallelizer 61 parallels the valid bank data signals BRX <0:15> which are from the state determinator 64 for signals and outputs the 64-bit parallel signals. This means that while that of the state determinator 64 for input signals transmitted signals BRX <0:15> are input to the previously parallelized signal format to be read from the memory cell areas of the banks BANK0 to BANK7 64-bit data or written into this. Therefore, it is necessary to convert 16-bit data into 64-bit data.

The serializer 62 receives the 64-bit data signals from the 64 data bus sense amplifiers 14 which are connected to the data buses of the banks and serializes the 64-bit data signals into 16-bit data signals DO <0:15> triggered by the pipe input strobe signal PINSTROBE and the pipe output control signals POUT <0: 3> ,

As in 5 is illustrated, the port selector receives 66 successively the data signals DO <0:15> from the serializer 62 in 16-bit units, and outputs the valid data signals Pi_DATA <0:15> to the port selected by the port / bank select signal P / B_SELECT.

The port selector 66 is equipped with demultiplexers (DEMUX). The demultiplexers are assigned to the respective ports PORT0 to PORT3 in such a way that they can carry out the signal transmission independently of all ports PORT0 to PORT3. In addition, each of the respective demultiplexers 16 Driver so that the 16-bit data signals DO <0:15> can be processed.

There the ones from the benches BANK0 to BANK7 signals output to ports PORT0 to PORT3 through the first global data buses GIO_OUT of all banks BANK0 until BANK7 are split, it is preferred that the respective Drivers are provided with tri-state buffers so that other banks will not to be influenced.

One Operation of the multi-port memory device will be described below.

7 is a diagram illustrating the transmission path of the input signal Pi_BK <0: 7> from the ports PORT0 to PORT3 to the banks BANK0 to BANK7, and 8th FIG. 12 is a diagram illustrating the transmission path of the output signal Pi_DATA <0:15> from the banks BANK0 to BANK7 to the ports PORT0 to PORT3. In 7 BKj_P <0: 3> (where j takes values from 0 to 7) represents a signal identical to the bank selection signal Pi_BK <0: 7>, but it is referred to by a different reference symbol for ease of explanation.

First becomes the transmission path from the first port PORT0 to the second bank BANK1 below described.

Regarding 7 For example, the 18-bit input signals (except for the physical link encoding bit) are serially input to the first port PORT0 from the external device through the reception pad RX. The first port PORT0 converts the 18-bit input signals into the valid 26-bit signals and transmits them through the second global data buses GIO_IN. Since the second global data buses GIO_IN through the second local data buses LIO_BIN (see 1 ) are connected to all banks BANK0 to BANK7, the valid 26-bit signals are sent to the bank voters 65 (please refer 5 ) of the banks BANK0 to BANK7 are transmitted by the second local data buses LIO_BIN.

There those transmitted from the first port PORT0 valid 26-bit signals, in particular the valid input data signals P0_RX <0:17>, only to the second Bank BANK1 transferred Need to become, It is necessary to prevent the signals to all the others benches BANK0 and BANK2 to BANK7 as transmitted to the second bank BANK1 become. For this purpose, bank selection signals P0_BK <0: 7> are used.

The bank selection signals P0_BK <0: 7> consist of the valid 26-bit signals supplied by the port PORT0 together with the valid input data signals P0_RX <0: 7>. The bank selection signals P0_BK <0: 7> are put into the bank selector 65 of the second bank BANK1 entered by the second global data buses GIO_IN together with the valid input data signals P0_RX <0:17> and controls the bank voter 65 ,

The bank voter 65 for controlling the input signal transmission of the second bank BANK1 is triggered by the bank selection signals P0_BK <0: 7> enabled, that is BK1_P <0: 3>, receives the valid input data signals P0_RX <0:17> through the second global data buses GIO_IN and transmits the received ones Signals P0_RX <0:17> to the second bank BANK1. At this time, the bank voters 65 Banks BANK0 and BANK2 to BANK7 are not enabled because the remaining bank select signals BK0_P <0: 3> and BK2_P <0: 3> to BK7_P <0: 3> go to a logical "HIGH" level or a logic "LOW" level are disabled, so that the valid input data signals P0_RX <0:17> are not transmitted to the banks BANK0 and BANK2 to BANK7.

When next below will be the transmission path the output signals from the second bank BANK1 to the first port PORT0 described.

With reference to 8th are the 64-bit data signals output from the second bank BANK1 from the serializer 62 the second bank controller BC1 is serialized into the 16-bit data signals DO <0:15>, and the 16-bit data signals DO <0:15> are sent to the port selector 66 , for example to the demultiplexer. Triggered by the activated control signals DRVEN_P <0> under the control signals DRVEN_P <0: 3>, the demultiplexer transmits the data signals DO <0:15> as the valid output data signals P0_DATA <0:15> through the first global data buses GIO_OUT.

The through the first global data buses GIO_OUT transmitted valid output data signals become the first through the third local data buses LIO_P1 Transfer port PORT0.

When next the normal read operation of the multi-port memory device will be described. The normal read means that data is from a specific Address of a corresponding bank to be read.

With reference to 1 the input signals (see 4D and 4E ) corresponding to the reading operation in the first port PORT0 via the receiving pad RX entered in series and the parallelizer 411 Parallelizes the input signals to output the valid 26-bit signals.

The valid 26-bit signals output from the first port PORT0 become the bank selector through the second global data buses GIO_IN 65 the second bank controller BC1 controlling the second bank BANK1. At this time, be as the bank voters 65 the second bank control device BC1 is connected by the second local data buses LIO_BIN to the second global data buses GIO_IN, which also receive signals from the second to fourth ports PORT1 to PORT3 as well as from the first bank BANK0.

Accordingly assign the 26-bit signals input from ports PORT0 to PORT3 the 8-bit bank select signals Pi_BK <0: 7>, with the corresponding ones Banks through bank selection signals Pi_BK <0: 7> are selected. Since only the bank selection signal P0_BK <1> is activated, it receives second bank controller BC the BANK1 the 26-bit signals (which are not valid signals are not from the second to fourth ports PORT0 to PORT3, but she receives the valid ones Input data signals P0_RX <0:17> from the first port PORT0.

The state machine 63 the second bank controller BC1 activates the internal active signal ACT and the read command signal READ using the valid 18-bit input data signals P0_RX <0:17>, generates the row / column addresses XADD and YADD of the second bank BANK1 by the row / column address generators 633 and 634 using the activated internal active signal ACT and the activated read command signal READ, the pipe input strobe signal asserts PINSTROBE and the pipe output control signals POUT through the read data pipe controller 635 and activates the control signal DRVEN_P by the data output controller 636 ,

Triggered by the read command signal READ input from the second bank controller BC1, the 64-bit data signals from the second bank BANK1 are amplified by the 64 data bus sense amplifiers through the data lines and sent to the serializer 62 output.

The in the serializer 62 input 64-bit output signals are serialized into 16-bit signals triggered by the pipe input strobe signal PINSTROBE and the pipe output control signals POUT <0: 3>. That is, the serializer 62 converts the 64-bit output signals into four serial signal units, each of which includes 16 bits, temporarily stores them and gives them to the port selector one after the other 66 in units of 16 bits.

The port selector 66 successively outputs the data signals DO <0:15> as the valid output data signals P0_DATA <0:15> in units of 16 bits to the selected port PORT0 through the first global data buses GIO_OUT triggered by the control signals DRVEN_P <0: 3> the Bank selection signals BK0_P <0: 3> correspond as in 5 is illustrated.

As in 3 1, the first port PORT0 receives the valid output data signals P0_DATA <0:15> through the first global data buses GIO_OUT in a parallel manner. The valid output data signals P0_DATA <0:15> are from the serializer 421 serialized and transmitted through the transfer pad TX to the corresponding external device.

Next, a normal writing operation of the multi-port memory device will be explained. By the normal writing operation is meant writing of data at a specific address of the corresponding bank. The input signals of four frames are received by the reception pad RX. The first frame corresponds to the command signal (hereinafter referred to as a command frame) (see 4B ), and the remaining three frames correspond to data signals (hereinafter referred to as data frames) (see 4C ). Each of the input signals is 16 bits. That means the input signals 64 Bits are.

Regarding 1 For example, the command frame and the data frames corresponding to the writing operation are serially input through the receiving pad RX into the first port PORT0, and the parallelizer 411 Parallelizes the serial frame signals to output the valid 26-bit signals.

The valid 26-bit signals output from the first port PORT0 become the bank selector through the second global data buses GIO_IN 65 the second bank controller BC1 controlling the second bank BANK1. At this point, as the bank voter 65 the second bank controller BC1 is connected by the second local data buses LIO_BIN to all second global data buses GIO_IN receiving signals from the second to fourth ports PORT1 to PORT3 as well as the first bank BANK0.

Accordingly For example, the valid 26-bit signals input from the ports PORT0 to PORT3 have the 8-bit bank select signals Pi_BK <0: 7> on, with the corresponding Banks through bank selection signals Pi_BK <0: 7> are selected. Since only the bank selection signal P0_BK <1> is activated, it receives second bank controller BC1 of the second bank BANK1 receives the 26-bit signals (which no valid ones Signals are) from the second to fourth ports PORT1 to PORT3 not, but receives the valid ones Input data signals P0_RX <0:17> from the first port PORT0.

The state machine 63 the second bank controller BC 1 activates the internal active signal ACT and the write command signal WRITE using the valid input data signals P0_RX <0:17>, generates the row / column addresses XADD and YADD of the bank BANK1 by the row / column address generators 633 and 634 using the activated internal active signal ACT and the activated write command signal WRITE, and activates the input data strobe signal DSTROBE16 <0: 3> and DSTROBE64 by the input data strobe generator 632 ,

In this state, the successively inputted valid 16-bit bank data signals BRX <0:15> corresponding to the valid data signals among the valid data signals BRX <0:15> of the three data frame signals by the parallelizer 61 (please refer 6 ) are parallelized into the 64 bits (16x4). At the same time, the 64-bit signals in the memory cell array 10 Bank BANK1 is inscribed by write driver W / D.

As explained above For example, the 64 data bits are simultaneously written in the memory cells when the four frame signals (command frame and data frame) during the Write sequentially be entered into a bank. If another command (interrupt operation) is executed before all four frames entered are only entered up to this time Data inscribed in the memory cells.

A such a multi-port memory device having the plurality of ports requires a test device running at a high speed works to test the ports, using a serial I / O interface is supported at a high speed. The conventional However, test device can not use the serial I / O interface assist at high speeds, so that a time for testing the multiport storage device.

Accordingly it is to reduce the time to test the multiport memory device required the serial I / O interface into a parallel I / O interface too convert.

SUMMARY THE INVENTION

It is therefore an object of the present invention to provide a multi-port memory device which performs high-speed serial data communication with external devices. The multi-port memory device may support various I / O data transmission modes, such as single data rate (SDR), double data rate (DDR) and quadruple data rate (QDR), and a time to Test the multiport memory device by reducing a Perform core test in a parallel I / O interface.

It is therefore a further object of the present invention, a Semiconductor memory device which provides data communication in a parallel I / O interface. The semiconductor memory device can use different I / O data transfer modes while support a test mode and reduce a time for testing a multi-port memory device.

In accordance One aspect of the present invention is a semiconductor memory device provided with: a plurality of first pads; a variety from ports to run a serial data communication with external devices via the first pads; a variety of benches to run a parallel data communication with the plurality of ports; one Variety of global data buses to support parallel data communication between the plurality of ports and the plurality of banks; and a test mode controller for performing a core test with different data transmission modes by converting serial data communication to parallel Data communication during a core test mode.

In accordance Another aspect of the present invention is a semiconductor memory device provided a parallel data communication with a external device executes, wherein the semiconductor memory device comprises: a Mode setting unit for generating a mode setting signal triggered by a mode register enable signal input in parallel by a plurality of first pads while a core test mode; a clock generator unit for receiving a external clock signal and for generating first and second internal Triggered clock signals by the mode setting signal; and a test input / output (I / O) controller for controlling input and output of an input / output (I / O) data signal through a plurality of second pads during the core test mode in synchronization with the first and second internal clock signals.

SHORT DESCRIPTION THE DRAWINGS

The above and other objects and features of the present invention will be described by the following description of the preferred embodiments clearly, in connection with the accompanying drawings, of which:

1 Fig. 10 is a block diagram of a conventional multi-port memory device;

2 a schematic diagram of an in 1 illustrated bank is;

3 a block diagram of an in 1 illustrated ports;

4 is a diagram showing a frame format of one in the port 1 input signal is;

5 a block diagram of an in 1 shown bank control device;

6 a block diagram of an in 6 shown state machine is;

7 Fig. 16 is a diagram illustrating a transmission path of an input signal from the port to the bank;

8th Fig. 12 is a diagram illustrating a transmission path of an output signal from the bank to the port;

9 Fig. 10 is a block diagram of a multi-port memory device in accordance with an embodiment of the present invention;

10 a block diagram of an in 9 illustrated test I / O controller;

11 Fig. 16 is a diagram illustrating a writing process classified by various data transmission modes; and

12 Fig. 10 is a diagram illustrating a reading process classified by various data transmission modes

DETAILED DESCRIPTION OF THE INVENTION

A Semiconductor memory device in accordance with exemplary versions The present invention will be described with reference to the accompanying drawings Drawings described in detail.

9 FIG. 10 is a block diagram of a multi-port memory device in accordance with an embodiment of the present invention. FIG. A normal operation of the multi-port memory device of the present invention is substantially the same as that of the conventional multi-port memory device. Hereinafter, a DRAM core test mode of the multi-port memory device will be explained.

The multi-port memory device has the following one mode setting unit 91 , a clock generator unit 92 and a test input / output loading (I / O) control unit 93 , The mode setting unit 91 outputs first through fourth mode setting signals TQDR0, TQDR1, TDDR and TSDR triggered by a mode register enable signal MREB and first and second data transmission mode selection signals DTT0 and DTT1. Here, the mode register enable signal MREB is enabled during the DRAM core test mode. The clock generator unit 92 receives an external clock signal CLK from an external pad and generates first and second internal clock signals TCLK and DCLK triggered by the first to fourth mode setting signals TQDR0, TQDR1, TDDR and TSDR. The test I / O control unit 93 receives external signals such as commands, addresses and control signals (hereinafter referred to as a test signal) in parallel through transmission pads TXi and reception pads RXi and an input data signal from test pads DQi to connect them to banks through one first global data bus GIO_IN triggered by the mode register enable signal MREB to transmit. Here, "i" is a positive integer, and in this case, data is serially input / outputted in normal operation by the transmission pads TXi and reception pads RXi.

In detail, the mode setting unit displaces 91 the multi-port memory device in the DRAM core test mode based on the mode register enable signal MREB input via an external path, and decodes the first and second data transmission mode selection signals DTT0 and DTT1 input from the test I / O control unit 93 through the first global data bus GIO_IN; to output the first to fourth mode setting signals TQDR0, TQDR1, TDDR and TSDR. Here, the first and second data transmission mode selection signals DTT0 and DTT1 correspond to two preset bits among a plurality of bits constituting the test signal input through the transmission pads TXi and the reception bits RXi. Further, the mode setting unit gives 91 a bank selection signal BKEN by decoding an external control signal inputted from another external pad except for the test pads DQi, the transmission pads TXi and the reception pads RXi.

The test I / O control unit 93 receives the test signal through the transmission pads TXi and the reception pads RXi of ports to transmit them to the first global data bus GIO_IN triggered by the mode register enable signal MREB. Furthermore, the test I / O control unit receives 93 it inputs the input data signal through the test pads DQi to transmit it to the first global data bus GIO_IN in synchronization with the first and second internal clock signals TCLK and DCLK at a different period according to a data transmission mode, or receives from the banks an output data signal through a second global data bus GIO_OUT to output to the test pads DQi in synchronization with the first and second internal clock signals TCLK and DCLK.

10 is a block diagram of in 9 illustrated test I / O controller 93 ,

The test I / O controller 93 has a command decoder 931 , a demultiplexer DEMUX, a multiplexer MUX and a tri-state buffer TB. The command decoder 931 decodes the test signal input through the transmission pads TXi and the reception pads RXi to generate internal command signals such as a write command WRITE, a read command READ, and a buffer control signal COUT triggered by the mode register enable signal. Furthermore, the command decoder buffers 931 the input data signal input through the test pads DQi to output the buffered input data signal to the demultiplexer DEMUX.

Of the Demultiplexer DEMUX transmits the buffered Input data signal to the first global data bus GIO_IN triggered by the write command WRITE. If, for example, the WRITE write signal is activated with a logic "HIGH" level, the demultiplexer transmits DEMUX the buffered input data signal to the first global data bus GIO_IN.

Of the Multiplexer MUX receives the output data signal through the second global data bus GIO_OUT, by the output data signal to the tri-state buffer TB triggered by output the read command READ. If, for example, the read command READ is activated with a logical "HIGH" level is, transfers the multiplexer MUX the output data signal from the second global data bus GIO_OUT to the tri-state buffer TB.

The tri-state buffer TB buffers the output data signal output from the multiplexer MUX, and outputs it triggered by the buffer control signal COUT or redirects the input data signal inputted through the test pads DQi to the command decoder 931. For example, when the buffer control signal COUT is activated at a logical "HIGH" level, the tri-state buffer TB outputs the output data signal outputted from the multiplexer MUX to the test pads DQi When the buffer control signal COUT is at a logic "LOW" level is deactivated, the tri-state buffer TB passes the test signal input by the test pads DQi to the command decoder 931 around.

During the normal mode, the output data signal read out from the banks is passed through transmit the second global data bus GIO_OUT to a corresponding port, and then the output data signal is sent through the transfer pads TXi to the external devices. In addition, an input signal input from the external devices is input to the ports through the reception pads RXi, and then the input signal is transmitted to the banks through the first global data bus GIO_IN.

As described above, in the multi-port memory device, the ports receive only the input signal from the reception pads RXi. Accordingly, it is required that the test I / O control unit 93 transmits the test signal input in parallel from an external test device through the transmission pads TXi and the reception pads RXi during the DRAM core test mode to the first global data bus GIO_IN.

meanwhile For example, the receive pads RXi will serve as an input pad for receiving the input signal while of the normal mode and also as an input pad for reception the test signal during used by the DRAM core test mode. Accordingly, each port is configured to the test signal during not to receive the DRAM core test mode, or even if everyone Port the test signal during is the DRAM core test mode he configured not to send the test signal to the first global one To transfer data bus GIO_IN Example, the ports through the mode register enable signal Controlled MREB. It means that the test signal is not transmitted to the first global data bus GIO_IN is set by the mode register enable signal MREB with a logic "LOW" level during the DRAM core test mode is released.

Each bank is capable of performing read and write operations in synchronization with the first and second internal clock signals TCLK and DCLK generated by the clock generator unit 92 be spent trained.

11 and 12 Figures are diagrams illustrating the reading and writing process classified by various data transmission modes.

Hereinafter, the reading and writing operation of the multi-port memory device during the DRAM core test mode will be described with reference to FIG 11 and 12 explained in detail.

When Reference, a first quad data rate (QDR) mode "QDR0" is selected when the first mode setting signal TQDR0 is activated; a second QDR mode "QDR1" is selected when the second mode setting signal TQDR1 is activated; a double data rate (DDR) mode "DDR" is selected when the third mode setting signal TDDR is activated; and a single rate (SDR) mode "SDR" is selected when the fourth mode setting signal TSDR is activated.

If in the case of the first QDR mode "QDR0" the first internal Clock TCLK has a first period T, is the second internal Clock DCLK designed so that it has a second period, which essentially the same as the half period T / 2 of the first one internal clock TCLK is. This becomes the first internal clock signal TCKL is used as a reference clock of command, address and control signals, and the second internal clock signal DCLK is used as a reference clock used by I / O data signals. In the first QDR mode "QDR0" becomes an I / O data signal group DQ <0: 3> in synchronization with each rising and falling edge of the second internal clock signal DCLK entered / issued through the test pads DQi.

in the Case of the second QDR mode "QDR1" has the second one internal clock DCLK the first period T is essentially the same as that of the first internal clock TCLK and one by half the period T / 2 delayed Waveform, that is, a phase of the second internal clock DCLK is shifted by 90 degrees. In the second QDR mode "QDR1", the I / O data signal group becomes DQ <0: 3> in synchronization with each rising and falling edge of the first and second internal clock signals TCLK and DCLK through the test pads DQi input / output. As a result, a data processing rate of the second QDR mode "QDR1" is the same as that of the first QDR mode "QDR0", which becomes the first internal clock signal TCLK also as a reference clock of the command, address and control signals used.

in the Case of DDR mode "DDR" becomes the second fixed internal clock DCLK with a logic "HIGH" level or a logic "LOW" level, or has the same waveform as the first internal clock signals TCLK on. Here, the second internal clock DCLK having the logical "LOW" level is an example fixed. In such DDR mode "DDR", the I / O data signal group DQ <0: 3> becomes in synchronization with each rising and falling edge of the first internal Clock signals TCLK entered / output through the test pads DQi. When As a result, a data processing rate of the DDR mode "DDR" is one-half that of the first and second QDR modes "QDR0" and "QDR1". Here is the first internal clock signal also as the reference clock of the command, Address and control signals used.

In the case of the SDR mode "SDR", the second internal clock DCLK is fixed with a logic "HIGH" level or a logic "LOW" level SDR mode "SDR", the I / O data signal group DQ <0: 3> is input / outputted through the test pads DQi in synchronization with the rising or falling edge of the first internal clock signal TCLK, as a result, the data processing rate of the SDR mode is " SDR "is one half of that of the DDR mode" DDR. "Here, the first internal clock signal is also used as the reference clock of the command, address and control signals.

Regarding 9 to 11 the process of writing the multiport memory device will be explained.

During the DRAM core test mode, when the mode register enable signal MREB having a logic "LOW" level is input from the external pad, the test I / O controller transmits 93 the test signal inputted through the transmission pads TXi and the reception pads RXi to the first global data bus GIO_IN.

The mode setting unit 91 decodes the first and second data transmission mode selection signals DTT0 and DTT1 loaded on the first global data bus GIO_IN and outputs the first to fourth mode setting signals TQDR0, TQDR1, TDDR and TSDR triggered by the mode register enable signal MDREB. Furthermore, the mode setting unit generates 91 the bank selection signal BDEN by decoding the external control signal.

The clock generator unit 92 receives the external clock signal CLK and generates the first and second internal clock signals TCLK and DCLK triggered by the first to fourth mode setting signals TQDR0, TQDR1, TDDR and TSDR. Here, the first and second internal clock signals TCLK and DCLK are in accordance with the data transmission mode, such as the first and second QDR modes QDR0 and QDR1, the DDR mode and the SDR mode, in FIG 11 shown.

The test I / O control unit 93 receives the input data signal through the test pads DQi in synchronization with the first and second internal clock signals TCLK and DCLK.

In particular, the test I / O controller receives 93 in the first QDR mode "QDR0", the input data signal through the test pads DQi in synchronization with each rising and falling edge of the second internal clock signal DCLK In the second QDR mode "QDR1", it receives the test I / O control unit 93 in synchronization with each rising and falling edge of the first and second internal clock signals TCLK and DCLK. In DDR mode "DDR" it receives the test I / O control unit 93 in synchronization with each rising and falling edge of the first internal clock signal TCLK. In the SDR mode "SDR", it receives the test I / O control unit 93 in synchronization with one of the rising and falling edges of the first internal clock signal TCLK.

Furthermore, the test I / O control unit generates 93 the write command WRITE by decoding the test signal inputted through the transmission pads TXi and the reception pads RXi and, triggered by the write instruction WRITE, transmits the input data signal inputted through the test pads DQi to the first global data bus GIO_IN. Here, the test signal is input through the transfer pads TXi and the receive pads RXi on a 1-bit basis in parallel. As the bit count of the test signal increases, the number of bits can be increased by adding dummy pads.

A corresponding bank controller is triggered by the mode setting unit 91 bank selection signal BKEN outputs the test signal and input data signal loaded on the first global data bus GIO_IN and decodes the test signal to thereby generate a write command signal, specific row / column addresses of a memory cell of a core area for writing, the input data signal.

Triggered by the write command signal output from the bank controller writes the bank corresponding to the bank controller the input data signal into the specific row / column addresses the memory cell.

With reference to 12 the reading process of the multi-port memory device will be explained.

The test I / O control unit 93 transmits the test signal inputted through the transmission pads TXi and the reception pads RXi to the first global data bus GIO_IN. In this case, the test signal corresponds to the read command READ.

The mode setting unit 91 decodes the first and second data transmission mode selection signals DTT0 and DTT1 loaded on the first global data bus GIO_IN and outputs the first to fourth mode setting signals TQDR0, TQDR1, TDDR and TSDR triggered by the mode register enable signal MREB. Furthermore, the mode setting unit generates 91 the bank selection signal BKEN by decoding the external control signal.

The clock generator unit 92 receives the external clock signal CLK and generates the first and second internal clock signals TCLK and DCLK triggered by the first to fourth mode setting signals TQDR0, TQDR1, TDDR and TSDR. Here are the first and second internal clock signals TCLK and DCLK according to the data transmission mode, such as the first and second QDR modes QDR0 and QDR1, the DDR mode and the SDR mode, in FIG 12 shown.

A corresponding bank controller receives this at the first global Data bus GIO_IN loaded test signal triggered by the bank select signal BKEN and decodes the test signal, thereby generating a read command signal, specific row / column addresses of the memory cell of the core area to generate the input data signal.

The bank corresponding to the bank controller reads the output data signal from the specific row / column addresses of the memory cell triggered by the read command signal and transmits the output data signal to the test I / O control unit 93 through the second global data bus GIO_OUT.

The test I / O control unit 93 generates the read command READ by decoding the test signal, and outputs the output data signal to the test pads DQi triggered by the read command READ in synchronization with the first and second internal clock signals TCLK and DCLK.

As in 12 is shown, outputs the test I / O control unit 93 the output data signal according to the data transmission mode, such as the first and second QDR modes QDR0 and QDR1, the DDR mode and the SDR mode. As a reference, a burst length "BL" has the meaning of the bit number of the output data signal A data output latency "tDOL" is a period for executing the read operation for reading data of the memory cell and has substantially the same value as the external clock signal CLK plus a Cas Latency CL, that is, "CLK + CL." A delay "tAC" is a time from a start time of the data output latency "tDOL" to a real reading time of data of the memory cell, taking into account a load time by a local data bus which is on the Corebereich is arranged.

In particular, the test I / O control unit gives 93 in the first QDR mode "QDR0", the output data signal is in synchronization with each rising and falling edge of the second internal clock signal DCLK to the test pads DQi, for example, if the bank is in four quarters with a 16-bit burst length, i.e. BL = 16, the output data signal is output on a 4-bit basis for each quarter in a row.

In the second QDR mode "QDR1" is the test I / O control unit 93 the output data signal in synchronization with each rising and falling edge of the first and second internal clock signals TCLK and DCLK.

In the DDR mode "DDR" gives the test I / O control unit 93 the output data signal in synchronization with each rising and falling edge of the first internal clock signal TCLK. For example, the input data signal is simultaneously written in two memory cells for 4 clocks with an 8-bit burst length, that is, BL = 8. During the read operation, the output data signal is output by dividing 4-bit data of each quarter on a 2-bit basis. Here, an earlier 8-bit input data signal and a later 8-bit input data signal are substantially the same data pattern. A duration of the read operation is extended to 4 clocks, more than those of the first and second QDR modes "QDR0" and "QDR1" and the SDR mode "SDR".

In the SDR mode "SDR" gives the test I / O control unit 93 the output data signal in synchronization with one of the rising and falling edges of the first internal clock signal TCLK. For example, the 4-bit data of each quarter having substantially the same input data signal is written in the memory cell having a 4-bit burst length, that is, BL = 4. During the read operation, the 4-bit data of each quarter is compressed, and the output data signal is output at a logic "LOW" or "HIGH" level in accordance with a status of the compressed data, for example all or nothing.

As described above uses the multiport memory device in accordance with the present invention during The DRAM core test has a parallel I / O interface and supports several I / O data transfer modes, such as SDR, DDR and QDR. As a result, it is possible to have a Reduce time to test the multiport memory device, by the DRAM core test based on the I / O data transfer modes selectively performed becomes.

Even though the description of the multiport memory device with four ports and eight benches has been made, the present invention is not limited to this Structure limited. That is, the invention applies to any multi-port memory device a serial data communication between a plurality of ports and external devices and a parallel data communication between a plurality of benches and running the ports, can be applied. Furthermore there are no restrictions in the positions of ports and banks.

Farther Is it possible, the first and second internal clock signals TCLK and DCLK Receive two external clock signals, not just a clock signal Generate CLK. At this time, each of the two external assigns Clock signals each have the same waveform as that of the first one and second internal clock signals TCLK and DCLK.

The The present invention may be applied to any multi-port memory device applied, such as to a general DRAM device, which a parallel data communication between a plurality of banks and runs the ports.

The present application contains the subject of the Korean patent application with the Number 2006-33749, which on April 13, 2006 at the Korean Patent Office has been registered, the entire contents herein is incorporated by reference.

While the present invention with reference to certain preferred embodiments has been described, it is for the skilled person will appreciate that various changes and modifications accomplished can be without departing from the scope of the invention, as in the following claims is fixed.

Claims (39)

A semiconductor memory device, comprising: a Variety of first pads; a variety of ports for running a serial data communication with external devices through the first pads; a variety of benches to run a parallel data communication with the plurality of ports; a Variety of global data buses to support parallel data communication between the plurality of ports and the plurality of banks; and a Test mode controller for performing a core test by Conversion of serial data communication to parallel Data communication during a selected one Core test mode. A semiconductor memory device according to claim 1, wherein the test mode controller comprises: a mode setting unit for receiving a data transmission mode signal input through the global data buses and for generating an during of the core test mode enabled mode setting signal triggered by a mode register enable signal; a Clock generator unit for receiving an external clock signal and for generating first and second internal clock signals triggered by the mode setting signal; and a test input / output (I / O) control unit to redirect a parallel input through the first pads Test signal to the global buses and to transmit an I / O data signal between a plurality of second pads and the banks triggered the global data buses by the mode register enable signal in synchronization with the first and second internal clock signals. A semiconductor memory device according to claim 2, wherein the mode setting signal is a data transmission mode of the I / O data signal sets. A semiconductor memory device according to claim 3, wherein the first and second internal clock signals are command signals, address signals and synchronize the I / O data signals. A semiconductor memory device according to claim 2, wherein the first internal clock signal as a reference clock during the Core test mode generated and used command signals and address signals is used. A semiconductor memory device according to claim 2, wherein the second internal clock signal as a reference clock during the Core test mode through the second pads input and output I / O data signals is used. A semiconductor memory device according to claim 3, wherein the first internal clock signal has substantially the same waveform regardless of the data transfer mode having. A semiconductor memory device according to claim 7, wherein the second internal clock signal has a different waveform Data transfer mode has accordingly. A semiconductor memory device according to claim 8, wherein the second internal clock signal is half a period of the first internal clock Clock signal has. A semiconductor memory device according to claim 9, wherein the test I / O controller transmits the I / O data signal through the second Pads in sync with each rising and falling edge of the second internal clock signal inputs and outputs. A semiconductor memory device according to claim 8, wherein the second internal clock signal is substantially the same Period as the first internal clock and has a phase which shifted by 90 degrees compared to the first internal clock signal is. Semiconductor memory device according to An 11, wherein the test I / O controller inputs and outputs the I / O data signal through the second pads in synchronization with each rising and falling edge of the first and second internal clock signals. A semiconductor memory device according to claim 8, wherein the second internal clock signal is one of a logical "LOW" level and a regardless of the logical "HIGH" level of the first internal clock signal. A semiconductor memory device according to claim 13, wherein the test I / O controller transmits the I / O data signal through the second Pads in sync with each rising and falling edge of the first internal clock signal inputs and outputs. A semiconductor memory device according to claim 13, wherein the test I / O controller transmits the I / O data signal through the second Pads in sync with each rising or falling edge of the first internal clock signal inputs and outputs. A semiconductor memory device according to claim 7, wherein the second internal clock signal is substantially the same Waveform as that of the first internal clock signal has. A semiconductor memory device according to claim 16, wherein the test I / O controller transmits the I / O data signal through the second Pads in sync with each rising and falling edge of the second internal clock signal inputs and outputs. A semiconductor memory device according to claim 16, wherein the test I / O controller transmits the I / O data signal through the second Pads in sync with each rising or falling edge of the second internal clock signal inputs and outputs. A semiconductor memory device according to claim 2, wherein the global data buses comprise: a first bus for transmission of the test signal input by the first pads and that of the first pad second pads input data signal to the banks; and one second bus for transmission of the benches outputted output signal to the second pads. A semiconductor memory device according to claim 19, while during In the core test mode, the test I / O control unit sends the test signal to Decoding generation of a write command and a read command, the input data signal from the second pads to the first bus is triggered by transmits the write command and that Output data signal from the second bus to the second pads triggered by the Read command transmits. A semiconductor memory device according to claim 19, wherein the test I / O control unit comprises: a command decoder for decoding the test signal input by the first pad for generating a write command and a read command, and for Buffering of the input data signal input through the second pad triggered by the mode register enable signal; a demultiplexer for transmission of the buffered input data signal to the first bus triggered by the write command; and a multiplexer for receiving the output data signal from the second bus to output the output data signal to the second one Pads triggered by the read command. A semiconductor memory device according to claim 21, the test I / O controller continues to provide a tri-state buffer for selectively buffering the output data signal output by the multiplexer and for redirecting the input data signal input through the second pad triggered by a buffer control signal output from the instruction decoder. A semiconductor memory device, comprising: a Mode setting unit for generating a mode setting signal triggered by one through a plurality of first pads during a core test mode parallel input mode register enable signal; a clock generator unit for receiving an external clock signal and for generating first and second internal clock signals triggered by the mode setting signal; and a test input / output (I / O) control unit for control an input and output of an input / output (I / O) data signal through a plurality of second pads during the core test mode in synchronization with the first and second internal clock signals. A semiconductor memory device according to claim 23, wherein the mode setting signal is a data transmission mode of the I / O data signal, which is input and output by the second pads. A semiconductor memory device according to claim 24, wherein the first and second internal clock signals are command signals, Address signals synchronize and the I / O data signal a data transfer rate corresponding to the data transmission mode having. A semiconductor memory device according to claim 23, wherein the first internal clock signal as a reference clock for during the Core test mode generated and used command signals and address signals is used. A semiconductor memory device according to claim 23, wherein the second internal clock signal is used as a reference clock during the Core test mode entered and output through the second pads I / O data signal is used. A semiconductor memory device according to claim 24, wherein the first internal clock signal is substantially the same waveform regardless of the data transfer mode having. A semiconductor memory device according to claim 28, wherein the second internal clock signal is a different waveform the data transfer mode has accordingly. A semiconductor memory device according to claim 29, wherein the second internal clock signal is half a period of the first one internal clock signal has. A semiconductor memory device according to claim 30, wherein the test I / O controller transmits the I / O data signal through the second Pads in sync with each rising and falling edge of the second internal clock signal inputs and outputs. A semiconductor memory device according to claim 29, wherein the second internal clock signal is substantially the same Period as the first internal clock and has a phase which shifted by 90 degrees compared to the first internal clock signal is. A semiconductor memory device according to claim 32, wherein the test I / O controller transmits the I / O data signal through the second Pads in sync with each rising and falling edge the first and second internal clock signals input and output. A semiconductor memory device according to claim 29, wherein the second internal clock signal is one of a logical "LOW" level and a regardless of the logical "HIGH" level of the first internal clock signal. A semiconductor memory device according to claim 34, wherein the test I / O controller transmits the I / O data signal through the second Pads in sync with each rising and falling edge of the first internal clock signal inputs and outputs. A semiconductor memory device according to claim 34, wherein the test I / O controller transmits the I / O data signal through the second Pads in sync with each rising or falling edge of the first internal clock signal inputs and outputs. A semiconductor memory device according to claim 28, wherein the second internal clock signal is substantially the same Waveform as the first internal clock signal has. A semiconductor memory device according to claim 37, wherein the test I / O controller transmits the I / O data signal through the second Pads in sync with each rising and falling edge of the second internal clock signal inputs and outputs. A semiconductor memory device according to claim 37, wherein the test I / O controller transmits the I / O data signal through the second Pads in sync with each rising or falling edge of the second internal clock signal inputs and outputs.