DE102006042115A1 - Circuit arrangement and method for operating a circuit arrangement - Google Patents

Abstract

The circuit arrangement comprises a control circuit (400) and a memory chain (500). The memory chain (500) comprising a first plurality n of memory circuits (501, 511, 521, 531), wherein at least one memory circuit (501, 511, 521, 531) comprises a non-volatile memory cell (502, 512, 522, 532) and a first output (505, 515, 525, 535) for outputting an output signal (DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4). An output (413) of the control circuit (400) is coupled to an input (503) of the first memory circuit (501).

Description

The The present invention relates to a circuit arrangement with a Control circuit and a memory chain, a use of the circuit arrangement and a method of operating a circuit arrangement.

One Memory can be non-volatile Have memory cells and data such as serial numbers or trim settings of analog circuits in a semiconductor body.

The document US 5,384,746 shows a circuit and a method for storing and retrieving data. The circuit uses a fuse, English fuse, to store.

task It is the object of the present invention to provide a circuit arrangement as well to provide a method of operating a circuit arrangement which can store more than one bit and are flexible.

These The object is with the subject of claim 1 and the Process according to claim 15 solved. Further developments and refinements are each the subject of dependent Claims.

According to the invention a circuit arrangement a control circuit and a memory chain, which is coupled to the control circuit. The storage chain includes a first plurality n of memory circuits. At least one memory circuit of the first plurality n of memory circuits comprises a non-volatile memory cell, an input and a first output. The control circuit is connected to the input of the first memory circuit.

The Control circuit provides information on the output side, the be forwarded to the storage chain. The information provided are supplied to the memory circuits. At least one memory circuit provides an output signal at the respective first output.

It is an advantage of the circuit arrangement that with the plurality n of memory circuits a plurality n of non-volatile Memory cells operable and thus a larger amount of data than 1 bit storable is. The first plurality n is flexible to the amount of data to be stored customizable. It is an advantage of the circuit that the necessary functions for the memory circuits are combined in a control circuit are.

In an embodiment can the information provided to the memory circuits in serial Form be forwarded. Alternatively, these can be in parallel form fed to the memory circuits become. Preferred may the information partly in serial form and partly in parallel Form be forwarded to the memory circuits.

Of the Input of at least one memory circuit of the first plurality n of memory circuits comprises a data input, a clock input and a control input. The control circuit is connected to the data input the input of the first memory circuit connected.

Of the Data input can have multiple lines. Preferably comprises the data input a line.

Of the Clock input may preferably have a line. The clock input is applied with a clock signal.

Of the Control input can have a line. Preferably, the Control input several lines. A control signal is the control input fed. Preferably, the control signal comprises a plurality of signals.

At least a memory circuit of the first plurality n of memory circuits includes the non-volatile Memory cell, the data input, the clock input and the control input as well as the first exit. At least one memory circuit can mean that exactly one memory circuit of the first plurality n of memory circuits this includes or alternatively that several Memory circuits of the first plurality n of memory circuits each include this. This preferably means that each memory circuit from the first plurality of memory circuits this includes.

In an embodiment the memory circuits are connected in series. It is the Data input of the first memory circuit with an output of Control circuit connected. The data input of another memory circuit is connected to a second output of the respective upstream memory circuit connected. The control signal or the plurality of signals of the control signal are sent from the control circuit in parallel to the plurality n given the memory circuits. It is an advantage of the serial Arrangement of the memory circuit that only a small number of Control and data lines needed being independent of of the first plurality n of the memory circuits.

In one embodiment, the clock signal is supplied to the clock input of the first memory circuit. In a further development of the embodiment the clock signal is fed to at least one further memory circuit. Preferably, the clock signal is supplied to each memory circuit. The clock signal may be provided by the control circuit.

In an embodiment the control circuit provides a first data signal corresponding to the Data input to the first memory circuit is supplied. The first Memory circuit outputs a second data signal at the second output the first memory circuit. In this case, the first memory circuit generates the second data signal in dependence from the clock signal and from the first data signal and the parallel control signals applied to all memory circuits. The second and another memory circuit is respectively at the second output a third or further data signal, depending on provided by a data signal, the control signals and the clock signal which is the data input of the second or further Memory circuit supplied becomes. Advantageously, thus, a data signal from the first memory circuit be looped through to the last memory circuit.

The Clock signal can be used to propagate the data signal from one memory circuit to the next memory circuit trigger.

In a development, one of the last memory circuits a Signal output on. At this a processing signal is provided. Of the Signal output is connected to the control circuit, which is the processing signal supplied becomes. It is an advantage of this embodiment that the control circuit independently be realized by the number of memory circuits to be controlled by it can. The circuit arrangement is thus very flexible with advantage Adaptable to the amount of data to be stored.

In an embodiment the control circuit comprises a sequence control. The flow control may have a microprocessor. Alternatively, the flow control be realized as a logic circuit. The sequence control is preferred realized as a finite state machine, so that effort and space requirements for the Control circuit are kept low.

One Oscillator for delivering an internal clock signal can via a Multiplexer be coupled to the flow control. The internal Clock signal may alternatively be provided by an external clock source become.

In In a further development, the circuit arrangement comprises a bidirectional Connection. The bidirectional connection can be with the flow control and / or with the last memory circuit and / or with the first Memory circuit connected. Preferably, the bidirectional Connection connected to all memory cells.

In an embodiment is the bidirectional connection via a second switch with a first connection of non-volatile Memory cell of the first memory circuit connected. Dependent on The connection can be activated effectively from the control and data signals be. The compound is preferably designed low impedance. A second Connection of non-volatile Memory cell of the first memory circuit can via a programming transistor be connected to a reference potential terminal. It is an advantage this arrangement that between the bidirectional terminal and the Reference potential connection essentially only the non-volatile memory cell the first memory circuit is connected, so that by means of a meter, which are connected externally to the bidirectional connection can, a resistance value of the non-volatile memory cell determined can be. Alternatively, the resistance value at the bidirectional Connection also determined by a measuring circuit on a semiconductor body be that includes the circuitry. It is another Advantage that over this low-resistance access to the non-volatile memory cell of the first Memory circuit the non-volatile Memory cell can be programmed. The programming can by means of a programming current which is the bidirectional connection is supplied.

In In a further development are the first connections of the non-volatile Memory cells connected to each other and via the second switch with the Bidirectional connection connected. The respective second connection the non-volatile Memory cell is over each its own programming transistor with the reference potential connection connected. Thus, over the respective programming transistor to be selected, which is the non-volatile Memory cells connected directly to the bidirectional terminal is, so a resistance value of this non-volatile Memory cell determined or the respective non-volatile memory cell can be programmed by means of a programming current.

The nonvolatile Memory cell may be a mask-programmed memory cell. Alternatively, the non-volatile Memory cell comprise a reversibly programmable memory cell. In a further alternative embodiment, the non-volatile memory cell be implemented as irreversibly programmable memory cell.

The nonvolatile Memory cell can be realized as a resistor, wherein a programming current the resistance value of the non-volatile Memory cell irreversibly enlarged. alternative can the non-volatile Memory cell be a fuse, English Fuse, by means of a Laser beam is programmed. The non-volatile memory cell is preferred realized as a backup, the one by means of a programming current includes fusible resistor. The non-volatile memory cell may have a Metal resistor, a polysilicon resistor or a combined Polysilicon / silicide resistor.

In an alternative embodiment can the non-volatile Memory cell be implemented as an antifuse element, wherein the resistance value irreversibly reducible by means of a programming current. In one embodiment the antifuse element can be used as a diode, in particular as a Zener diode, be realized.

The Circuit arrangement may be formed on a semiconductor body. she can be implemented in a bipolar integration technique. Preferably can by means of complementary metal-oxide-semiconductor integration technology, abbreviated CMOS integration technology, be manufactured and implemented as field effect transistors switch and transistors.

The Circuitry can lead to a permanent storage of data be used. The data can a serial number or an identification number for the semiconductor body. Alternatively, the circuitry may be used to store a trim adjustment an analog circuit, in particular an analog / digital or a Digital / analog converter, be provided. It can be used to repair a Random Access Memory, abbreviated RAM, by accessing redundant cells or columns instead serve broken lines or columns.

According to the invention sees a method for operating a circuit arrangement comprises the following steps: A first data signal is output to a first memory circuit a first plurality n of serially connected memory circuits fed. The first memory circuit comprises a non-volatile memory cell. A control signal becomes parallel to the first plurality n of the memory cells to disposal posed. A second data signal is from the first memory circuit provided on the output side. The second data signal is dependent generated by the control signal and the first data signal. The second data signal is supplied to the second memory circuit. Accordingly, the second memory circuit provides another data signal, which is fed to a downstream memory circuit. The further data signal is dependent on the supplied control signal and the previous data signal. Be with advantage thus looped through the data signals from one memory circuit to the next memory circuit.

In an embodiment a clock signal is supplied to the first memory circuit. Preferably the clock signal is supplied in parallel to all the memory circuits. The second data signal is dependent from the control signal, the first data signal and the clock signal generated.

In an embodiment become the control signal and the first data signal from a control circuit provided. The control signal may comprise a plurality of signals. The clock signal may be supplied externally to the circuitry become. Alternatively, the clock signal may be an internal clock signal provided by the control circuit.

The Invention will be described below in several embodiments with reference to the Figures closer explained. Function or effect same components carry the same Reference numerals. Insofar as circuit parts or components in Their description does not correspond to their function the following figures repeated.

1 shows an exemplary embodiment of a circuit arrangement with a control circuit and a memory chain,

2 shows an exemplary embodiment of the circuit arrangement and

3 shows an exemplary embodiment of a memory circuit with a non-volatile memory cell.

1 shows an exemplary embodiment of a circuit arrangement with a control circuit 400 and a storage chain 500 , The control circuit 400 has a flow control 440 on. The flow control 440 is realized as finite state machine FSM. The storage chain 500 comprises a first plurality n of series-connected memory circuits 501 . 511 . 521 . 531 , In the exemplary embodiment according to 1 the first plurality n is equal to 4. The sequence control 440 is over an exit 413 the control circuit 400 with a data input 503 an input of the first memory circuit 501 connected. The sequence control is via another output 417 in parallel with the control inputs 507 . 517 . 527 . 537 the inputs of the memory circuits 501 . 511 . 521 . 531 connected. The connection of the further output 417 to the control inputs 507 . 517 . 527 . 537 includes several lines. The memory circuits 501 . 511 . 521 . 531 each have a non-volatile memory cell 502 . 512 . 522 . 532 on. The input of the first memory circuit 501 also includes a clock input 504 and a control input 507 , The first memory circuit 501 has a first exit 505 and a second exit 506 on that with a data input 513 the second memory circuit 511 connected is. Furthermore, the input of the second memory circuit comprises 511 a clock input 514 and a control input 517 , The second memory circuit 511 includes a first exit 515 and a second exit 516 that with a data input 523 the next memory circuit 521 connected is. Furthermore, the input of the third memory circuit comprises 521 a clock input 524 and a control input 527 , The third memory circuit 521 includes a first exit 525 and a second exit 526 that with a data input 533 the fourth memory circuit 531 , So the last memory circuit is connected. Furthermore, the input of the fourth memory circuit comprises 531 a clock input 534 and a control input 537 , The fourth memory circuit 531 includes a first exit 535 , a signal output 599 , which with the flow control 440 the control circuit 400 coupled, and a serial data output 598 ,

The flow control 440 puts at the exit 413 a first data signal S1, which is the data input 503 the input of the first memory circuit 501 is forwarded. The flow control 440 puts at an exit 417 a control signal F1 ready in parallel to the control inputs 507 . 517 . 527 . 537 the memory circuits 501 . 511 . 521 . 531 is forwarded. The clock inputs 504 . 514 . 524 . 534 the memory circuits 501 . 511 . 521 . 531 a clock signal SCLK is supplied. At the first exit 505 the first memory circuit 501 a first output signal DATAOUT1 can be tapped off. The first memory circuit 501 generated in response to the control signal 507 , the first data signal S1 and the clock signal SCLK a second data signal S2, via the second output 506 the first memory circuit 501 the data input 513 the second memory circuit 511 is supplied. At the first exit 515 the second memory circuit 511 a second output signal DATAOUT2 can be tapped off. The second memory circuit 511 provides a third data signal S3 at the second output 516 the second memory circuit 511 ready. The third data signal S3 is generated as a function of the control signal F1, the second data signal S2 and the clock signal SCLK. In an analogous way, the third and the fourth memory circuit 521 . 531 at their respective first outputs 525 . 535 a third or fourth output signal DATAOUT3, DATAOUT4 ready. The fourth memory circuit 531 puts at the signal output 599 a processing signal REGLAST ready, the flow control 440 in the control circuit 400 is forwarded. The signal REGLAST signals that an instruction or data information of the last memory circuit 531 was forwarded. By supplying the processing signal REGLAST from the last memory circuit 531 to the control circuit 400 receives the control circuit 400 the information, whether data or a command through the storage chain 500 are looped through. The fourth memory circuit 531 also puts on the serial data output 598 a serial data signal REGOUT comprising the data of the first to the fourth output signal DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4. At the serial data output 598 are the first to the fourth output DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4 serially available.

It is an advantage of the circuit arrangement according to 1 that the control circuit 400 and the storage chain 500 can be designed independently of each other. The control circuit 400 is independent of the plurality n of memory elements in the memory chain 500 ,

In an alternative embodiment, the penultimate memory circuit, ie according to 1 the third memory circuit 521 , the signal output 599 for providing the processing signal REGLAST.

2 shows an exemplary embodiment of the circuit arrangement, which is a development of 1 is. The circuit arrangement may be the control circuit 400 and the storage chain 500 according to 1 include. The control circuit 400 indicates in addition to the flow control 440 a detection circuit 410 and an oscillator 430 on. The detection circuit 410 is with the flow control 440 connected. The oscillator 430 is with an input of a signal switch 420 , subsequently called the MUX gate. An output of the MUX gate 420 is to the flow control 440 and to the second signal inputs 504 . 514 . 524 . 534 the memory circuits 501 . 511 . 521 . 531 connected. The circuit arrangement 700 has a first entrance 701 on, with the recognition circuit 410 connected is. In addition, the circuit arrangement has a second input 702 on top of that with another input of the mux gate 420 and with an input of the detection circuit 410 connected is. The first and the second entrance 701 . 702 each have a buffer for signal adaptation. This buffer can be implemented as an in-circuit buffer or as a peripheral cell.

The circuit arrangement 700 further comprises a bi-directional connection 300 who egg on its output 301 with an entrance 403 the flow control 440 and with the detection circuit 410 connected is. The serial data output 598 the fourth memory circuit 531 is with an entrance 302 of the bidirectional connection 300 connected. The bidirectional connection 300 has a buffer 304 that's the exit 301 is upstream, and another buffer 305 on, the entrance 302 is downstream. A control input 303 of the bidirectional connection 300 is with an exit 411 the flow control 440 connected. A connection 601 , which is realized as a good conductive path, couples the bidirectional connection 300 via a second switch 600 with the analog connections 508 the memory circuits 501 . 511 . 521 . 531 , The connection 601 is directly accessible externally without the interposition of a buffer. A control output 402 the flow control 440 is with a control input of the second switch 600 connected. A not-shown circuit part of the circuit arrangement is via an internal terminal 401 with the flow control 440 connected. The flow control 440 is over an exit 412 connected to a circuit part, not shown, of the circuit arrangement. The first exits 505 . 515 . 525 . 535 the memory circuits 501 . 511 . 521 . 531 are via an internal data bus 597 connected to a circuit part, not shown, of the circuit arrangement. The internal data bus 597 is realized as a parallel bus with the first plurality n of lines.

The detection circuit 410 will be over the first entrance 701 a mode signal MODE, via the second input 702 a signal CLK and via the third input 703 a signal DATA is supplied. The detection circuit 410 recognizes from these signals the mode to be set. An operating mode can be, for example, the parallel readout of the non-volatile memory cells 502 . 512 . 522 . 532 of the four memory circuits 501 . 511 . 521 . 531 mean. Another mode, for example, the serial readout of the non-volatile memory cells 502 . 512 . 522 . 532 in the form of the signal REGOUT at the serial data output 598 be. Another mode of operation may be, for example, programming the non-volatile memory cells 502 . 512 . 522 . 532 about the connection 601 and the second switch 600 to the bidirectional connection 300 mean. Another mode of operation may for example be the connection of one of the non-volatile memory cells 502 . 512 . 522 . 532 also about the connection 601 and the second switch 600 to the bidirectional connection 300 for the purpose of determining the analog resistance value of the non-volatile memory elements 502 . 512 . 522 . 532 be.

A clock signal CLK is via the second input 702 an input of the MUX gate 420 fed. The oscillator 430 On the output side, an internal clock signal ICLK is provided, which is another input of the MUX gate 420 is forwarded. A clock signal SCLK generated by the MUX gate 420 is provided, the flow control 440 and the clock inputs 504 . 514 . 524 . 534 the memory circuits 501 . 511 . 521 . 531 fed. The circuit can thus either with the external clock signal CLK or with the built-in from the internal oscillator 430 generated clock signal ICLK operated.

The oscillator can be over the multiplexer 420 be switched. The internal clock signal SCLK may be from the oscillator 430 or externally over the entrance 702 to be provided.

The flow control 440 can the bidirectional connection 300 set in accordance with the operating mode via a setting signal ES, which of the sequence control 440 at the exit 411 provided. In the serial readout mode, a serial data signal REGOUT is applied to the serial data output 598 the fourth memory circuit 531 provided and via the bidirectional connection 300 provided as signal DATA externally. Data, for example for programming the non-volatile memory cells 502 . 512 . 522 . 532 , are called the signal DATA via the bidirectional connection 300 the entrance 403 the flow control 440 fed the data over the output 413 by means of the data signal S1 to the data input 503 the first memory cell 501 can forward. About the connection 601 can be the bidirectional connection 300 with an analogue connection 508 the memory circuits 501 . 511 . 521 . 531 and in this with the corresponding memory cell 502 . 512 . 522 . 532 get connected. By means of this connection 601 Thus, a resistance value of the non-volatile memory cells 502 . 512 . 522 . 532 be measured in serial order or programmed.

The four output signals DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4 are sent via the internal bus 597 fed in parallel to another circuit part of the circuit arrangement, which is not shown. A POR signal is sent through the internal connector 401 the flow control 440 fed. The POR signal enables the data when the circuit is turned on from the non-volatile memory cells 502 . 512 . 522 . 532 read out, and on the internal bus 597 to provide. The flow control 440 puts at the exit 412 a stand-by signal BUSY, which provides information about the standby state of the control circuit 400 and the storage chain 500 includes.

3 shows an exemplary embodiment of a memory circuit, as in the scarf according to 1 and 2 can be used. Exemplary is in 3 for the plurality n of memory circuits, the first memory circuit 501 shown. Also other than in 3 Shown embodiments of memory circuits are suitable for use in a memory chain, as in 1 or 2 is shown.

The memory circuit 501 has a differential path with a first branch 35 and a second branch 55 on that between a supply voltage connection 9 and a reference potential connection 8th are switched. The first and the second branch 35 . 55 together form a differential current path of a comparator 3 , The comparator 3 has a first amplifier 11 and a second amplifier 21 on. The first amplifier 11 is between a supply connection 12 of the first amplifier 11 and the reference potential connection 8th connected and has a first transistor 30 and a second transistor 40 on, which are connected to each other in series. The transistors 30 . 40 are input side with an input 14 of the first amplifier 11 connected. A knot 31 between the first and second transistors 30 . 40 of the first amplifier 11 makes an exit 15 of the first amplifier 11 , Accordingly, the second amplifier 21 a first transistor 50 and a second transistor 60 on that between a supply connection 22 of the second amplifier 21 and the reference potential connection 8th are switched. The two transistors 50 . 60 of the second amplifier 21 are input side to an input 24 of the second amplifier 21 connected. A knot 51 between the first and second transistors 50 . 60 of the second amplifier 21 serves as an exit 25 of the second amplifier 21 , The first amplifier 11 thus comprises an inverter and the second amplifier 21 also includes an inverter. The two amplifiers 11 . 21 are thus symmetrical. The exit 15 of the first amplifier 11 is with the entrance 24 of the second amplifier 21 and the exit 25 of the second amplifier 21 is with the entrance 14 of the first amplifier 11 connected. The exit 15 of the first amplifier 11 is via a first charging transistor 70 and the exit 25 of the second amplifier 21 is via a second charging transistor 80 with the reference potential connection 8th coupled.

The first branch 35 includes the non-volatile memory cell 502 between the supply connection 12 of the first amplifier 11 and a connection node 2 is switched. The second branch 55 includes a reference element 20 that between the supply connection 22 of the second amplifier 21 and the connection node 2 is switched. The connection node 2 is over a switch 160 with the supply connection 9 coupled. A control input of the switch 160 is to a control output of a logic circuit 509 the memory circuit 501 connected. The connection node 2 is directly with the analogue connection 508 connected. The first and the second charging transistor 70 . 80 are input side to each other and to an output of the logic circuit 509 connected.

The memory circuit 501 in 3 has a programming transistor 150 on, the supply connection 12 of the first amplifier 11 with the reference potential connection 8th combines. The programming transistor 150 is at a control input to an output of the logic circuit 509 the memory circuit 501 connected. In addition, a capacitive compensation element 151 to the supply connection 22 of the second amplifier 21 connected. The compensation element 151 is designed as a transistor.

At the exit 15 of the first amplifier 11 is a first buffer 106 and to the exit 25 of the second amplifier 21 is a second buffer 104 connected. The first buffer 106 includes an inverter comprising two transistors 130 . 140 , on, between the supply voltage connection 9 and the reference potential connection 8th is switched. Accordingly, the second buffer 104 another inverter comprising two transistors 110 . 120 , on, between the reference potential terminal 8th and the supply voltage connection 9 is switched. The inputs of the two transistors 130 . 140 of the first buffer 106 are with the exit 15 of the first amplifier 11 as well as the inputs of the two transistors 110 . 120 of the second buffer 104 with the exit 25 of the second amplifier 21 connected. A knot 102 between the two transistors 110 . 120 of the second buffer 104 forms an output of the second buffer 104 that with the first exit 505 the first memory circuit 501 connected is.

The exit 15 of the first amplifier 11 is via a first switch 100 a writing arrangement 89 with a connection of the logic circuit 509 connected. Likewise, the output 25 of the second amplifier 21 via a second switch 90 the writing arrangement 89 with another connection of the logic circuit 509 connected. The control terminals of the first and second switches 90 . 100 are with each other and with a control input 92 the writing arrangement 89 linked, in turn, with a control output of the logic circuit 509 connected is.

The transistors 30 . 40 . 50 . 60 . 70 . 80 . 90 . 100 . 110 . 120 . 130 . 140 . 150 . 151 and the switch 160 can be realized as field effect transistors, in particular as metal oxide semiconductor field effect transistors, abbreviated MOSFETs.

The logic circuit 509 is the input side to the data input 503, the clock input 504 and the control input 507 the first memory circuit 501 and on the output side with the second output 506 the first memory circuit 501 connected. The logic circuit 509 includes a flip-flop 510 and logic gates.

At the supply voltage connection 9 a supply voltage VDD is connected. The control terminals of the first and the second charging transistor 70 . 80 a load signal LOAD can be fed. The first and the second charging transistor 70 . 80 as well as the switch 160 are turned on in a first operating state. Thus, the first transistor 30 and the first transistor 50 the first and the second amplifier 11 . 21 conducting and the second transistor 40 and the second transistor 60 the first and the second amplifier 11 . 21 switched off. In the two branches of the differential current path 35 . 55 occur due to the different resistances of the non-volatile memory cell 502 and the reference element 20 different sized currents I1, I2 on the supply terminals 12 and 22 cause different voltage potentials. Be the two charging transistors 70 and 80 switched off, detects the compa rator 3 the voltage difference between the supply connections 12 and 22 and stores the result latched in the two amplifiers 11 and 21 from.

Indicates the non-volatile memory cell 502 a smaller resistance than the reference element 20 On, the inverted output voltage NVOUT rises faster than the output voltage VOUT, so that due to the feedback of the first and the second amplifier 11 . 21 the second transistor 60 of the second amplifier 21 as well as the first transistor 30 of the first amplifier 11 conductive and the two other transistors 50 . 40 are switched as a lock. At the exit 15 of the first amplifier 11 is an inverted output voltage NVOUT and at the output 25 of the second amplifier 21 an output voltage VOUT can be tapped.

The programming transistor 150 serves to provide a first current I1 with a high current value passing through the non-volatile memory cell 502 to perform a programming operation. Due to its size, the programming transistor 150 a capacitive load on the supply terminal 12 In the read process described above, the two branches 35 . 55 the differential current path with advantage in the same way capacitive load to a symmetrical design of the comparator 3 to ensure. This is the supply connection 22 of the second amplifier 21 with the compensation element 151 connected. This compensation element 151 is designed as a transistor and provides for the second branch 55 of the differential current path is the same capacitive loading as the programming transistor 150 for the first branch 35 represents.

The logic circuit 509 is the first data signal S1, the clock signal SCLK and the control signal F1 via the data input 503 , the clock input 504 and the control input 507 fed. In response to the clock signal SCLK, the control signal F1 and the data signal S1, the logic circuit 509 using the flip-flop 510 the second data signal S2 and the signals for operating the memory circuit 501 such as the programming signal BURN, the load signal LOAD and the write signal WRITE ready. A data signal DATAIN and a data signal NDATAIN which is inverted for this purpose is output by the logic circuit, depending on the operating mode 509 provided or from the logic circuit 509 receive. The flip-flop 510 can be realized clock-controlled by means of the clock signal SCLK.

Advantageous is the comparator 3 symmetrically constructed and includes a self-holding function by the feedback of the two amplifiers 11 . 21 is achieved.

Advantage is on the two outputs 15 . 25 the first and the second amplifier 11 . 21 one buffer each 104 . 106 downstream, leaving a capacitive load at the output 15 of the first amplifier 11 and a capacitive load at the output 25 of the second amplifier 21 are the same. Thus, downstream circuit parts do not affect the setting and switching operation of the first and second amplifiers 11 . 21 , Advantageously, by means of the writing arrangement 89 the output voltage VOUT with the value of the data signal DATAIN and the inverted output voltage NVOUT with the value of the inverted data signal NDATAIN are provided, as soon as by means of a write control signal WRITE the two switches 90 . 100 are switched on. Advantageously, it is therefore possible to data in a second way in the two amplifiers 11 and 21 save, provided the non-volatile memory cell 502 is low impedance. This allows for test purposes data independent of the non-volatile memory cell 502 get saved.

In an alternative embodiment, another memory circuit 511 . 521 . 531 no clock input for supplying the clock signal SCLK. In an alternative embodiment, the control signal F1 or the further data signals S2, S3, S4 comprise the clock signal SCLK or a signal derived from the clock signal SCLK.

2

connecting node

3

comparator

8th

Reference potential terminal

9

supply terminal

11

first amplifier

12

supply terminal

14

entrance

15

output

20

reference element

21

second amplifier

22

supply terminal

24

entrance

25

output

30

first transistor

31

node

35

first branch

40

second transistor

50

first transistor

51

node

55

second branch

60

second transistor

70

first charging transistor

80

second charging transistor

89

write assembly

90

second switch

91

second entrance

92

control input

100

first switch

101

first entrance

102 103

node

104

second buffer

106

first buffer

110 120, 130, 140

transistor

150

programming transistor

151

compensation element

160

switch

300

bidirectional connection

301

output

302

entrance

303

control

304 305

buffer

400

control circuit

401

internal connection

402

control output

403

entrance

410

detection circuit

411 412, 413, 417

output

420

MUX gate

430

oscillator

440

flow control

500

store chain

501

first memory circuit

511

second memory circuit

521

third memory circuit

531

fourth memory circuit

502 512, 522, 532

non-volatile memory cell

503 513, 523, 533

data input

504 514, 524, 534

clock input

505 515, 525, 535

first output

506 516, 526

second output

507 517, 527, 537

control input

508

analog connection

510

Flip-flop

597

internal bus

598

serial data output

599

signal output

600

second switch

601

connection

700

circuitry

701

first entrance

702

second entrance

BURN

programming signal

BUSY

ready signal

CLK

clock signal

SCLK

internal clock signal

DATA

signal

DATAIN

einzulesendes data signal

DATAOUT1

first output

DATAOUT2

second output

DATAOUT3

third output

DATAOUT4

fourth output

IT

adjustment

F1

control signal

FSM

finite State machine

ICLK

internal clock signal

I1

first electricity

I2

second electricity

LORD

load signal

FASHION

Mode signal

NDATAIN

inverted data signal

NDATAOUT

inverted first data signal

NVout

inverted output voltage

POR

internal control signal

REGLAST

processing signal

REGOUT

serial data signal

S1

first data signal

S2

second data signal

S3

third data signal

S4

fourth data signal

VDD

supply voltage

VOUT

output voltage

VSS

reference potential

WRITE

Write control signal

Claims (22)

Circuit arrangement, comprising - a control circuit ( 400 ) and - a storage chain ( 500 ), comprising a first plurality n of memory circuits ( 501 . 511 . 521 . 531 ), wherein at least one of the memory circuits ( 501 . 511 . 521 . 531 ) - a non-volatile memory cell ( 502 . 512 . 522 . 532 ), - an entrance ( 503 . 504 . 507 . 513 . 514 . 517 . 523 . 524 . 527 . 533 . 534 . 537 ) and - a first exit ( 505 . 515 . 525 . 535 ) for outputting an output signal (DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4) and the input ( 503 ) of the first memory circuit ( 501 ) with an output ( 413 ) of the control circuit ( 400 ) is coupled. Circuit arrangement according to claim 1, wherein the input of at least one of the memory circuits ( 501 . 511 . 521 . 531 ) - a data input ( 503 . 513 . 523 . 533 ), - a clock input ( 504 . 514 . 524 . 534 ) and - a control input ( 507 . 517 . 527 . 537 ). Circuit arrangement according to claim 2, wherein at least two memory circuits ( 501 . 511 . 521 . 531 ) are connected in series and the data input ( 513 . 523 . 533 ) another memory circuit ( 511 . 521 . 531 ) with a second output ( 506 . 516 . 526 ) of the respective upstream memory circuit ( 501 . 511 . 521 ) is coupled. Circuit arrangement according to Claim 3, in which - the data input ( 503 ) of the first memory circuit ( 501 ) a first data signal (S1) is fed, - the clock input ( 504 ) of the first memory circuit ( 501 ) a clock signal (SCLK) is supplied, - the control input ( 507 ) of the first memory circuit ( 501 ) a control signal (F1) is fed, - at the second output ( 506 ) of the first memory circuit ( 501 ) a second data signal (S2) in response to the control signal (F1), the first data signal (S1) and the clock signal (SCLK) is provided and - each at the second output ( 516 . 526 ) of the further memory circuit ( 511 . 521 ) another data signal (S3, S4) in response to the control signal (F1), the clock signal (SCLK) and a further data signal (S2, S3), the data input ( 513 . 523 ) of the further memory circuit ( 511 . 521 ) is provided. Circuit arrangement according to one of claims 1 to 4, wherein a penultimate or a last of the plurality n of memory circuits ( 521 . 531 ) a signal output ( 599 ) connected to the control circuit ( 400 ) for supplying a processing signal (REGLAST) to the control circuit ( 400 ) is coupled. Circuit arrangement according to one of claims 1 to 5, wherein at least one of the memory circuits ( 501 . 511 . 521 . 531 ) comprises: - a first amplifier ( 11 ), which has an entrance ( 14 ) and an output ( 15 ) and between a supply connection ( 12 ) of the first amplifier ( 11 ) and a reference potential terminal ( 8th ), and - a second amplifier ( 21 ), which has an entrance ( 24 ) connected to the output ( 15 ) of the first amplifier ( 11 ) and an output ( 25 ), with the entrance ( 14 ) of the first amplifier ( 11 ) and between a supply connection ( 22 ) of the second amplifier ( 21 ) and the reference potential terminal ( 8th ), - the non-volatile memory cell ( 502 . 512 . 522 . 532 ) between the supply connection ( 12 ) of the first amplifier ( 11 ) and a connection node ( 2 ) connected to the supply connection ( 9 ), and - a reference element ( 20 ) connected between the supply connection ( 22 ) of the second amplifier ( 21 ) and the connection node ( 2 ) is switched. Circuit arrangement according to claim 6, wherein the first amplifier ( 11 ) as inverter and the second amplifier ( 21 ) are designed as inverters. Circuit arrangement according to Claim 6 or 7, at least one memory circuit ( 501 . 511 . 521 . 531 ) comprises: a first buffer ( 106 ), the output ( 15 ) of the first amplifier ( 11 ), and - a second buffer ( 104 ), the output ( 25 ) of the second amplifier ( 21 ) and on the output side of which the output signal (DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4) can be tapped off. Circuit arrangement according to one of claims 2 to 8, wherein at least one memory circuit ( 501 . 511 . 521 . 531 ) a logic circuit ( 509 ) with the data input ( 503 . 513 . 523 . 533 ), the clock input ( 504 . 514 . 524 . 534 ), the control input ( 507 . 517 . 527 . 537 ) and the second output ( 506 . 516 . 526 ) is coupled. Circuit arrangement according to one of Claims 1 to 9, the control circuit ( 400 ) comprises: - a flow control ( 440 ), - an oscillator ( 430 ), which is used to deliver an internal clock signal (ICLK) to the sequencer ( 440 ), and - a detection circuit ( 410 ), with the flow control ( 440 ) and for setting an operating mode of the circuit arrangement ( 700 ) is provided. Circuit arrangement according to Claim 10, comprising - a first input ( 701 ) connected to the detection circuit ( 410 ), - a second input ( 702 ), which is provided for supplying a clock signal (CLK) and with the sequence control ( 440 ), the memory circuits ( 501 . 511 . 521 . 531 ) and the detection circuit ( 410 ) coupled, and - a bidirectional connection ( 300 ), with the flow control ( 440 ), the detection circuit ( 410 ) and a switch ( 600 ) with the memory circuits ( 501 . 511 . 521 . 531 ) is coupled. Circuit arrangement according to Claim 11, comprising a connection ( 601 ) of the bidirectional connection ( 300 ) via a second switch ( 600 ) connected to a control terminal with the control circuit ( 400 ) to a terminal of the non-volatile memory cells ( 502 . 512 . 522 . 532 ) of the memory circuits ( 501 . 511 . 521 . 531 ). Circuit arrangement according to one of Claims 1 to 12, comprising a data bus ( 597 ), with the first outputs ( 505 . 515 . 525 . 535 ) of the memory circuits ( 501 . 511 . 521 . 531 ) for outputting the output signals (DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4) to the data bus ( 597 ) is coupled. Use of the circuit arrangement according to one of claims 1 to 13 for the permanent storage of data, in particular one Serial number, a semiconductor body number or a trim adjustment of an analog circuit on a semiconductor body, the the circuit comprises. Method for operating a circuit arrangement, comprising the following steps: - supplying a control signal (F1) and a first data signal (S1) to a first memory circuit ( 501 ) comprising a non-volatile memory cell ( 502 ), a first plurality n of serially connected memory circuits ( 501 . 511 . 521 . 531 ), - providing a second data signal (S2) as a function of the control signal (F1) and the first data signal (S1) on the output side of the first memory circuit ( 501 ), In each case supplying a data signal (S2, S3, S4) to a further memory circuit ( 511 . 521 . 531 ) and providing the respective data signal (S3, S4) to a downstream memory circuit ( 521 . 531 ) in response to the supplied control signal (F1) and the supplied data signal (S2, S3). Method according to claim 15, wherein a clock signal (SCLK) of at least the first of said memory circuits (SCLK) 501 . 511 . 521 . 531 ) and the second data signal (S2) is provided in response to the clock signal (SCLK). Method according to Claim 15 or 16, comprising providing a processing signal (REGLAST) by the penultimate or last memory circuit ( 521 . 531 ), after the control signal (F1) and the associated data signal (S3, S4) of the penultimate and the last memory circuit ( 521 . 531 ). Method according to one of claims 15 to 17, comprising serial readout of data of the memory circuits ( 501 . 511 . 521 . 531 ) by serially providing the first plurality n of output signals (DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4) at a serial data output ( 598 ). Method according to one of claims 15 to 18, comprising parallel reading out of data of the memory circuits ( 501 . 511 . 521 . 531 by providing the first plurality n of output signals (DATAOUT1, DATAOUT2, DATAOUT3, DATAOUT4) on an internal bus ( 597 ). Method according to one of claims 15 to 19, comprising providing - a connection between an external connection ( 300 ) and a terminal of one of the non-volatile memory cells ( 502 . 512 . 522 . 532 ) and - a connection between a reference potential terminal ( 8th ) and a further connection of the non-volatile memory cell ( 502 . 512 . 522 . 532 ) for an analog measurement of a resistance value of the non-volatile memory cell ( 502 . 512 . 522 . 532 ) or for programming the non-volatile memory cell ( 502 . 512 . 522 . 532 ) by means of a programming current. Method according to one of claims 15 to 20, comprising providing - a connection between a supply voltage connection ( 9 ) and a terminal of one of the non-volatile memory cells ( 502 . 512 . 522 . 532 ) and - a connection between a reference potential terminal ( 8th ) and a further connection of the non-volatile memory cell ( 502 . 512 . 522 . 532 ) for programming the non-volatile memory cell ( 502 . 512 . 522 . 532 ) by means of a programming current. Method according to one of claims 20 or 21, wherein a height of the programming current is set such that the non-volatile memory cell ( 502 . 512 . 522 . 532 ) is burned out.