DE102006040728A1 - Method and device for producing an electronic module - Google Patents
Method and device for producing an electronic module Download PDFInfo
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- DE102006040728A1 DE102006040728A1 DE102006040728A DE102006040728A DE102006040728A1 DE 102006040728 A1 DE102006040728 A1 DE 102006040728A1 DE 102006040728 A DE102006040728 A DE 102006040728A DE 102006040728 A DE102006040728 A DE 102006040728A DE 102006040728 A1 DE102006040728 A1 DE 102006040728A1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
- B23K26/00—Working by laser beam, e.g. welding, cutting or boring
- B23K26/08—Devices involving relative movement between laser beam and workpiece
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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Abstract
Die Erfindung betrifft ein Verfahren und eine Vorrichtung zum Übertragen eines Layouts einer leitenden Struktur auf eine Oberfläche (29) eines Substrats (11), auf dem zumindest ein Bauelement (16, 19) angeordnet ist, bei dem zur Übertragung des Layouts eine lichtempfindliche Schicht (40) aus Kunststoffmaterial, die auf die Oberfläche (29) aufgebracht ist, selektiv belichtet wird, wobei vor dem Schritt des Belichtens der lichtempfindlichen Schicht (40) für zumindest manche der auf dem Substrat (11) angeordneten Bauelemente (16, 19) zumindest ein Positionsparameter erfasst und bei der Übertragung des Layouts berücksichtigt wird.The invention relates to a method and an apparatus for transferring a layout of a conductive structure onto a surface (29) of a substrate (11) on which is arranged at least one component (16, 19) in which a photosensitive layer (12) is used to transfer the layout. 40) of plastic material applied to the surface (29) is selectively exposed, wherein prior to the step of exposing the photosensitive layer (40) for at least some of the substrates (16, 19) disposed on the substrate (16) Position parameter is captured and taken into account when transferring the layout.
Description
Die Erfindung betrifft ein Verfahren und eine Vorrichtung zum Übertragen eines Layouts einer leitenden Struktur auf eine Oberfläche eines Substrats, auf dem zumindest ein Bauelement, insbesondere ein Halbleiterchip, angeordnet ist.The The invention relates to a method and a device for transmitting a layout of a conductive structure on a surface of a Substrate on which at least one component, in particular a semiconductor chip, is arranged.
Ausgangspunkt
bei der Herstellung des elektronischen Moduls ist ein in
Alternativ
ist die Herstellung von elektrischen Verbindungen zwischen den Kontaktflächen
Die Belichtung erfolgt üblicherweise mittels einer Maske, mit der das Layout der leitenden Struktur auf die Fotofolie übertragen wird. Dabei werden diejenigen Abschnitte der Fotofolie durch die Maske abgeschattet, welche die spätere elektrisch leitende Struktur ausbilden sollen. Die nicht belichteten Abschnitte der Fotofolie lassen sich in einem weiteren Verfahrensschritt entfernen, so dass eine Freilegung der darunter befindlichen Sputterschicht, genauer der Kupferoberfläche der Sputterschicht, erfolgt. Durch Eintauchen des vorbereiteten Halbzeugs in ein Elektrolytbad, insbesondere ein Kupfer-Elektrolytbad, wird durch galvanische Verstärkung eine ca. 100 bis 200 μm dicke Kupferschicht aufgewachsen. In einem sich daran anschließenden Schritt, der als Strippen der Fotofolie bezeichnet wird, wird die noch auf der Oberfläche befindliche Fotofolie an den Bereichen, an welchen keine elektrisch leitende Struktur ausgebildet werden soll, entfernt. Als letzter Schritt erfolgt ein sog. Differenzätzen, bei dem ganzflächig die aus Titan und Kupfer bestehende Sputterschicht entfernt wird, so dass lediglich die gewünschte leitfähige Struktur überbleibt.The Exposure is usually done by means of a mask showing the layout of the conductive structure transfer the photo film becomes. In the process, those sections of the photographic film are replaced by the Mask shaded, which is the later electrically conductive structure should train. The unexposed sections of the photo film can be removed in a further process step, so that an exposure of the underlying sputtering layer, more precisely the copper surface the sputtering layer occurs. By dipping the prepared Semi-finished product in an electrolyte bath, in particular a copper electrolyte bath, is by galvanic reinforcement one about 100 to 200 microns grown thick copper layer. In a subsequent step, which is referred to as stripping the photofinish, which is still on the surface located photo film at the areas where no electrical conductive structure is to be formed away. As last one Step is a so-called. Differenzätzen, in the whole area of the Titanium and copper existing sputtering layer is removed, so that only the desired conductive Structure remains.
Die Herstellung der elektrischen Verbindungen unter Verwendung der beschriebenen planaren Verbindungstechnologie weist den Nachteil auf, dass bei komplexen Leiterstrukturen manche Kontaktflächen nicht oder nur ungenügend in elektrischem Kontakt zu einer erzeugten Leiterstruktur stehen. Das elektronische Modul ist damit Ausschuss, da eine nachträgliche Reparatur der elektrischen Verbindung nicht möglich ist. Aufgrund der bereits verarbeiteten elektronischen Bauelemente sind damit sehr hohe Kosten verbunden.The Preparation of electrical connections using the described planar interconnect technology has the disadvantage that at complex conductor structures some contact surfaces are not or only inadequate are in electrical contact with a generated conductor structure. The electronic Module is thus reject, because a subsequent repair of the electrical Connection not possible is. Due to the already processed electronic components are associated with very high costs.
Es ist daher Aufgabe der vorliegenden Erfindung, ein Verfahren und eine Vorrichtung zum Übertragen eines Layouts einer leiteten Struktur auf eine Oberfläche eines Substrats anzugeben, welches die Herstellung von elektronischen Modulen mit hoher Zuverlässigkeit bei einer geringen Fehlerquote ermöglicht.It is therefore an object of the present invention, a method and a device for transmitting a layout of a conductive structure on a surface of a Substrate, which is the production of electronic Modules with high reliability with a low error rate.
Diese Aufgaben werden mit den Merkmalen der unabhängigen Patentansprüche gelöst. Vorteilhafte Ausführungsformen ergeben sich aus den abhängigen Patentansprüchen.These Tasks are solved with the features of the independent claims. advantageous embodiments arise from the dependent ones Claims.
Bei dem erfindungsgemäßen Verfahren zum Übertragen eines Layouts einer leitenden Struktur auf eine Oberfläche eines Substrats, auf dem zumindest ein Bauelement angeordnet ist, wird zur Übertragung des Layouts eine lichtempfindliche Schicht aus Kunststoffmaterial, die auf die Oberfläche aufgebracht ist, selektiv belichtet. Dabei wird vor dem Schritt des Belichtens der lichtempfindlichen Schicht für zumindest manche der auf dem Substrat angeordneten Bauelemente zumindest ein Positionsparameter erfasst und bei der Übertragung des Layouts berücksichtigt.at the method according to the invention to transfer a layout of a conductive structure on a surface of a Substrate on which at least one component is arranged, is for transmission the layout of a photosensitive layer of plastic material, the on the surface applied, selectively exposed. This is before the step of exposing the photosensitive layer to at least some of the substrate arranged components at least one position parameter recorded and during transmission of the layout.
Eine erfindungsgemäße Vorrichtung zum Übertragen eines Layouts einer leitenden Struktur auf eine Oberfläche eines Substrats, auf dem zumindest ein Bauelement angeordnet ist, wobei zur Übertragung des Layouts eine lichtempfindliche Schicht aus Kunststoffmaterial, die auf die Oberfläche aufgebracht ist, selektiv zu belichten ist, umfasst eine optische Erfassungseinrichtung und eine Verarbeitungseinrichtung. Die optische Erfassungseinrichtung ist zur Erfassung zumindest eines Positionsparameters für zumindest manche der auf dem Substrat angeordneten Bauelemente ausgebildet. Die Verarbeitungseinrichtung dient zur Steuerung einer steuerbaren Belichtungseinheit, welcher der zumindest eine Positionsparameter zuführbar ist, wobei die Verarbeitungsrichtung dazu ausgebildet ist, den zumindest einen Positionsparameter bei der Steuerung der Belichtungseinheit zu berücksichtigten.A inventive device to transfer a layout of a conductive structure on a surface of a Substrate on which at least one component is arranged, wherein for transmission the layout of a photosensitive layer of plastic material, the on the surface is applied, is to be selectively exposed, comprises an optical detection device and a processing device. The optical detection device is for detecting at least one position parameter for at least some of the components arranged on the substrate are formed. The processing device serves to control a controllable exposure unit, to which at least one position parameter can be fed, wherein the processing direction is adapted to the at least a positional parameter in the control of the exposure unit to be considered.
Der Erfindung liegt die Erkenntnis zugrunde, dass beim Aufbringen der Bauelemente auf das Substrat eine nicht beeinflussbare Positionsänderung der Bauelemente parallel zur Oberfläche des Substrats erfolgt. Dies resultiert daraus, dass die Bauelemente üblicherweise unter Verwendung eines zunächst flüssigen Haftmittels, in der Regel ein Lot, auf die Oberfläche des Substrats aufgepresst werden. Beim Aufpressen des Bauelements auf das flüssige oder viskose Haftmittel kann es hierbei zu einem "Versatz" des Bauelements relativ zu seiner Sollposition kommen. Dieser Versatz kann bei herkömmlichen Fertigungsverfahren unter ungünstigen Umständen dazu führen, dass eine auf der Oberfläche des Substrats erzeugte Leiterstruktur nicht die zu verbindenden Kontaktflächen der auf das Substrat aufgebrachten Bauelemente trifft. Bei der Erfindung wird dieses Problem dadurch umgangen, dass vor dem Schritt des Belichtens der lichtempfindlichen Schicht die Position zumindest mancher, bevorzugt aller, der auf dem Substrat angeordneten Bauelemente, erfasst wird. Hierzu wird zumindest ein Positionsparameter erfasst, welcher eine Positionsänderung relativ zu der Sollposition wiedergibt. Dieser zumindest eine Positionsparameter wird dann bei der Übertragung des Layouts berücksichtigt. Das erfindungsgemäße Verfahren ermöglicht daher eine nahezu ausschussfreie Fertigung eines elektronischen Moduls. Hierdurch verringern sich die Stückkosten bei der Produktion.Of the Invention is based on the finding that when applying the Components on the substrate an uncontrollable position change the components are parallel to the surface of the substrate. This results from the fact that the components are usually using one at first liquid Adhesive, usually a solder, on the surface of the Substrate to be pressed. When pressing the device on the liquid or viscous adhesive, this may lead to a "misalignment" of the device come relative to its nominal position. This offset can be conventional Manufacturing process under unfavorable circumstances cause that one on the surface The conductor structure produced by the substrate does not have the contact surfaces to be connected impinges on the substrate applied components. In the invention this problem is circumvented by the fact that before the step of exposing the photosensitive layer, the position of at least some, preferably all of the components arranged on the substrate are detected. For this At least one position parameter is detected, which is a position change relative to the desired position. This at least one position parameter will then be in the transmission of the layout. The inventive method allows therefore an almost jam-free production of an electronic Module. This reduces the unit costs during production.
Der zumindest eine Positionsparameter wird gemäß einer Ausführungsvariante des erfindungsgemäßen Verfahrens einer Ver arbeitungseinrichtung zur Steuerung einer steuerbaren Belichtungseinheit, insbesondere einem Laser, als Korrekturdaten zugeführt, welche diesen zur Positionskorrektur von Steuerdaten, welche das zu erzielende Layout nachbilden, verwendet und eine Belichtung mit den korrigierten Steuerdaten bewirkt. Im Rahmen des erfindungsgemäßen Verfahrens erfolgt hiermit keine Belichtung unter Verwendung einer starren Maske, sondern mittels einer durch die Verarbeitungseinrichtung steuerbaren Belichtungseinheit. Dies ermöglicht es auf besonders einfache und kostengünstige Weise, eine Korrektur von Steuerdaten vorzunehmen, welche das zu erzielende Layout (entsprechend der Belichtung mit einer Maske) ermöglichen.Of the at least one position parameter is according to an embodiment variant the method according to the invention a Ver processing device for controlling a controllable exposure unit, in particular a laser, supplied as correction data, which this for position correction of control data which mimic the layout to be achieved and causing exposure to the corrected control data. in the Framework of the method according to the invention no exposure is made using a rigid Mask, but by means of a processing device controllable exposure unit. This makes it especially easy and cost-effective Way to make a correction of control data, which is the achieving layout (corresponding to the exposure with a mask) enable.
Als Positionsparameter wird zweckmäßigerweise für jedes Bauelement zumindest seine x- und y-Position auf dem Substrat erfasst. x und y bilden Achsen, die sich parallel zur Ebene des Substrats erstrecken und die vorzugsweise in einem Winkel von 90° zueinander stehen. Falls erforderlich, kann zusätzlich als Positionsparameter auch seine z-Position erfasst werden, um ggf. Abweichungen von einer vorgegebenen Soll-Höhe erfassen zu können. Die z-Achse erstreckt sich somit orthogonal zu der Ebene des Substrats und ermöglicht eine Fokusanpassung der Belichtungseinheit.When Position parameter is expediently for each Component detects at least its x and y position on the substrate. x and y form axes parallel to the plane of the substrate extend and preferably at an angle of 90 ° to each other stand. If necessary, can additionally as a position parameter Also, its z position can be captured to reflect any deviations from one predetermined target height to be able to capture. The z-axis thus extends orthogonal to the plane of the substrate and allows a focus adjustment of the exposure unit.
Zweckmäßigerweise werden die einem Bauelement zugeordneten Positionsparameter in einem Datensatz gespeichert, welcher dem Substrat mit dem zumindest einen Bauelement zugeordnet ist. Weiter bevorzugt wird jedem zu belichtenden Substrat ein Global-Datensatz mit den Datensätzen der Bauelemente, deren Position erfasst wurde, (bevorzugt sämtlicher Bauelemente) zugeordnet. Hierdurch wird eine besonders einfache Verarbeitung der Positionsparameter zur Positionskorrektur durch die Verarbeitungseinheit möglich.Conveniently, become the position parameter assigned to a component in a record stored, which the substrate with the at least one component assigned. Further preferred is each substrate to be exposed a global record containing the datasets of the components whose Position was detected, (preferably all components) assigned. This results in a particularly simple processing of the position parameters for position correction by the processing unit possible.
Es ist weiter vorgesehen, dass jedes Substrat mit einer, insbesondere optisch auslesbaren, Kennzeichnung versehen wird, deren Informationsgehalt dem Global-Datensatz zugefügt wird. Anhand der Kennzeichnung ist eine Identifizierung des betref fenden Substrats mit den darauf befindlichen Bauelementen auch nach einer Anzahl von Verfahrensschritten möglich, die zwischen dem Belichten und dem Erfassen der Positionsparameter liegen. Anhand dieser erfolgt dann die Zuordnung des korrekten Global-Datensatzes.It is further provided that each substrate with a, in particular optically readable, marking is provided, the information content added to the global record becomes. On the basis of the marking is an identification of the relevant Substrate with the components thereon even after a Number of process steps possible, between exposing and capturing the positional parameters lie. On the basis of this, then the assignment of the correct global data set takes place.
Die Ermittlung des zumindest einen Positionsparameters wird vor oder nach dem Aufbringen einer Isolierfolie auf die Oberfläche vorgenommen. Die Ermittlung des zumindest einen Positionsparameters, z.B. nach dem Aufbringen einer Isolierfolie auf die Oberfläche des Substrats und dem Einbringen von Öffnungen im Bereich von Kontaktflächen, weist jedoch den Vorteil auf, dass bereits die exakte Lage der Kontaktflächen, welche durch eine Öffnung der Isolierfolie erfolgt, möglich ist.The Determination of the at least one position parameter is before or made after applying an insulating film on the surface. The Determining the at least one position parameter, e.g. after this Applying an insulating film on the surface of the substrate and the introduction of openings in the area of contact surfaces, points However, the advantage that already the exact location of the contact surfaces, which through an opening of the Insulating foil is possible is.
Weiter bevorzugt ist es, wenn die Ermittlung des zumindest einen Positionsparameters ohne Zwischenschaltung weiterer Verarbeitungsschritte nach dem Aufbringen des zumindest einen Bauelements auf das Substrat vorgenommen wird. Die Ermittlung des zumindest einen Positionsparameters ohne Zwischenschaltung weiterer Verarbeitungsschritte nach dem Aufbringen auf das Substrat weist den Vorteil auf, dass eine genauestmögliche Abweichung der tatsächlichen Position von einer Sollposition der betreffenden Bauelemente ermittelbar ist.It is further preferred if the determination of the at least one position parameter is carried out without the interposition of further processing steps after the application of the at least one component to the substrate. The investigation the at least one position parameter without interposition of further processing steps after application to the substrate has the advantage that a most accurate deviation of the actual position from a desired position of the relevant components can be determined.
In einer weiteren zweckmäßigen Ausgestaltung ist vorgesehen, dass die Belichtung mit einer Belichtungseinheit vorgenommen wird, die gegenüber einer senkrechten Achse zu dem Substrat neigbar ist, um eine Belichtung von senkrecht verlaufenden Abschnitten der Bauelemente durchführen zu können. Bei einer Belichtung, die ausschließlich in einer senkrechten Achse zu dem Substrat vorgenommen wird (wie z.B. bei einer Maskenbelichtung) kann es vorkommen, dass senkrecht verlaufende Abschnitte der Bauelemente (z.B. deren Seitenflächen) nicht ausreichend belichtet werden, wodurch in den nachfolgenden Verarbeitungsschritten eine unpräzise elektrische Leiterstruktur die Folge sein kann. Eine Belichtungseinheit, welche gegenüber der senkrechten Achse zu dem Substrat neigbar ist, kann hingegen senkrecht verlaufende Abschnitte und eventuell sogar in einem spitzen Winkel relativ zu dem Substrat verlaufende Abschnitte belichten, so dass eine präzise Erzeugung der leitfähigen Struktur möglich ist.In a further advantageous embodiment is provided that the exposure with an exposure unit is made, the opposite a vertical axis to the substrate is tilted to an exposure to be able to perform from perpendicular sections of the components. at an exposure that exclusively is made in a vertical axis to the substrate (as e.g. in a mask exposure), it can happen that vertically extending portions of the components (e.g., their side surfaces) not be sufficiently exposed, which in the subsequent processing steps an imprecise electrical conductor structure may be the result. An exposure unit, which opposite the vertical axis can be tilted to the substrate, however, can vertical sections and possibly even in a point Expose angles relative to the substrate, so that's a precise one Generation of the conductive Structure possible is.
Alternativ oder zusätzlich können vor dem Schritt des Aufbringens der lichtempfindlichen Schicht an im Wesentlichen senkrecht zu dem Substrat verlaufenden Abschnitten des zumindest einen Bauelements Flanken erzeugt werden, welche die Seitenkanten des Bauelements mit dem Substart in einem stetigen Übergang verbinden. Hierdurch können relativ zu dem Substrat senkrecht verlaufende Abschnitte im Wesentlichen vermieden werden.alternative or additionally can before the step of applying the photosensitive layer substantially perpendicular to the substrate extending portions of the at least one component flanks are generated which the side edges of the device with the Substart in a steady transition connect. This allows substantially perpendicular to the substrate substantially extending portions be avoided.
Die lichtempfindliche Schicht, die in Form einer Folie (Fotofolie) oder eines Lacks ausgebildet sein kann, wird bevorzugt aus einem isolierenden Material gewählt. Die Oberfläche, auf welche die Schicht aufgebracht (im Falle einer Folie laminiert) wird, weist eine dreidimensionale Struktur auf.The photosensitive layer in the form of a film (photofinish) or a lacquer is formed, is preferably made of an insulating material selected. The surface, on which the layer is applied (in the case of a film laminated), has a three-dimensional structure.
Mit der erfindungsgemäßen Vorrichtung zum Übertragen eines Layouts einer leitenden Struktur auf eine Oberfläche eines Substrats sind die gleichen Vorteile verbunden, wie sie in Verbindung mit dem erfindungsgemäßen Verfahren erläutert wurden.With the device according to the invention to transfer a layout of a conductive structure on a surface of a Substrate are connected to the same benefits as they are related with the method according to the invention explained were.
In einer Ausführungsform der erfindungsgemäßen Vorrichtung ist die Verarbeitungseinheit dazu ausgebildet, den zumindest einen Positionsparameter zur Korrektur von Steuerdaten, welche das zu erzielende Layout nachbilden, heranzuziehen.In an embodiment the device according to the invention the processing unit is adapted to the at least one Position parameter for correction of control data, which is the emulate the resulting layout, use.
In einer weiteren zweckmäßigen Ausführungsform ist die Belichtungseinheit als Laser ausgebildet.In a further advantageous embodiment the exposure unit is designed as a laser.
In einer Ausführungsform kann vorgesehen sein, dass die Belichtungseinheit gegenüber einer senkrechten Achse zu dem Substrat oder das Substrat gegenüber der Belichtungseinheit steuerbar neigbar ist, um eine Belichtung von senkrecht verlaufenden Abschnitten der Bauelemente durchführen zu können.In an embodiment can be provided that the exposure unit with respect to a vertical Axis to the substrate or the substrate relative to the exposure unit controllable is tiltable to an exposure of vertical sections perform the components to be able to.
Die Erfindung weist den Vorteil auf, dass Bauelemente mit einer Höhe von 50 μm bis 10 mm nicht nur auf der Oberfläche, sondern auch an nahezu senkrechten Flanken strukturierbar sind.The Invention has the advantage that components with a height of 50 microns to 10 mm not just on the surface, but also structurable on almost vertical flanks.
Die Erfindung wird nachfolgend weiterhin anhand eines Ausführungsbeispiels in der Figur näher erläutert. Es zeigen:The Invention will continue below using an embodiment explained in more detail in the figure. It demonstrate:
Der
prinzipielle Aufbau eines elektronischen Moduls
Entgegen
der zeichnerischen Darstellung müssen
die Höhen
der Bauteile
Eine
auf die Oberfläche
Das
Aufbringen der Isolationsfolie erfolgt beispielsweise in einer Vakuumkammer.
Der genaue Prozess des Aufbringens der Isolationsfolie auf die Oberfläche
Eine
Abweichung der tatsächlichen
Position von der Soll-Position
wird bei der Belichtung der Fotofolie
Die
erfindungsgemäße Vorrichtung
zum Übertragen
des Layouts auf die Oberfläche
des Substrats
Die
Erfassung der optischen Position kann, wie dies vorstehend bereits
erläutert
wurde, unmittelbar nach dem Aufbringen der Bauelemente
Das
Aufbringen der optisch auslesbaren Markierung auf das Substrat
Zur
Belichtung der mit einer Fotofolie
Die
Belichtung der Fotofolie
Im
Ausführungsbeispiel
der
Claims (16)
Priority Applications (2)
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DE102006040728A DE102006040728A1 (en) | 2006-08-31 | 2006-08-31 | Method and device for producing an electronic module |
PCT/EP2007/059073 WO2008025832A1 (en) | 2006-08-31 | 2007-08-30 | Method and apparatus for manufacturing an electronic module |
Applications Claiming Priority (1)
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DE102006040728A DE102006040728A1 (en) | 2006-08-31 | 2006-08-31 | Method and device for producing an electronic module |
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DE102006040728A Withdrawn DE102006040728A1 (en) | 2006-08-31 | 2006-08-31 | Method and device for producing an electronic module |
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DE (1) | DE102006040728A1 (en) |
WO (1) | WO2008025832A1 (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0189781B1 (en) * | 1985-01-28 | 1989-05-03 | Siemens Aktiengesellschaft | Method for making a flat coil, and a flat coil for a shock wave tube |
US5648854A (en) * | 1995-04-19 | 1997-07-15 | Nikon Corporation | Alignment system with large area search for wafer edge and global marks |
DE10128476A1 (en) * | 2001-06-12 | 2003-01-02 | Siemens Dematic Ag | Optical sensor device for the visual detection of substrates |
US20030208740A1 (en) * | 2000-11-10 | 2003-11-06 | Tourne Joseph A.A.M. | System and method for monitoring and improving dimensional stability and registration accuracy of multi-layer PCB manufacture |
US20060050940A1 (en) * | 2002-12-20 | 2006-03-09 | Ichitaroh Satoh | System and method for detecting and correcting position deviations of an object having a curved surface |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5653019A (en) * | 1995-08-31 | 1997-08-05 | Regents Of The University Of California | Repairable chip bonding/interconnect process |
JP2003186173A (en) * | 2001-12-18 | 2003-07-03 | Fujitsu Ltd | Pattern forming method |
JP4190269B2 (en) * | 2002-07-09 | 2008-12-03 | 新光電気工業株式会社 | Device-embedded substrate manufacturing method and apparatus |
DE102004018475A1 (en) * | 2004-04-16 | 2005-11-10 | eupec Europäische Gesellschaft für Leistungshalbleiter mbH | A power semiconductor device |
-
2006
- 2006-08-31 DE DE102006040728A patent/DE102006040728A1/en not_active Withdrawn
-
2007
- 2007-08-30 WO PCT/EP2007/059073 patent/WO2008025832A1/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0189781B1 (en) * | 1985-01-28 | 1989-05-03 | Siemens Aktiengesellschaft | Method for making a flat coil, and a flat coil for a shock wave tube |
US5648854A (en) * | 1995-04-19 | 1997-07-15 | Nikon Corporation | Alignment system with large area search for wafer edge and global marks |
US20030208740A1 (en) * | 2000-11-10 | 2003-11-06 | Tourne Joseph A.A.M. | System and method for monitoring and improving dimensional stability and registration accuracy of multi-layer PCB manufacture |
DE10128476A1 (en) * | 2001-06-12 | 2003-01-02 | Siemens Dematic Ag | Optical sensor device for the visual detection of substrates |
US20060050940A1 (en) * | 2002-12-20 | 2006-03-09 | Ichitaroh Satoh | System and method for detecting and correcting position deviations of an object having a curved surface |
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