DE102006036295A1 - High voltage transistor integrated into CMOS logic structures for e.g. smart power technology, combines junction- and complementary metal oxide transistor structures - Google Patents

Abstract

The semiconducting substrate (1) includes a semiconducting zone (11) of first conductive type, with greater doping than the substrate, in a first lateral zone (111) of the substrate. A third semiconducting zone (3) of second, opposite conductive type, extends in the first zone (11) and is connected electrically to the source connection (S). This zone is spaced laterally from the substrate/first zone boundary. It borders the gate connection (G) laterally, but is insulated from it by a dielectric (9) layer. A fourth semiconducting zone (4) of the first type, extends inside the first zone (11) and is electrically connected to the source connection. Further fifth- (5), sixth- (6) and trenched- (20) zones of the structure are detailed.

Description

The The invention relates to a semiconductor component, in particular a high-voltage transistor, usually used CMOS logic structures can be integrated.

In various applications, such as Smart Power Technology (SPT) products, are logic structures that are commonly used in CMOS technology accomplished be, with high-voltage driver stages integrated. The problem here is the discrepancy between the external rated voltage the resulting device or the resulting circuit from 15 to 30 V and the operating voltage of the CMOS logic transistors of about 1.5 V.

Because of the high transconductance of the transfer characteristic LDMOS or DEMOS transistors are preferably used. at these transistors serve a so-called drain extension to the non-voltage-resistant gate oxide of the CMOS logic transistor at shielded transistor from the high drain voltage. For this purpose, a semiconductor region between the inner and outer drain connection provided over when the transistor is switched off, the largest part of the voltage at the outer drain connection drops so that at the inner drain port only the voltage tolerated by the CMOS transistor is applied. this will achieved by depletion of the semiconductor region. When switched on Transistor should, however, the current flow through the semiconductor region not or hardly be limited.

The optimization between the withstand voltage and on-resistance requirements R _on , combined with the requirements for scaling down the lateral dimensions of the devices, presents a challenge in integrating with existing CMOS logic technologies. Especially when using shallow Trench Isolation (STI) with implanted and retrograde doped wells instead of LOCOS technologies, the necessary increase of the drain voltage by a factor of 10 to 20 with respect to the CMOS base transistor is difficult to realize.

Known solutions for LOCOS technologies are transistors with a lateral doping gradient within the drain extension and / or the channel region (LDMOS) or RESURF transistors, in which by a Drain extension completely or partially overlapping thick dielectric (field oxide) and a field plate distributes the voltage drop more evenly in the drain extension becomes. At the "Double RESURF " Technology will be additional buried layers to optimize depletion and field strength distribution used.

at the use of retrograde doped logic wells as a drain extension becomes their vertical doping gradient as electrically effective Used element of the drain extension. However, this is not sufficient increase to reach the dielectric strength at the drain. For the integration of output stages for higher voltages to about 24V in pure CMOS logic processes No solutions are known.

Therefore It is an object of the invention to provide a high-voltage transistor, which can be integrated into a CMOS logic base process with STI and one opposite previously known solutions has significantly extended voltage range at the drain.

These Task is solved by a semiconductor device according to claim 1. Advantageous embodiments or Weitererbil applications of the inventive concept can be found in the subclaims.

The inventive semiconductor device comprises at least one MOS transistor with a source, a Gate and drain. It is in a semiconducting Substrate of a first conductivity type having a surface a first semiconductive region of the first conductivity type whose doping higher than that of the substrate is arranged. The first semiconducting area is formed in a first lateral region of the substrate.

One third semiconducting region of a second conductivity type, the is opposite to the first conductivity type, and a fourth semiconducting one Area of the first conductivity type extend within the first semiconducting region and are electrically connected to the source terminal conductively connected. The third semiconducting region is lateral to the interface spaced between the substrate and the first semiconductive region and laterally adjoins the gate terminal, passing it from the gate terminal through a dielectric Layer is isolated.

One fifth Semiconducting region of the second conductivity type is spaced from the interface disposed between the first semiconductive region and the substrate and is electrically connected to the drain terminal.

Between the third semiconductive region and the interface between the substrate and the first semiconducting region, a channel laterally extends within the first semiconducting region. That is, the channel is laterally located between the third and fifth semiconductive regions assigns. The channel is electrically connected to the gate terminal via the dielectric layer and can be controlled via a voltage applied to the gate terminal. It forms the channel region of the MOS transistor.

The Semiconductor device further comprises a sixth semiconducting region of the second conductivity type, which is laterally intermediate between the fifth Region and the channel is arranged. The sixth area is electric conducting with the fifth semiconducting Area and extends vertically to a sixth Depth d6. The sixth semiconductive area is from the gate terminal isolated by the dielectric layer.

Farther For example, the semiconductor device includes a buried semiconductive region of the second conductivity type whose upper edge is at a depth d21 of the surface is the substrate and the electrically conductive with the fifth semiconducting Area is connected, where d21 is greater than d6 and the buried territory at least partially below the sixth semiconducting Area is located.

In a particular embodiment becomes the sixth semiconductive area when voltage is applied at the gate terminal, which is smaller than the threshold voltage of the MOS transistor is passing through the channel area and the third and sixth semiconducting Area is formed, impoverished. That is, within the sixth Semiconducting region forms, starting from the pn junction between the sixth semiconductive region and the substrate, a barrier layer out.

The inventive semiconductor device provides a high-voltage CMOS transistor in which is located between the drain terminal of the semiconductor device and the inner drain terminal of the CMOS transistor has a drain extension, the sixth semiconducting area. Drain connection, drain extension and in nerer drain terminal of the CMOS transistor form a JFET, which is controlled by the substrate as a gate.

The Drain extension is the CMOS transistor turned off by the Substrate until impoverished that over the drain extension a voltage drops. This means, the doping strength and width of the forming barrier layer must be suitable, a desired Voltage drop between the fifth Semiconducting area and the inner drain connection. The falling voltage must be so great that the at the inner drain connection of the CMOS transistor applied field strength smaller than the breakdown field strength of the dielectric Layer is below the gate of the CMOS transistor. The below the drain extension lying and spaced from her buried Semiconducting region of the second conductivity type, in the following field plate called, which lies at the potential of the drain terminal, but does not contribute to the flow of electricity, improves the distribution the field strength lines within the drain extension. This allows field strength peaks within the drain extension avoided and thus the dielectric strength of the JFET and the whole Semiconductor device can be increased by a factor of 10 to 20. In contrast, is with an ordinary one Drain extension only one increase the dielectric strength reach the CMOS base transistor by a factor of 3 to 4.

When the CMOS transistor is switched on, the JFET acts as a current source at high drain voltages (saturation range of the characteristic curve), the current flowing only through the drain extension. Since due to the improved distribution of the field strength lines in the drain extension higher doping concentrations for the drain extension can be realized without reducing the dielectric strength, the drain extension has a lower R _on resistance.

In a particular embodiment are adjacent CMOS transistors Isolated from each other by a shallow trench isolation (STI). A shallow trench isolation is one in the surface of the substrate introduced trench, at least partially with insulating material filled is. In this embodiment the field plate is of particular importance, as a positive Influencing the field strength distribution in the drain extension by the action of the thick field oxide of LOCOS technology, as used in RESURF transistors, is eliminated or eliminated is limited to very small areas.

In another particular embodiment contacts the sixth semiconducting area, ie the drain extension, the surface of the substrate below the gate terminal and extends to the interface between the substrate and the first semiconductive region. In order to the inner drain terminal of the CMOS transistor is inside of the sixth semiconducting area, only from its bottom is depleted from the substrate.

In another particular embodiment, an isolation trench is located within the sixth semiconductive region. The drift path (ie the depleted region) within the drain extension is extended by a vertical part due to the slightly retrograde doping of the sixth semiconducting region with the same lateral space requirement. In other words, the lateral space requirement can be equal to one at the same drift distance Semiconductor device can be reduced without such an isolation trench. Furthermore, can be avoided by overlapping the gate terminal on the isolation trench field strength peaks within the drain extension. Thus, the theoretically shortest possible drift length can be almost utilized in a real component, and the wei tere structural reduction of the semiconductor devices with constant dielectric strength is possible. Furthermore, the cross-section of the sixth semiconducting region below the isolation trench is reduced, so that the doping of the sixth semiconducting region in this region can be further increased without jeopardizing the complete depletion of the region.

In another embodiment the semiconductor device according to the invention is the sixth semiconducting area, the drain extension, realized as a buried area. This means that the upper edge of the sixth semiconducting area is located measured at a seventh depth d60 from the surface of the Substrate. The sixth semiconducting area does not border on this the surface of the substrate. Furthermore contacted the sixth semiconducting area not the first semiconducting area.

Between the upper edge of the sixth semiconducting area and the surface of the Substrates, a seventh semiconducting region extends from the first Conduction type, which is electrically connected to the substrate. The seventh semiconductive region may be part of the substrate (a specially prepared and adjusted substrate) or an introduced be doped area.

One Eighth semiconducting region of the second conductivity type is located within the seventh semiconducting area. It is from the fifth semiconducting area spaced and with the sixth semiconducting area at some Make electrically conductive connected. The eighth semiconducting area extends laterally to the channel and contacts below the Gate terminal the surface of the substrate. The eighth semiconductive area is from the gate terminal isolated by the dielectric layer and forms the inner Drain terminal of the CMOS transistor.

In order to arises in the third lateral area, the area of the drift path between drain and inner drain a structure of two buried Regions of the second conductivity type, both with the second semiconductive region electrically connected, but from the first semiconducting area are spaced. Between the buried area and the sixth semiconducting Territory and between the sixth semiconducting area and the surface of the substrate is in each case an area of the first conductivity type, which is electrically connected to the substrate.

at turned off CMOS transistor becomes the sixth semiconductive region depleted from the top and bottom by the substrate. This falls above the sixth semiconducting region a voltage that is so great that the at the inner drain terminal of the CMOS transistor, that is in eighth semiconducting area, applied field strength smaller than the breakdown field strength of dielectric layer is. The buried area below the sixth semiconducting area influenced in the above described Way the field strength distribution within the sixth semiconducting area. This creates a vertical superjunction structure, in which several opposite doped semiconducting regions are arranged one below the other, whereby increases the doping of the individual areas and reduces their thickness can be. This can be good Breakthrough properties for the off CMOS transistor and low resistance values for the turned-on CMOS transistor can be realized.

at When the CMOS transistor is switched on, a current flows from the drain connection via the CMOS transistor sixth semiconducting area to the eighth semiconducting area. The Field plate bears not at the current flow.

The Invention will be described below with reference to the figures exemplary embodiment explained in more detail. It demonstrate:

1 A first embodiment of the semiconductor device according to the invention in cross-sectional view,

2 A second embodiment of the semiconductor device according to the invention in cross-sectional view,

3 a plan view of the region of the semiconductor device in 2 between the lines A and B in a particular embodiment,

4 A third embodiment of the semiconductor device according to the invention in a cross-sectional view.

In the figures are identical or corresponding areas, Components / component groups are identified by the same reference numerals. Furthermore you can all embodiments be inversely doped, that is n-areas become through p-areas replaced and vice versa.

In the 1 to 4 For example, all regions of the first conductivity type are p-type regions while regions of the second conductivity type are n-type regions.

1 shows a first embodiment of the semiconductor device according to the invention with a source terminal S, a gate terminal G and a drain terminal D, which is a CMOS transistor 13 includes. The source, gate and drain terminals are made of an electrically conductive material, such as polysilicon or a silicide. In a lightly doped p-substrate 1 are in a first lateral area 111 a first region doped higher than the substrate 11 and in a second lateral area 112 a second area 2 brought in. The area 11 is a p-logic pan while the area 2 is an n-logic pan. The area 11 extends from the surface 10 of the substrate 1 to a depth d1 while the area 2 from the surface 10 extends to a depth d2. The depths d1 and d2 and the dopants Ndot11 and Ndot2 are predetermined by the underlying CMOS basic technology. The training of the area 2 can also be saved, but the electrically conductive connection between the fifth semiconducting region 5 and the buried territory 20 and the sixth semiconducting area 6 be guaranteed, which are described below.

• – für das Substrat 1: Ndot1 = 5·10¹⁹ ... 5·10¹⁶ cm^–3
• – für das Gebiet 11 bzw. 2: d1/d2 = 1 ... 1,8 μm, Ndot11/Ndot2 = 5·10¹⁷... 5·10¹⁸ cm^–3.

Typical dopants and depths are:

• - for the substrate 1 : Ndot1 = 5 × 10 ¹⁹ ... 5 × 10 ¹⁶ cm ^-3
• - for the area 11 respectively. 2 : d1 / d2 = 1 ... 1.8 μm, Ndot11 / Ndot2 = 5 × 10 ¹⁷ ... 5 × 10 ¹⁸ cm ^-3 .

The areas 11 and 2 are in a lateral area 113 from each other through the substrate 1 spaced. In this lateral area 13 there is a buried, weakly doped n-region 20 that with the area 2 is electrically connected. As in 1 represented, the area can 20 in the area 2 protrude. The area 20 can also be lateral over the area 2 hinauserstrecken; in other words, it may be on the other side of the field 2 in the substrate 1 protrude (not shown). The top edge 21 of the area 20 is located at a depth d21 measured from the surface 10 , The area 20 is from the interface of the area 11 spaced from the substrate, but may also be adjacent to or below the area 11 extend. The lateral extent of the area 20 becomes dependent on the doping of the areas 11 and 2 selected.

In the area of 11 are two highly endowed areas 3 and 4 formed, both of which are electrically connected to the source terminal S. The n + area 3 forms the source region of the semiconductor device and extends vertically to a depth d3 from the surface 10 , The area 3 is lateral to the interface between substrate 1 and area 11 through the area 12 is adjacent and adjacent to the gate terminal G, the area 3 through a dielectric layer 9 isolated from the gate terminal. The area 12 is part of the area 11 and forms the channel region of the CMOS transistor 13 of the semiconductor device. The p + region 4 forms the substrate contact of the semiconductor device and extends to a depth d4 from the surface 10 , The depths d3 and d4 as well as the lateral dimensions of the areas 3 and 4 and the dopants Ndot3 and Ndot4 are given by the underlying CMOS base technology, where d3 and d4 are smaller than d1.

The dielectric layer 9 serves as a gate oxide for the semiconductor device. It may, for example, comprise thermal silicon oxide or another dielectric material or a layer stack. The thickness and the material of the dielectric layer 9 is predetermined by the underlying CMOS base technology.

A highly doped n + area 5 is at least partially within the area 2 and is electrically connected to the drain contact D of the semiconductor device. The area 5 thus forms the outer drain region of the semiconductor device.

The areas 2 and 20 are at the same potential as the area 5 because they are electrically connected to each other. The area 5 can become lateral completely within the area 2 However, it can also, as in 1 represented over the lateral area 112 out into the lateral area 113 protrude. It can also be over the whole area 2 extend beyond; in other words, it may be on the other side of the field 2 in the substrate 1 protrude. The area 5 extends to a depth d5 from the surface 10 , The depth d5 and the lateral dimensions of the area 5 are predefined by the underlying CMOS base technology, where d5 is smaller than d2.

In the lateral area 113 extends a weakly doped n-region 6 between the area 2 and the area 12 or the interface between the substrate 1 and the area 11 , It borders the area 6 in part to the gate terminal G, where it from the gate terminal G through the dielectric layer 9 is isolated. The to the gate terminal G and the area 12 adjacent part of the area 6 forms the inner drain of the semiconductor device and the drain of the CMOS transistor 13 , The area 6 forms the drift path or drain extension of the semiconductor device.

The area 6 can be easily doped retrograde, that is, the doping intensity increases with depth within the area 6 increases. The area 6 can be higher than the area 2 be endowed and also up within the area 2 extend. In particular, it is also possible that the Ge Biet 6 lateral to across the area 2 extends, that is, it is laterally continuous from one side of the area 2 to the other side of the area 2 each extending into the substrate 1 inside.

The area 6 extends vertically to a depth d6, where d6 is less than d21. This is an area 14 between the lower edge of the area 6 and the top of the buried territory 20 , The area 14 is of the substrate conduction type and with the substrate 1 electrically connected. He can be part of the substrate 1 can be, but can also be specially doped.

• – für das Gebiet 3, 4 bzw. 5: d3/d4/d5 = 0,1 ... 0,5 μm, Ndot3/Ndot4/Ndot5 = 5·10¹⁹ ... 5·10²¹ cm^–3,
• – für das vergrabene Gebiet 20: d21 = 1 ... 1,8 μm, Ndot11/Ndot2 < Ndot20 < Ndot3/Ndot4/Ndot5.
• – für das Gebiet 6: d6 = 0,5 ... 1 μm, Ndot11/Ndot2 < Ndot6 < Ndot3/Ndot4/Ndot5.

Typical dopants and depths are:

• - for the area 3 . 4 respectively. 5 : d3 / d4 / d5 = 0.1 ... 0.5 μm, Ndot3 / Ndot4 / Ndot5 = 5 × 10 ¹⁹ ... 5 × 10 ²¹ cm ^-3 ,
• - for the buried territory 20 : d21 = 1 ... 1.8 μm, Ndot11 / Ndot2 <Ndot20 <Ndot3 / Ndot4 / Ndot5.
• - for the area 6 : d6 = 0.5 ... 1 μm, Ndot11 / Ndot2 <Ndot6 <Ndot3 / Ndot4 / Ndot5.

Adjacent semiconductor devices or adjacent CMOS transistors, for example within the area 11 , are electrically isolated from each other. The insulation can be realized by a commonly used shallow trench isolation (STI), which differs from the surface 10 out into the area 11 extends. The depth of isolation is greater than d3 and d4. The insulation is located laterally on the area 12 opposite side of the area 3 , She can between the area 3 and the area 4 be arranged, the areas 3 and 4 both are electrically connected to the source contact S. But the isolation can also be next to the adjacent areas 3 and 4 be arranged. This will be the n + source area 3 from other n + areas within the p-logic well 11 isolated.

In the in 1 illustrated embodiment is within the area 6 an isolation ditch 91 brought in. The isolation trench 91 can be designed like an ordinary shallow trench Isola tion. It extends to a depth d91 from the surface 10 from, where d91 is smaller than d6. In a plane perpendicular to the image plane of the 1 through the isolation trench 91 runs, the isolation trench extends 91 over the area 6 out. In other words, in such a plane touches the area 6 the surface 10 Not.

The isolation in the tub 11 in particular, a frame around the entire semiconductor device or to the CMOS transistor 13 form. In the latter case, the insulation in the tub 11 at the edge termination of the device in the isolation trench 91 pass.

The dielectric layer 9 extends below the gate G to the isolation trench 91 approach, while the gate connection up to above the isolation trench 91 extends. This causes field strength peaks at the vertices of the isolation trench 91 (For example, at the border of the isolation trench 6 to the dielectric layer 9 and at the corner of the isolation trench in the area 6 ), which is advantageous for the dielectric strength of the device. The length L of the isolation trench 91 overlapping part of the gate terminal G is thus a geometric parameter of the component, which has effects on the electrical properties of the component.

Between the isolation ditch 91 and the drain terminal D may be a thick dielectric layer 15 on the surface 10 be arranged as in 1 shown. The gate terminal G may also be the layer 15 overlap in part, with a sufficient electrical isolation to the drain terminal D must be guaranteed. Also with it can the field strength distribution in the range 6 positively influenced.

Also between the gate terminal G and the source terminal S and on the areas of the surface 10 of the substrate located to the left of the source terminal S and to the right of the drain terminal D may be a dielectric layer, for example, the dielectric layer 9 or the dielectric layer 15 be arranged as in 1 shown.

Furthermore, the area can 5 on its entire depth to the isolation trench 91 adjoin, as in 1 shown. This is with respect to the distribution of field strength lines at the interface of the area 5 to the area 2 or area 6 advantageous. Furthermore, the area can be 2 lateral to below the isolation trench 91 extend. In other words: the isolation trench 91 can become lateral to the area 2 extend. This is particularly advantageous for components in which an electrostatic static discharge (ESD) case may occur.

Mirror-symmetric can further components in the areas 11 and 2 be formed (not shown). That is: left to the areas 3 and 4 may, separated by an isolation described above, other areas 3 and 4 another semiconductor device while, for example, the area 5 also as an area 5 for another semiconductor device located to the right of the illustrated device (not shown). Furthermore, it is possible that the mirror-symmetrical continuation of the illustrated structure, the semiconductor device is increased in order to achieve predetermined electrical parameters.

The following is the operation of the Semiconductor device and the importance of the semiconducting regions are explained in more detail.

The semiconductor device according to the invention can be considered as an interconnection of a CMOS transistor 13 and a JFET. The CMOS transistor 13 is made of the area 3 , which forms the source region of the MOS transistor, from the region 12 , which forms the channel region of the MOS transistor below the gate terminal G, the gate terminal G, via the dielectric layer 9 with the area 12 electrically connected, and that to the area 12 adjacent part of the area 6 which forms the drain terminal of the MOS transistor and the inner drain terminal of the semiconductor device.

The JFET is made up of area 5 , which forms the drain terminal of the JFET, from the area 6 acting as the channel region of the JFET from the substrate region 14 , which acts as the gate of the JFET, and from the area 12 adjacent part of the area 6 which acts as the source region of the JFET.

With the MOS transistor switched off 13 no electricity flows over the channel 12 , If the voltage between the inner drain and the substrate is greater than the threshold voltage of the JFET, then the pn junction to the channel is reverse biased and a barrier layer expands into the channel. That is, the area 6 is from the area 14 out of poverty. This forms due to the depletion and the inhomogeneous charge carrier distribution within the area 6 an inner field opposite to the outer field and a voltage drop across the area 6 leads. Thus, even at high voltages at the outer drain terminal D, a field strength at the inner drain terminal can be achieved, which is below the breakdown field strength of the dielectric layer 9 that is, the gate oxide of the MOS transistor 13 , lies.

The one in the area 6 introduced isolation trench 91 has several effects. First, it extends the drift path within the area 6 between the area 5 and the area 12 by dividing the drift distance from a lateral into a mixed drift path containing both lateral and vertical proportions (due to the retrograde doping of the area 6 ), is converted. Since the gate terminal G overlaps the isolation trench, field strength spikes within the area can occur 6 For example, be reduced at corners of the isolation trench and at the interface with the dielectric layer. Furthermore, the doping of the area 6 through the smaller cross section of the area 6 be increased without endangering the necessary impoverishment. These effects lead to a possible reduction in the lateral dimension of the area 6 and thus to a possible further reduction of the lateral space requirement of the semiconductor component. Furthermore, an increase in the doping of the area 6 to a desired reduction in resistance R _on .

The buried territory 20 located below the area 6 extends and is at the same potential as the outer drain terminal acts as a field plate with respect to the area 6 , That is, it affects the distribution of field lines within the area 6 such that no field strength peaks, resulting in a breakdown of the gate oxide of the MOS transistor 13 or the barrier layer could occur. Unlike conventional field plates, the area becomes 6 partially depleted depending on the applied external voltages. As a result, the field plate effect is voltage-dependent and dependent on the doping of the area 6 and adjacent layers in a desired manner.

When the MOS transistor is switched on 13 the voltage between the inner drain and the substrate drops below the threshold voltage of the JFET. This will be the area 6 conductive, with the possible higher doping of the area 6 positively affects.

Both in the switched on and in the off state of the MOS transistor 13 there is no net flow over the area 20 but exclusively over the area 6 ,

The buried territory 20 is also useful as a triel well isolation for other devices, for example for high-side applications where all terminals S, G and D have a different potential than that of the substrate. This is necessary, for example, for a semiconductor component according to the invention having inversely doped semiconducting regions, that is to say for a pMOS.

2 shows a second embodiment of the semiconductor device according to the invention. The basic structure of the semiconductor device with respect to the substrate, the areas 11 . 2 . 20 . 3 and 4 and the insulation between adjacent components, the S, G and D terminals, and the dielectric layer 9 corresponds to the first embodiment.

In contrast to the first embodiment, the highly doped n + region is located 5 exclusively within the area 2 , Furthermore, the low-doped n-type region 6 , the drain extension or drift path of the semiconductor device, designed as a buried region. That is, the top edge 60 of the area 6 is located at a depth d60 from the surface 10 of the substrate. The area 6 is from the interface between the substrate and that area 11 spaced and electrically conductive with the area 5 over the area 2 connected.

Between the surface 10 and the top edge 60 of the area 6 there is a doped p-region 7 which is electrically connected to the substrate. In particular, the area can 7 a specially introduced doped region or part of a specially prepared substrate.

The inner drain terminal of the semiconductor device is in the in 2 illustrated embodiment by a highly doped n + region 8th realized within the territory 7 located. It extends laterally to below the gate terminal G, from which it passes through the dielectric layer 9 is isolated. The area 8th is from the area 2 spaced and extends vertically to a depth d8 from the surface 10 , Here, d8 is smaller than d60, so that, in the in 2 section shown between the area 8th and the top edge 60 of the area 6 a part of the area 7 located. In another section plane is the area 8th electrically conductive to the area 6 connected.

The depth d60 as well as the lateral dimensions of the area 6 and its doping are adaptable to the parameters of the semiconductor device and / or the manufacturing conditions and freely selectable, while the doping, the depth d8 and the lateral dimensions of the area 8th are predetermined by the CMOS basic technology.

• – für das Gebiet 8: d8 = 0,1 ... 0,5 μm, Ndot8 = 5·10¹⁹ ... 5^.10²¹ cm^–3,
• – für das vergrabene Gebiet 6: d60 = 0,5 ... 1,2 μm, Ndot11/Ndot2 < Ndot6 < Ndot8/Ndot5.

Typical dopants and depths are:

• - for the area 8th : d8 = 0.1 ... 0.5 μm, Ndot8 = 5 × 10 ¹⁹ ... 5 ^. 10 ²¹ cm ^-3 ,
• - for the buried territory 6 : d60 = 0.5 ... 1.2 μm, Ndot11 / Ndot2 <Ndot6 <Ndot8 / Ndot5.

The surface 10 of the semiconductor device may be between the gate terminal G and the drain terminal D through the dielectric layer 9 or another dielectric layer passivated. In a metal layer arranged above a correspondingly thick dielectric, there may be a metallic layer (field plate) which is electrically conductively connected to the gate terminal G and, similar to the overlapping gate terminal G in FIG 1 , the field strength distribution in the areas 7 and 6 positively influenced.

Below the area 6 is an n-area 20 arranged, which is electrically conductive to the area 2 respectively. 5 connected is. It is from the area 6 through a p-region 14 spaced, the electrically conductive with the substrate 1 connected is. The area 14 can be part of the substrate 1 But it can also be a specially endowed area.

To avoid breakthroughs of the device on the surface 10 , lateral superjunctions between the areas 2 and 8th to be ordered. For example, interdigitated comb structures from highly doped n and p regions (eg, regions 8th and 7 ) are formed in a direction perpendicular to the illustrated sectional plane as in 3 shown.

3 is a plan view of the semiconductor device according to the invention the 2 between the lines A and B. For a better representation of the lateral superjunctions was the on the surface 10 the dielectric member disposed dielectric layer 9 not shown. Furthermore, they are also below the areas 8th . 7 and 2 located areas ( 6 . 14 . 20 and 1 ) not shown. As in 3 shown is the area 8th formed laterally in the form of a comb structure, wherein the areas 8th' from the area 2 are spaced. Between the individual areas 8th' are each areas of the area 7 , The resulting structure of several pn junctions reduces the risk of electrical breakdown of the semiconductor device on the surface 10 ,

In the following, the operation of the individual regions in the second embodiment, as in 2 illustrated, are explained. When the MOS transistor is switched off 13 passing through the territories 3 . 8th . 12 and the gate terminal G and the dielectric layer 9 is formed, the area becomes 6 from the area 14 and area 7 out of poverty. This falls over the area 6 from a voltage, so that at the inner drain connection, the area 8th , only a voltage that is below the breakdown voltage of the dielectric layer 9 lies. That under the area 6 arranged area 20 acts again as a field plate and leads to an improvement in the field strength distribution within the area 6 so the area 6 is depleted more uniformly and the dielectric strength is increased. This is a higher doping of the area 6 possible, which occurs when the MOS transistor is turned on 13 positive for the resistance of the area 6 effect.

When the transistor is switched on 13 flows over the area 6 a stream from the area 5 to the area 8th , The area 20 is not involved in the flow of electricity.

Furthermore, it is, as in 4 shown possible by introducing more buried areas 20 ' below the area 6 , by appropriately doped areas 14 ' of the other type of line are spaced apart to form a vertical superjunction. Thus, the doping strength (dopant concentration) of the area 6 be further increased. Here are the areas 20 ' electrically conductive with the fifth semiconducting region 5 connected. In the in 4 illustrated Ausfüh This is achieved by the second semiconducting area 2 realized. The areas 14 ' are electrically conductive to the substrate 1 connected. In 4 are only one area each 20 ' and an area 14 ' shown, but it can also be several areas 20 ' and 14 ' be arranged alternately with each other.

The arrangement of other areas 20 ' and 14 ' below the buried territory 20 is also for the in 2 illustrated embodiment of the semiconductor device according to the invention possible.

The Production of the semiconductor device according to the invention can with known processes, such as implantation, layer deposition, Lithography and etching, respectively. In particular, an integration of the production of the Semiconductor device in known CMOS basic technologies possible.

Semiconductor component

1

substratum (1st conductivity type)

10

Surface of the substrate

11

first Semiconducting region (1st conductivity type)

12

Area of the first semiconducting area

13

MOS transistor

14

Area of the substrate

14 '

buried Semiconducting region of the 1st conductivity type

15

dielectric layer

111

first lateral area

112

second lateral area

113

third lateral area

2

second Semiconducting region (2nd conductivity type)

20

buried Semiconducting region (2nd conductivity type)

20 '

additional buried semiconducting area of the 2nd Lei

processing type

21

top edge of the buried semiconducting area

3

third Semiconducting region (2nd conductivity type)

4

fourth Semiconducting region (1st conductivity type)

5

fifth semiconducting Area (2nd line type)

6

sixth Semiconducting region (2nd conductivity type)

60

top edge of the sixth semiconducting area

7

seventh Semiconducting region (1st conductivity type)

8th

eighth Semiconducting region (2nd conductivity type)

9

dielectric Layer (gate dielectric)

91

Shallow Trench isolation

92

Isolationssgraben

D

Drain

G

Gate terminal

S

Source terminal

L

Length of the overlapping part of the gate terminal

Claims (13)

Semiconductor device comprising a MOS transistor having a source (S), a drain (D) and a gate (G), comprising: - a semiconducting substrate ( 1 ) of a first conductivity type with a surface ( 10 ), - a first semiconducting area ( 11 ) of the first conductivity type whose doping is higher than that of the substrate ( 1 ), the first semiconducting area ( 11 ) in a first lateral area ( 111 ) of the substrate, - a third semiconducting region ( 3 ) of a second conductivity type, the second conductivity type being opposite to the first conductivity type, the third semiconductive region ( 3 ) within the first semiconducting area ( 11 ) and is electrically conductively connected to the source terminal (S), the third semiconducting area ( 3 ) laterally of the interface between substrate ( 1 ) and the first semiconducting area ( 11 ) and laterally adjacent to the gate terminal (G), passing through a dielectric layer (G) from the gate terminal (G). 9 ), - a fourth semiconducting area ( 4 ) of the first conductivity type located within the first semiconducting region ( 11 ) and is electrically connected to the source terminal (S), - a fifth semiconducting area ( 5 ) of the second conductivity type spaced from the interface between the first semiconducting region ( 11 ) and the substrate ( 1 ) is arranged and which is electrically conductively connected to the drain terminal (D), - a channel ( 12 ) within the first semiconducting area ( 11 ) extending laterally between the third semiconducting region ( 3 ) and the interface between the substrate ( 1 ) and the first semiconducting area ( 11 ) and electrically through the dielectric layer ( 9 ) is isolated from the gate terminal (G) and can be controlled via a voltage applied to the gate terminal (G), the channel ( 12 ) laterally between the third and fifth semiconducting regions ( 3 . 5 ), - a sixth semiconducting area ( 6 ) of the second conductivity type, laterally between the fifth semiconducting region ( 5 ) and the channel ( 12 ) is electrically conductively connected to the fifth semiconducting region ( 5 ) and extends vertically to a sixth depth d6, the sixth semiconductive region ( 6 ) from the gate terminal (G) through the dielectric layer ( 9 ), and - a buried semiconducting area ( 20 ) of the second conductivity type whose upper edge ( 21 ) at a depth d21 from the surface ( 10 ) of the substrate and the electrically conductive with the fifth semiconducting region ( 5 ), where d21 is greater than d6 and the buried area ( 20 ) at least partially below the sixth semiconducting area ( 6 ) is located. Semiconductor component according to Claim 1, characterized in that the sixth semiconductive region ( 6 ) when a voltage at the gate terminal (G), which is smaller than the threshold voltage of the MOS transistor ( 13 ) passing through the canal ( 12 ) and the third and sixth semiconducting areas ( 3 . 6 ) as well as the dielectric layer ( 9 ) and the gate terminal (G) is formed is depleted. Semiconductor component according to Claim 1, characterized in that adjacent MOS transistors ( 13 ) through one in the surface ( 10 ) of the substrate introduced trench, which is at least partially filled with insulating material, are isolated from each other. Semiconductor component according to Claim 1, characterized in that the fifth semiconductive region ( 5 ) and the buried semiconducting area ( 20 ) through a second semiconducting area ( 2 ) of the second conductivity type are electrically connected to each other. Semiconductor component according to Claim 1, characterized in that the sixth semiconductive region ( 6 ) below the gate terminal (G) the surface ( 10 ) of the substrate and extends to the interface between the substrate ( 1 ) and the first semiconducting area ( 11 ). Semiconductor component according to Claim 5, characterized in that in the sixth semiconducting region ( 6 ) from the surface ( 10 ) of the substrate ( 1 ) from an isolation trench ( 91 ) is introduced. Semiconductor component according to claim 6, characterized in that the gate connection (G) extends above the isolation trench (FIG. 91 ). Semiconductor component according to claim 6, characterized in that between the isolation trench ( 91 ) and the drain terminal (D) a thick dielectric layer ( 15 ) on the surface ( 10 ) of the substrate ( 1 ) and the gate terminal (G) except for the thick dielectric layer (FIG. 15 ), wherein the gate terminal (G) is spaced from the drain terminal (D). Semiconductor component according to Claim 6, characterized in that the fifth semiconducting region ( 5 ) to a depth d5 from the surface ( 10 ) of the substrate extends and over the entire depth d5 to the isolation trench ( 91 ) adjoins. Semiconductor component according to Claims 3 and 9, characterized in that the second semiconducting region ( 2 ) laterally to below the isolation trench ( 91 ). Semiconductor component according to Claim 6, characterized in that the sixth semiconductive region ( 6 ) is doped retrograde. Semiconductor component according to claim 1, characterized in that - the sixth semiconducting region ( 6 ) is formed as a buried layer, wherein the sixth semiconducting region ( 6 ) the first semiconducting area ( 11 ), - between the sixth semiconducting area ( 6 ) and the surface ( 10 ) of the substrate a seventh semiconducting region ( 7 ) of the first conductivity type, which is electrically conductive with the substrate ( 1 ), and - an eighth semiconducting area ( 8th ) of the second conductivity type within the seventh semiconducting region ( 7 ) of the fifth semiconducting area ( 5 ) and does not directly contact, but is electrically conductive with the sixth semiconducting region ( 6 ), the eighth semiconducting area ( 8th ) below the gate terminal (G) the surface ( 10 ) of the substrate, from the gate terminal (G) through the dielectric layer ( 9 ) is isolated and laterally to the channel ( 12 ). Semiconductor component according to one of claims 1 to 12, characterized in that below the buried semiconducting region ( 20 ) other semiconducting areas ( 20 ' ) of the second conductivity type, which are electrically conductive with the fifth semiconducting region ( 5 ) and from each other through semiconducting areas ( 14 ' ) of the first conductivity type which is electrically conductive with the substrate ( 1 ) are spaced apart.