DE102005048447B4 - Semiconductor power device with charge compensation structure and method of making the same - Google Patents

Semiconductor power device with charge compensation structure and method of making the same

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Publication number
DE102005048447B4
DE102005048447B4 DE102005048447A DE102005048447A DE102005048447B4 DE 102005048447 B4 DE102005048447 B4 DE 102005048447B4 DE 102005048447 A DE102005048447 A DE 102005048447A DE 102005048447 A DE102005048447 A DE 102005048447A DE 102005048447 B4 DE102005048447 B4 DE 102005048447B4
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semiconductor power
characterized
power device
drift
semiconductor
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DE102005048447A1 (en
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Anton Dr.-Ing. Mauder
Hans-Joachim Dr. Schulze
Helmut Dr. Strack
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Infineon Technologies AG
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Infineon Technologies AG
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712Vertical DMOS transistors, i.e. VDMOS transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692Surface layout
    • H01L29/0696Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873Drain regions
    • H01L29/0878Impurity concentration or distribution
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41766Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor

Abstract

Semiconductor power device with charge compensation structure (2), wherein the semiconductor power device (1) comprises a semiconductor body (3) with a vertical weak to medium doped drift path (4) between a first electrode (5) on top of the semiconductor power device (1) and a second electrode (8) the back side of the semiconductor power device (1), the drift path (4) having vertically aligned drift regions (11) surrounded by vertically aligned charge compensation regions (12) and the charge compensation regions (12) comprising a number of vertically stacked pn junctions (11) 13) with highly doped p + and n + regions (14, 16), the sum of the breakdown voltages of the stacked pn junctions (13) of the charge compensation regions (12) being smaller than the breakdown voltage of the drift regions (11).

Description

  • The The invention relates to a semiconductor power device with an in a semiconductor body formed in the current flow direction drift path of a semiconductor material of a conductivity type. The drift path is between at least one disposed first and a second electrode and has a charge compensation structure on. Furthermore, the invention relates to a process for the preparation of the semiconductor element. Such semiconductor elements with a drift path Depending on the design of the drift path for high voltages up to several 100 volts can be used.
  • In conventional MOSFETs with drift path, the maximum donor concentration [N D ] in an n - region as the drift path and thus also the electrical conductivity of the drift path is determined by the required blocking capability or vice versa. In the avalanche breakthrough, approximately 1.5 × 10 12 cm -2 donors are then ionized, which find their counter-charge in the acceptor charge of the p-type region of the conventional MOSFET structure. If a higher donor concentration is to be made possible, countercharges for the donor atoms of the drift path or of the n - region must be found approximately in the same component plane as the drift path. In MOS field plate transistors with trench structure, as is known from the publication US 6,573,558 B2 are known, this is done by the charge carriers of the field plate.
  • at Compensation components as in the "CoolMOS", the n-areas arranged alternately in cells and p-regions, this is done by acceptors of the p-regions as countercharges.
  • If the electrical conductivity of a drift path with an n-region by compensation structures such. B. in a "CoolMOS" can be further improved so that it reaches an average dopant concentration, the degree of compensation must be adjusted more accurately. This is already reaching the limits of technological feasibility, so that the drift paths of "CoolMOS" semiconductor power devices, which are described in the publication DE 103 40 131 have an impurity concentration up to [N] ≤ 2 × 10 17 cm -3 .
  • From US 6,573,558 B2 known MOS field plate transistors with trench structure have the disadvantage that depending on the type of connection of the field plate either at the source or at the drain end to the n - area the full reverse voltage drops and thus very thick insulation layers are required. At 600 V continuous load, an approximately 3 microns to 6 microns thick SiO 2 would be required, which significantly reduces the effect of the field plate in the provision of countercharges.
  • Other semiconductor power devices are from the document US 6,608,350 B2 known. These have trench structures. With such known trench structures, a high-voltage transistor having a low on-state resistance can be formed on an n + -type semiconductor substrate having a lightly doped semiconductor body region on the n + -type semiconductor substrate by diffusing compensation regions from the trench structure into the lightly doped semiconductor body region. The trench can be filled with a dielectric or a highly resistive semi-insulating Mate rial, as it is also in the DE 198 488 28 C2 is described.
  • Semiconductor power devices with trench structure are also from the documents US 4,893,160 and US 5,282,018 known. In these trench structures avalanche breakthroughs in the lightly doped region between a gate arrangement in the trench structure and a drain region with highly doped substrate are avoided by medium to highly doped zones in the region of the trench bottoms. Semiconductor components having a trench structure have the fundamental disadvantage that in some cases no standard methods of semiconductor technology exist for producing the trench structure and for the structured filling of the trenches, so that new methods have to be developed at high cost in order to realize such new semiconductor power components.
  • Out US 2004/0084721 A1 is a semiconductor power device for low level and middle reverse voltage classes known instead of charge compensation structures Having buried diode stack along the drift zone.
  • Semiconductor power devices for blocking voltages however, with some 100 volts are extremely critical in their avalanche behavior. By the high voltages in the breakthrough case are already at small Avalanche currents high power losses implemented in the semiconductor power device. These are predominantly in zones of high field strength at and near the blocking pn junctions localized. Therefore, semiconductor power devices are in principle over, for example Varistors of comparable blocking resistance in avalanche behavior At a disadvantage, since varistors through the multiple series and parallel circuits of Diode structures with comparatively low reverse voltage the Power dissipation almost homogeneous to the device volume to distribute. You can therefore for spark quenching be used with high voltage contacts without being destroyed themselves.
  • By further miniaturization of semiconductor power devices for high voltage applications thus becomes the avalanche strength to the limiting parameter, because the power density loss due to overload of the higher one Rated current increases while the thermal capacity of the Semiconductor volume by the Miniaturisierungsbedarf constantly decreases. As a result, critical temperatures that lead to blocking failure, already achieved at a smaller proportion of the rated current than in semiconductor devices with a lower rated current density.
  • task The invention is a semiconductor power device with drift path and charge compensation structure, despite increased nominal current density in the case of passage, in the case of blocking an improved avalanche resistance having. It is another object of the invention, a cost-effective method specify with which such a semiconductor power device manufactured using standardized methods of semiconductor technology can be.
  • These The object is achieved with the subject matter of the independent claims. advantageous Further developments of the invention will become apparent from the dependent claims.
  • According to the invention, a semiconductor power device with compensation structure is provided, wherein the semiconductor power device has a semiconductor body with a vertical weak to medium doped drift path between a first electrode on top of the semiconductor power device and a second electrode on the back of the semiconductor power device. In addition, the drift path has vertically aligned drift zones surrounded by vertically aligned charge compensation areas. The charge compensation regions in turn comprise a number of vertically stacked pn junctions with highly doped p + and n + regions, the sum of the breakdown voltages of the stacked pn junctions of the charge compensation regions being less than the breakdown voltage of the respective drift zone.
  • One Such semiconductor power device has the advantage that the in the charge compensation areas stacked pn junctions before reaching the Drift zone breakdown voltage act practically like overvoltage protection diodes and thus an avalanche breakthrough in the drift zones in an advantageous Suppress way.
  • The means that the breakdown voltage of the semiconductor power device through this vertical stack of pn junctions in defines the charge compensation regions within the semiconductor body becomes. In practice, the pn junctions form diodes, the e.g. by multiple implantations in the surface of a each epitaxially deposited silicon layer are introduced. Their series connection within the charge compensation range has a lower breakdown voltage than the edge termination and in MOSFET devices a lower breakdown voltage than the blocking pn junction the body region of the semiconductor power device. The avalanche breakthrough Thus, through the stack of a series of pn junctions of a Stack of diodes within the semiconductor body determined so that it to no highly inhomogeneous heating of the semiconductor power device by an avalanche current in the area of the interfaces of Drift routes comes.
  • Furthermore define the pn junctions the Potential profile within the semiconductor power device, the static locks even without any avalanche breakthrough. By the high, not complete reamed Doping of the vertical layers forming the pn junctions, be mobile charges for the positively charged donor hulls in the adjacent weak to medium-doped area of the drift zones so that the doping in the drift zones is similar to at conventional Compensation components or as in so-called high-k devices, or, as in the case of trench capacitors, significantly increased can, and thus also better on-state values for the semiconductor power device be achieved. The inventive structure of stacked pn junctions in The charge compensation ranges are also suitable as edge termination for semiconductor power devices analogous to the high-k components or the components with corresponding Grave capacitors.
  • The pn junctions can also be implemented as pn - n + transitions for better setting of the individual breakdown voltages. In this case, the vertical dimensioning of the pn - n + structures may be such that there is less than or more than the breakdown charge as integral donor doping between two vertically consecutive p-type regions. Both methods are suitable for the production and can be controlled by the thickness of the epilayer, ie the n - doping lying between two p regions and the height of the n + doping or its thickness. When dimensioning, the donor charge integrally present in the drift zone must be taken into account, whose compensation charge is formed by the p regions. If the integral donor doping exceeds the breakdown charge, the breakthrough occurs through the avalanche or tunnel effect, depending on the level of doping. However, if the integral donor dopant remains below the breakdown charge, then attacks the electric field through to the next p-region, which is not completely eliminated by the field, thus limiting the voltage pickup between two p-regions. The advantage here is that no charge carriers must be transported through the space charge zone.
  • In a preferred embodiment The invention includes the semiconductor material of the semiconductor body homogeneous, monocrystalline semiconductor material, in particular silicon, on. Such homogeneous, monocrystalline semiconductor materials can be by introducing impurities on substitution grid sites dope, taking elements of the third group of the periodic system on substitution grid sites the monocrystalline semiconductor materials at room temperature or at the permissible Operating temperatures of a semiconductor power device a p-type conductivity with acceptor hulls form. Accordingly, elements of the fifth group of the periodic table form on substitution grid sites of the monocrystalline semiconductor material regions with an n-type conductivity, wherein at room temperature and the permissible Operating temperatures of the semiconductor power device electrons donated to the grid, and donor hulls remain on the lattice sites.
  • The pn junctions of the invention in the Charge compensation areas preferably define the field distribution in the power semiconductor device along the drift zones. This will be ensured that in the adjacent drift zones, the field distribution guaranteed is that no avalanche breakthroughs can occur, especially before the stacked pn junctions locally exceed their blocking voltages and break through.
  • In a further preferred embodiment The invention relates to the pn junctions of Charge compensation ranges, which the field distribution of the surrounding Driftzone influence structured so that the drift zones one opposite drift routes without adjacent charge compensation areas by at least the Factor 3 increased dopant concentration at unchanged Have reverse voltage resistance. Thus, by the charge compensation areas not only achieves improved avalanche behavior of the drift zones, but in addition also a lower on resistance for the semiconductor power device allows with a lower power loss in the through-connected state connected, which at the same time means that the heat loss at Semiconductor power devices with the structure according to the invention the charge compensation regions is reduced.
  • In a preferred embodiment invention, the pn junctions of Charge compensation areas in their planar extent in the semiconductor body a Strip, grid, checkerboard or honeycomb structure. With such structures can be guaranteed be adjacent to each drift zone, a charge compensation region exists, and vice versa.
  • In a further embodiment According to the invention, the stacked pn junctions comprise semiconductor materials same or complementary Conduction type to the conductivity type of the drift zones with a carrier concentration which is at least one order of magnitude higher than the charge carrier concentration in the surrounding drift zones. Due to this high charge carrier concentration in the areas surrounding the stacked pn junctions in the charge compensation areas form, it is achieved that the sum of the reverse voltages of the pn junctions lower is, than the reverse voltages of the drift zones.
  • In a further embodiment The invention is the sum of the breakdown voltages of the individual pn transitions greater than the permissible reverse voltage of the semiconductor power device. This has the advantage that the permissible reverse voltage of the semiconductor power device can be applied without while the stack of PN junctions in the Breaks charge compensation areas. The permissible reverse voltage of Semiconductor power devices is thus below the sum of the breakdown voltages the stacked pn junctions.
  • A single pn junction structure of the stack of pn junctions a thickness d between 0.1 μm ≤ d ≤ 20 μm, preferably between 0.3 μm ≤ d ≤ 10 μm, on. there depends on that Thickness d of a single pn junction structure from the thickness of the epitaxial layer into which the pn junction structure is introduced. In this context, the thickness d is a single one pn junction structure smaller, as the thickness h of an epitaxial layer.
  • The drift zones have a dopant concentration N between 2 × 10 15 cm -3 ≦ N ≦ 10 18 cm -3 , preferably between 1 × 10 16 cm -3 ≦ N ≦ 2 × 10 17 cm -3 . Such a high doping concentration N, which reduces the on-resistance of the semiconductor power component, in the drift zones is advantageously possible only because correspondingly dimensioned charge compensation regions with stacked pn junctions are arranged adjacent to the drift zones.
  • In a further preferred embodiment of the invention, the extension of a drift zone from a charge compensation region to a next charge compensation region is not more than about 1/3 of the extent of the drift zone in FIG Current flow direction between the first and the second electrode. In principle, this means that the length to width ratio in a drift zone is greater than or equal to 3: 1, to ensure that in the case of blocking, the charges in the drift zone can be compensated by the charge compensation regions.
  • The structure according to the invention is advantageously used for semiconductor power components which are to be used as MOSFETs, or as JFETs, or as IGBTs, or as pn - n diodes, or as Schottky diodes or as bipolar transistors.
  • is the semiconductor power device is designed as a vertical MOSFET, Thus, the drift zones on a highly doped substrate with the same conductivity type arranged like the drift zones. This has the advantage that the web resistance of the drain region kept low by the high doping of the substrate can be. In a further preferred embodiment of the invention ranges the structure of pn junctions in the charge compensation areas approximately up to the highly doped Substrate. This has the advantage that even avalanche effects, in the transition area from weak to medium doped drift zones to the heavily doped Substrate area could occur through the up to the highly doped substrate zoom reaching pn junction structure be avoided.
  • Farther it is provided that the drift zone of the opposite in the region to a main surface of the semiconductor body second electrode adjacent to a highly doped region and with the second electrode as a drain electrode electrically connected stands. The advantage of this construction has already been mentioned above and lies in the fact that the track resistance of the drain region in the semiconductor body up to to the drain electrode is kept as low as possible.
  • Besides that is in MOSFET devices, the first electrode as a source electrode trained and is at source potential. The stack of pn junctions can in the region of the top of the semiconductor body with an additional Electrode, or with the source electrode, or with the gate electrode electrically in operative connection.
  • In a further preferred embodiment According to the invention, the semiconductor power device is a planar one Gate structure with a gate electrode and a gate oxide on. This Gate oxide extends over a channel region of the body zone and isolates the gate electrode, without diminishing their control effect on the channel of the Bodyzone. In a further embodiment According to the invention, the semiconductor power device has a trench gate structure on, wherein the trench gate electrode penetrates the body zone. These Construction has the advantage over the planar gate electrode, that at approx same length the channel of the MOSFET structure, an enlargement of the Width of the canal area can be achieved.
  • In a further embodiment the invention is the width b of a drift zone between the stacked pn transition areas, in the range of 1 μm ≤ b ≤ 30 μm, preferably 2 μm ≤ b ≤ 10 μm. Further lies the length L of a drift zone in the vertical direction in silicon for a breakdown voltage of about 600 volts, between about 30 μm ≤ 1 ≤ 90 μm.
  • A method for producing semiconductor power devices with charge compensation structure comprises the following method steps. First, a highly doped semiconductor wafer of a first conductivity type is produced by a first method step a). Thereafter, in a second method step b), a first weakly to medium-doped epitaxial layer of the first conductivity type is applied as the first step for forming a drift path. This first epitaxial layer of the first conductivity type is realized for MOSFET devices, pn - n diodes or IGBTs. In contrast to pn - n diodes and MOSFETs, in IGBTs the first weakly to medium-doped epitaxial layer of a complementary conductivity type is realized with method step b).
  • In a third process step c) will be a selective ion implantation of substitutional impurities of the complementary Conductivity type to the conductivity type of the surrounding epitaxial layer in Charge compensation regions for generating high and complementary doped Zones performed in the power compensation areas. In a further, fourth process step d) is then a selective Ion implantation of substitutional impurities of the first conductivity type in charge compensation regions for generating highly doped pn junctions in the high and complementary doped zones of the charge compensation areas performed. The Dimensioning of these pn structures in the vertical direction can be done via the Choice of implantation energies of the two implantation steps be set.
  • In a fifth Process step will eventually another weak to medium doped epitaxial layer of the first Line type as a further step to the formation of a drift path under diffusion of the implanted substitutional impurities and repeat the implantation steps c) and d).
  • In process step f), the steps b) to e) repeated several times until a thickness of the drift zone which is sufficient for an intended blocking voltage is achieved with simultaneous formation of highly doped pn junctions in charge compensation regions at the boundaries of the respective epitaxial layers.
  • In a final one Process step g) is at least one final epitaxial layer without introducing a pn junction structure carried out.
  • This Method has the advantage that in each epitaxial layer a pn junction with highly doped impurity concentrations is produced, so that after completion of all epitaxial layers a plurality of stacked pn junctions in the charge compensation regions to disposal stands. The thicknesses of the epitaxial layer and the thickness become the highly doped complementary doped zone, as well as the highly doped produced in these zones Areas of the first conductivity type are coordinated with each other, that the thickness of a pn junction structure is preferably smaller than the thickness of an epitaxial layer.
  • Next the advantages already described above with such Method produced semiconductor power devices is added that The deposition of epitaxial layers is a well-controlled process semiconductor technology, and also doping and ion implantation of impurities is precisely controlled in such epitaxial layers. Consequently can reliably stack up diodes with such a stack of pn junctions within the semiconductor body done with the application of the required for the drift zones Epitaxial layers arise.
  • there are used in a preferred implementation of the method as impurity elements of the complementary Conductivity type impurity elements implanted, whose diffusion coefficient is greater as the diffusion coefficient of the impurity elements of the first Line type for forming pn junctions in the line compensation areas. With such a difference in the diffusion coefficient between the defects for the Different types of lines have the advantage that when Ion implantation of the impurities one and the same mask can be used to selectively only on the bodies impurities bring in, where pn transitions arise should. In the subsequent or subsequent application of an epitaxial layer become temperatures achieved that make that the impurities with higher Diffusion coefficients diffuse deeper than the impurities with a lower diffusion coefficient, so that automatically upon application of the subsequent epitaxial layer, a pn junction structure in the previously selectively doped and ion implanted epitaxial layer established.
  • In Another preferred embodiment of the method the impurity elements of the complementary Conductivity type with a higher Penetration depth implanted in an epitaxial layer, as the impurities of the first conductivity type for forming the pn junctions within the charge compensation regions. Such a different depth implantation of impurities for the formation of pn junctions in Epitaxial layers is required when the diffusion coefficient of the have two dopant elements about the same order of magnitude. on the other hand It may also be advantageous to have a different penetration depth the ion implantation to ensure that corresponding locally separated p and n regions for a pn junction structure form.
  • to Manufacturing a MOSFET will be a source-gate structure in the final, free from buried pn junctions Epitaxial layer introduced, as far as the formation of a body zone of the complementary Conductivity type and a highly doped source terminal zone of the first Type of line concerns. On this final epitaxial layer becomes for one Then the source-gate structure a gate oxide and a gate material are applied as a gate electrode. With such a method becomes a planar source-gate structure produced.
  • For a trench gate structure it is necessary to create a trench that permeates the bodyzone, on its walls subsequently the gate oxide is generated, so that finally the trench structure with the gate electrode material, preferably made of polysilicon, are filled can. The manufacture of trench gate troughs has the advantage that the channel width can be increased significantly, across from a planar gate connection structure.
  • For the production an IGBT will be the same as a heavily doped substrate Conductivity type such as the drift path, a substrate of complementary conductivity type used to form an emitter region.
  • The The invention will now be described with reference to the accompanying figures.
  • 1 shows a schematic cross section through part of a semiconductor power device, in the form of a MOSFET;
  • 2 to 8th show schematic diagrams of manufacturing steps of a method for manufacturing Development of a semiconductor power device, according to 1 ;
  • 2 shows a schematic cross section through a highly doped n + -layer substrate after application of a first weak to medium doped epitaxial layer;
  • 3 shows a schematic cross section through the substrate with epitaxial layer according to 2 after introduction of a highly doped p + -type zone into the weakly to medium-doped n-type epitaxial layer;
  • 4 shows a schematic cross section through the substrate with an epitaxial layer, according to 3 after introducing a highly doped n + -type region into the highly doped p + -type or above the highly doped p + -type region;
  • 5 shows a schematic plan view of an epitaxial layer according to 4 ;
  • 6 shows a schematic cross section through the substrate 17 after application of x + 1 epitaxial layers;
  • 7 shows a schematic cross section through the substrate according to 6 after diffusion of impurities from the highly doped n + and p + regions of the stacked pn junction regions;
  • 8th shows a schematic cross section of a semiconductor power device after applying a source-gate structure on a main top side of the semiconductor body of the semiconductor power device.
  • 1 shows a schematic cross section through part of a semiconductor power device 1 , in the form of a MOSFET 15 , according to an embodiment of the invention. The semiconductor power device 1 points to the back 31 a semiconductor body 3 , a metallization 32 in this embodiment of the invention, a drain electrode D as a second electrode 8th on the back side 9 of the semiconductor power device 1 forms. This metallization is on the back 9 an n + -type substrate 17 applied when, as in this embodiment, a MOSFET is to be produced, and on the other hand has a highly doped p + -type substrate 17 when an IGBT power semiconductor device is to be manufactured.
  • In the case of the MOSFET shown here 15 are on the heavily doped n + -type substrate 17 several epitaxial layers 18 arranged to x + 1, with the epitaxial layer 18 to x + 1 are formed of an n-type monocrystalline silicon material. Generally, one or more epitaxial layers 18 to x + 1 in one or more epitaxial deposition runs (ie, individual layer deposition processes) can be made to produce the desired layer thickness. These parts of the layers may well differ in the layer thickness and / or the height of the doping. Only the layers relevant for the formation of the buried pn junctions or of the body and cell regions are listed here. These stacked epitaxial layers 18 to x + 1 form a drift path 4 from a first electrode 5 , which in this case a source electrode S on the top 7 of the semiconductor power device 1 is. This drift track 4 is in drift zones 11 whose width b is in relation to the height h / b ≤ 1/3.
  • These drift zones 11 become of charge compensation areas 12 a charge compensation structure 2 surrounded, wherein the charge compensation areas 12 in each of the epitaxial layers 18 to x two stacked pn junctions 13 exhibit. The blocking voltage across these pn junctions 13 is adjusted by its doping, wherein the doping of the pn junction-forming layers is at least one order of magnitude higher than the doping of the surrounding drift zones 11 , In this case, the blocking voltage of this pn junction structure of an n + and p + zone is lower than the A valanche effect triggering field peaks in the adjacent drift zones 11 ,
  • The at least one terminal epitaxial layer x + 1 has no charge compensation regions, but serves to provide a p-conducting body zone and a highly doped n + -type junction region for the source electrode S. On the main top 26 of the semiconductor body 3 Accordingly, a planar source-gate structure is arranged, wherein the planar gate structure 27 a gate oxide 35 and corresponding gate electrodes G. The isolated individual gate electrodes 34 become a common gate electrode G via respective wiring lines 33 on the top 7 of the semiconductor power device 1 merged. The advantages of such a semiconductor power device 1 will not be listed again to avoid repetition.
  • Instead of The planar gate structure shown here may also be the invention used in devices that have a trench gate structure exhibit.
  • The 2 to 8th show schematic diagrams of manufacturing steps of a method for producing a semiconductor power device 1 , according to 1 , Components with the same functions as in 1 are ge with the same reference numerals ge features and in the 2 to 8th not discussed separately.
  • 2 shows a schematic cross section through a highly doped n + -type substrate 17 after application of a first weak to medium doped n-type epitaxial layer 18 , The epitaxial layer 18 has a thickness h 18 of 0.1 μm ≤ h 18 ≤ 20 μm, preferably of 0.3 μm <h 18 <10 μm. Such an epitaxial layer 18 is usually on the entire semiconductor substrate 17 of a semiconductor wafer from the gas phase deposited.
  • 3 shows a schematic cross section through the substrate 17 with epitaxial layer 18 according to 2 after introducing a highly doped p + zone with a complementary conductivity type into the weak to medium doped n-type epitaxial layer 18 , The thickness d of this highly doped p + -type region is preferably less than the thickness h 18 of the epitaxial layer 18 , Such a zone 14 can be created by selectively implanting elements of the third group of the Periodic Table into the epitaxial layer, with the final thickness d of the zone 14 in the subsequent Epitaxieschrctt or after high temperature steps later fully formed in the manufacturing process.
  • 4 shows a schematic cross section through the substrate 17 with an epitaxial layer 18 after introducing a highly doped n + -zone 16 in the highly doped or above the highly doped p + zone 14 , according to 3 , By introducing this zone 16 will now have an npn layering under the top 36 the epitaxial layer 18 reached. Also this n + -type zone 16 can be achieved by selective implantation with or without subsequent diffusion step. Is the diffusion constant of the impurities for the p + -type zone 14 significantly larger than the diffusion constant of the n + -type zone 16 So, the same implantation mask for introducing the impurities in the top 36 the epitaxial layer 18 can be used, wherein during a later Epitaxieschrittes or during a separate diffusion step, the two implanted areas then achieve due to the different diffusion coefficient different diffusion depths to form two pn junctions.
  • Another possibility is to use the dopant elements for the p + -type region 14 deeper into the epitaxial layer 18 implant into it and a flatter implantation for the dopant elements of the n + -type zone 16 provided. Also in this case, a single ion implantation mask can be used. By this structuring of charge compensation areas 12 arise in the epitaxial layers 18 to x each have an np + junction and a p + n + junction, and form a stack of pn junctions that have a potential distribution in the line compensation regions 12 create that for a field distribution in the drift zones 11 ensures the avalanche breakthroughs in the drift zones 11 prevented.
  • 5 shows a schematic plan view of the in 4 illustrated structure. In this embodiment of the invention has been a honeycomb structure 30 chosen, with each drift zone 11 of three charge compensation zones 12 is surrounded, so that an optimal land use of the surface 36 the first epitaxial layer 18 for the drift zones 11 results. It is in the charge compensation areas 12 a highly doped n + -type surface surrounded by a p + -type surface, so that below the plane of the drawing two pn-junctions 13a and 13b in the epitaxial layer 18 available. Instead of the honeycomb structure shown here 30 can also be the areal extent of the charge compensation areas 12 in alternation with the drift zones 12 have a strip, grid or checkerboard pattern structure.
  • 6 shows a schematic cross section through the substrate 17 after application of x + 1 epitaxial layers with corresponding charge compensation regions 12 and with stacked pn junctions 13 , Depending on the diffusion characteristics of the respective impurity of the highly doped n + - and p + -type regions of the pn junctions, this structure can also in each over the first epitaxial layer 18 growing next epitaxial layer 19 diffuse into, which is shown in the next figure.
  • 7 shows a schematic cross section through the substrate 17 according to 6 , after out-diffusion of impurities of the n + - and p + -zones of the stacked pn-junctions 13 , At this time, the thickness d of each of the pn junction structures remains 10 preferably under the thickness h of the individual epitaxial layers. The uppermost at least one epitaxial layer x + 1 is not provided for the formation of buried pn junctions in this embodiment of the invention, but a p-conducting body zone is formed in this final epitaxial layer x + 1 6 as in 8th shown with complementary conductive material in relation to the conductivity type of the drift path and with n + -type regions within the p + -type body zone for corresponding source connection zones 29 introduced, which also in the following 8th are shown. This introduction of these zones into the uppermost epitaxial layer x + 1 can likewise be effected by ion implantation with subsequent diffusion.
  • 8th shows a schematic cross section of a semiconductor power device 1 after applying a source-gate structure 28 on a Main top 20 of the semiconductor body 3 , The semiconductor body 3 sits down from the substrate 17 and the epitaxial layers of thickness h e , as in 6 ge be together. On the main top 20 of the semiconductor body 3 becomes for the planar gate structure 27 a structured gate oxide layer 35 produced by thermal oxidation of the silicon, and on this submicrometer thick gate oxide layer 35 Gate electrodes G are deposited from highly doped polycrystalline silicon, so that these gate electrodes G can be isolated from the source electrode S by further oxidation.
  • 1
    Semiconductor power device
    2
    Charge compensation structure
    3
    Semiconductor body
    4
    drift
    5
    first electrode
    6
    P-type Body zone
    7
    top of the semiconductor power device
    8th
    second electrode
    9
    back of the semiconductor power device
    10
    pn junction structure
    11
    drift region
    12
    Power factor correction area
    13a, 13b
    pn junction
    14
    highly doped p + -type zone
    15
    MOS field-effect power transistor
    16
    highly conductive n + -type zone
    17
    substratum
    18 to 25
    epitaxial layers
    26
    Main top of the semiconductor body
    27
    planar gate structure
    28
    Source-gate structure
    29
    Source terminal zone
    30
    Honeycomb structure
    31
    back of the semiconductor body
    32
    metallization
    33
    wiring lines
    34
    separate gate electrode
    35
    gate oxide
    36
    top the n-epitaxial layer
    b
    width a drift zone
    f
    extensive extension
    H
    vertical Thickness of a drift zone
    h e
    thickness the sum of the epitaxial layers
    h 13 to h x + 1
    thickness of different epitaxial layers
    x
    final epitaxial layer
    x + 1
    final epitaxial layer
    D
    drain
    G
    gate electrode
    S
    source electrode

Claims (36)

  1. Semiconductor power device with charge compensation structure ( 2 ), wherein the semiconductor power device ( 1 ) a semiconductor body ( 3 ) with a vertical weak to medium doped drift path ( 4 ) between a first electrode ( 5 ) on top of the semiconductor power device ( 1 ) and a second electrode ( 8th ) on the backside of the semiconductor power device ( 1 ), wherein the drift path ( 4 ) vertically oriented drift zones ( 11 ) of vertically aligned charge compensation regions ( 12 ) and wherein the charge compensation regions ( 12 ) a number of vertically stacked pn junctions ( 13 ) with highly doped p + and n + regions ( 14 . 16 ), wherein the sum of the breakdown voltages of the stacked pn junctions ( 13 ) of the charge compensation regions ( 12 ) is less than the breakdown voltage of the drift zones ( 11 ).
  2. Semiconductor power device according to claim 1, characterized in that the semiconductor material of the semiconductor body ( 3 ) has a homogeneous monocrystalline semiconductor material, in particular silicon (Si).
  3. Semiconductor power device according to claim 1 or claim 2, characterized in that the pn junctions ( 13 ) of the charge compensation regions ( 12 ) the field distribution in the power semiconductor power device ( 1 ) along the drift zones ( 11 ) define.
  4. Semiconductor power component according to one of the preceding claims, characterized in that the pn junctions ( 13 ) of the charge compensation regions ( 12 ) the field distribution of the surrounding drift zones ( 11 ) such that the drift zones ( 11 ) one versus drift paths without adjacent charge compensation regions ( 12 ) have at least a factor of 3 increased dopant concentration with unchanged blocking voltage resistance.
  5. Semiconductor power component according to one of the preceding claims, characterized in that the pn junctions ( 13 ) of the charge compensation regions ( 12 ) in their planar extent in the semiconductor body ( 3 ) a strip, grid, checkerboard or honeycomb structure ( 30 ) exhibit.
  6. Semiconductor power device according to one of the preceding claims, characterized in that the stacked pn junctions ( 13 ) Semiconductor materials of a same (n) and a complementary (p) conductivity type to the conductivity type (s) of the drift zones ( 11 ) having a carrier concentration by at least one power of ten is higher than the charge carrier concentration in the surrounding drift zones ( 11 ).
  7. Semiconductor power component according to one of the preceding claims, characterized in that the sum of the breakdown voltages of the individual pn junctions ( 13 ) is greater than the permissible reverse voltage of the semiconductor power device ( 1 ).
  8. Semiconductor power device according to one of the preceding claims, characterized in that a single pn junction structure ( 10 ) of the stack of pn junctions ( 13 ) has a thickness d between 0.1 μm ≤ d ≤ 20 μm, preferably between 0.3 μm ≤ d ≤ 10 μm.
  9. Semiconductor power device according to one of the preceding claims, characterized in that the drift zones ( 11 ) have a dopant concentration N between 2 × 10 15 cm -3 ≦ N ≦ 10 18 cm -3 , preferably between 1 × 10 16 cm -3 ≦ N ≦ 2 × 10 17 cm -3 .
  10. Semiconductor power device according to one of the preceding claims, characterized in that the extent of a drift zone ( 11 ) of a charge compensation region ( 12 ) to a next charge compensation area ( 12 ) no more than about 1/3 of the extent of the drift zone in the current flow direction between the first and the second electrode ( 5 . 8th ) is.
  11. Semiconductor power component according to one of the preceding claims, characterized in that the semiconductor power component ( 1 ) a MOSFET ( 15 ) or a JFET or an IGFET or a PIN diode or a Schottky diode or a bipolar transistor.
  12. Semiconductor power component according to one of the preceding claims, characterized in that the semiconductor power component ( 1 ) a vertical MOSFET ( 15 ) and the drift zones ( 11 ) on a heavily doped substrate ( 17 ) with the same conductivity type as the drift zones ( 11 ) are arranged.
  13. Semiconductor power device according to one of the preceding claims, characterized in that the structure consists of pn junctions ( 13 ) up to the heavily doped substrate ( 19 ).
  14. Semiconductor power device according to one of the preceding claims, characterized in that the drift zones ( 11 ) in the region of the main surface ( 26 ) of the semiconductor body ( 3 ) opposite second electrode ( 8th ) to a highly doped region and with the second electrode ( 8th ) as a drain electrode (D) are electrically connected.
  15. Semiconductor power component according to one of the preceding claims, characterized in that the first electrode ( 5 ) is at source potential as the source electrode (S).
  16. Semiconductor power device according to one of the preceding claims, characterized in that the stack of pn junctions ( 13 ) in the area of the main surface ( 26 ) of the semiconductor body ( 3 ) is provided with an additional electrode.
  17. Semiconductor power device according to one of the preceding claims, characterized in that the stack of pn junctions ( 13 ) is electrically connected to the source electrode (S).
  18. Semiconductor power device according to one of the preceding claims, characterized in that the stack of pn junctions ( 13 ) is electrically connected to the gate electrode (G).
  19. Semiconductor power component according to one of the preceding claims, characterized in that the semiconductor power component ( 1 ) a planar gate structure ( 27 ) with a gate electrode (G) and a gate oxide ( 35 ) having.
  20. Semiconductor power component according to one of the preceding claims, characterized in that the semiconductor power component ( 1 ) has a trench gate structure.
  21. Semiconductor power component according to one of the preceding claims, characterized in that the trench gate electrode is a body zone ( 6 ) penetrates.
  22. Semiconductor power device according to one of the preceding claims, characterized in that the width b of a drift zone ( 11 ) between the stacked pn junctions ( 13 ) in the range of 1 μm ≤ b ≤ 30 μm, preferably 2 μm ≤ b ≤ 10 μm.
  23. Semiconductor power device according to one of the preceding claims, characterized in that the length l of a drift zone ( 11 ) in the vertical direction in silicon for a breakdown voltage of about 600 V between about 30 microns ≤ 1 ≤ 90 microns.
  24. Semiconductor power device according to one of the preceding claims, characterized in that the pn junctions as pn - n + -Struktu are executed ren.
  25. Semiconductor power device according to claim 24, characterized in that for the vertical dimensioning of pn - n + structures between two vertically successive p-regions less or more than the breakdown charge is provided as an integral donor dopant.
  26. Semiconductor power device according to claim 24 or claim 25, characterized in that the n - doping lying between two p regions and the height of the n + doping or the thickness thereof are controlled such that the donor charge integral in the drift zone, the Compensation charge is formed by the p-areas are taken into account.
  27. Semiconductor power device according to one of claims 24 to 26, characterized in that when the integral donor doping exceeds breakthrough charge, the breakthrough over the avalanche or tunneling effect, depending on the level of doping and when the integral donor dopant is below the breakdown charge remains, the electric field penetrates to the next p-area, that from the field is not complete cleared is such that the voltage is limited between two p-regions is.
  28. Method for producing a semiconductor power component ( 1 ) with charge compensation structure ( 2 ), the method comprising the following steps: a) producing a highly doped semiconductor wafer of a first conductivity type; b) applying a first lightly doped to medium doped epitaxial layer ( 18 ) of the first conductivity type as the first step to form a drift path ( 4 ); c) selective implantation of substitutional impurities of the complementary conductivity type to the conductivity type of the surrounding epitaxial layer ( 18 ) in line compensation areas ( 12 ) for creating highly doped and complementary doped zones ( 14 ) in the line compensation areas ( 12 ); d) selectively implanting substitutional impurities of the first conductivity type in conduction compensation regions ( 12 ) for generating highly doped pn junctions ( 13 ) in the highly and complementarily doped zones ( 14 ) of the line compensation areas ( 12 ); e) application of a further weakly to medium doped epitaxial layer ( 19 ) of the first conductivity type as a further step for forming a drift path ( 4 ) with diffusion of the implanted substitutional impurities and repeating the implantation steps c) and d); f) repeated repetition of step e) until a thickness of the drift zone ( 11 ) with simultaneous formation of highly doped pn junctions ( 13 ) in charge compensation areas ( 12 ) at the boundaries of the epitaxial layers ( 18 to 25 ) is reached; g) applying at least one final epitaxial layer (x + 1).
  29. Method according to claim 28, characterized in that one or more of the epitaxial layers ( 18 to x + 1) in one or more individual layer deposition processes to produce the desired layer thickness, wherein the individual layers differ or are identical in layer thickness and / or level of doping.
  30. A method according to claim 28 or claim 29, characterized in that as impurity elements of the complementary conductivity type impurity elements are implanted whose diffusion coefficient is greater than the diffusion coefficient of the impurity elements of the conductivity type to form the pn junctions ( 13 ) in the line compensation areas ( 12 ).
  31. Method according to one of claims 28 to 30, characterized in that the impurity elements of the complementary conductivity type with a higher penetration depth into an epitaxial layer ( 18 to 25 ) are implanted as the impurity elements ( 13 ) of the conductivity type for forming the pn junctions in the line compensation regions ( 12 ).
  32. Method according to one of claims 28 to 31, characterized in that for the production of a MOSFET ( 15 ) a source-gate structure ( 28 ) is introduced into the final epitaxial layers (x + 1) as far as the formation of a body zone ( 6 ) of the complementary conductivity type and a highly doped source connection zone ( 29 ) of the first conductivity type and on the final epitaxial layer, as far as the formation of a gate oxide ( 35 ) and a gate connection.
  33. Method according to one of claims 28 to 32, characterized in that for producing an IGBT instead of a heavily doped substrate ( 17 ) of the same conductivity type as the drift path ( 4 ) a substrate ( 17 ) of complementary conductivity type is used to form an emitter region.
  34. A method according to any one of claims 28 to 31 or claim 33, characterized in that for producing an IGBT's an emitter structure with insulated gate into the final epitaxial layer (x + 1) is introduced.
  35. Method according to one of claims 28 to 31, or claim 33, characterized in that for producing a pn - n diode in the ab closing epitaxial layer (x + 1) a heavily doped anode junction zone of the first conductivity type is introduced.
  36. Method according to one of claims 28 to 35, characterized in that for introducing a highly doped zone and / or for introducing a body zone ( 6 ) implanted in the final epitaxial layers (x + 1) first with a selective implantation impurity elements and then the impurity elements are diffused on substitution grid sites by means of a diffusion step.
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DE102006061994B4 (en) 2006-12-21 2011-05-05 Infineon Technologies Austria Ag Charge compensation device with a drift path between two electrodes and method for producing the same
DE102007018631B4 (en) * 2007-04-19 2009-01-22 Infineon Technologies Austria Ag Semiconductor device with compensation zones and discharge structures for the compensation zones
DE102007020659B4 (en) 2007-04-30 2012-02-23 Infineon Technologies Austria Ag Semiconductor device and method of making the same
US7880200B2 (en) * 2007-09-28 2011-02-01 Infineon Technologies Austria Ag Semiconductor device including a free wheeling diode
EP2884538A1 (en) * 2013-12-16 2015-06-17 ABB Technology AB Power semiconductor device

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