DE102006025374B4 - A junction field effect transistor arrangement and method for driving a junction field effect transistor - Google Patents

Abstract

Junction field effect transistor arrangement, with
At least one junction field effect transistor;
At least one gate drive device, comprising:
A power supply device for providing an electric current,
A switching device for selectively short-circuiting the current-providing device, and
A charge storage device which is electrically switchable or switched to the current supply device;
Wherein the current providing means is electrically coupled to at least one gate terminal and at least one source / drain terminal of the at least one junction field effect transistor such that the electrical current provided by the current providing means at least partially into a control side pn junction between the gate terminal and the source / drain terminal of the junction field effect transistor can be impressed.

Description

The The invention relates to a junction field effect transistor arrangement and a method of driving a junction field effect transistor.

Next the further development of silicon-based power semiconductor switches Meanwhile, the material silicon carbide (SiC) for use controllable in power electronic circuits, see for example [1], [2]. Due to the excellent material properties of SiC can be based on its high-blocking, unipolar semiconductor switches see, for example [3], and find SiC field-effect transistors therefore increasingly attention.

When active switching element or active switch is the junction field effect transistor (Junction Field Effect Transistor, JFET) in the focus of the developers, see for example [4]. This transistor type is not used by a MOS-gate (MOS: Metal Oxide Semiconductor) controlled, which would allow a simple adaptation of known driver topologies, but by means of the space charge zone of a reverse-biased pn junction between the gate and the source of the JFET. A JFET therefore requires a different driver topology than devices with a MOS gate such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) or IGBTs (Insulated Gate Bipolar Transistor).

The Control of a JFET is done by means of the gate-source voltage. At a Gate-source voltage of 0 volts, the circuit breaker is conductive. If the JFET is to be disabled, it must be negative in the case of an n-channel JFET Voltage is applied between the gate and the source (in the case of a p-channel JFET, accordingly, a positive Tension). The space charge zone (low-carrier zone) of the reverse direction operated pn junction extends deeper and deeper into the n (p) channel with enough greater negative gate-source voltage (or in the case of a p-channel JFET with a sufficiently large positive gate-source voltage) completely off (Pinch-off voltage or pinch-off voltage): the JFET is blocking. The gate leakage current is negligibly small. With rising negative gate-source voltage (or for a p-channel JFET with increasing positive gate-source voltage) however, at a breakdown voltage, the gate leakage current abruptly decreases to and would destroy the component.

1A shows a schematic half-cell cross-sectional view 100 a conventional vertical n-channel JFET, and 1B shows an associated switching symbol 150 in which on the JFET 100 applied electrical voltages (gate-source voltage u _GS , drain-gate voltage u _DG , drain-source voltage u _DS ) or through the JFET 100 flowing electrical currents (gate current i _G , drain current i _D ) are drawn.

The JFET 100 has a source connection 101 , a drain connection 102 and a gate terminal 103 on. Further, the JFET has 100 a first (n -) doped region 104 , a second (n -) doped region 105 , an n ++ doped region 106 , a first p ++ doped region 107 and a second p ++ doped region 108 on.

As can be seen in cross-section, the source terminal 101 and the drain connection 102 in the absence of a gate-source voltage u _GS (or at u _GS = 0) solely by means of n-doped regions, ie the first weakly n-doped region 104 (n-epilayer 1), the second weakly n-doped region 105 (n-Epilayer 2) and the very heavily n-doped (n ++) range 106 , electrically connected to each other, so that in this case a low ohmic resistance between the source terminal 101 and the drain port 102 results. In other words, the circuit breaker 100 or the JFET 100 conductive. Since this is the case without a gate-source voltage u _GS , this is called the normally-on behavior.

Should the JFET 100 lock, the electrical connection between source 101 and drain 102 become high impedance. This can be achieved by applying a negative voltage u _GS (u _GS <0) between the gate contact 103 and the source contact 101 is created. The result is a reverse-biased pn junction (transition between the first p + + doped region 107 and the second (n -) doped region 105 ), whose space charge zone (low-carrier zone) extends into the channel and this completely strangles at sufficiently low voltage u _GS (ie, at a sufficiently large amount | u _GS |), ie in a high-impedance state.

This in 2 illustrated diagram 200 shows the dependence of the drain current i _D (curves 201 . 201b ) and the gate current i _G (curves 202a . 202b ) of an n-channel JFET from the gate-source voltage u _GS for two different temperatures T ₁ = 25 ° C and T ₂ = 125 ° C.

In other words, in 2 the drain current i _D as a function of the gate-source voltage u _GS (i _D = f (u _GS ), where u _DS = 1.56 V) and the gate current i _G as a function of the gate-source voltage (i _G = f (u _GS )) plotted for two different values of the parameter T (temperature).

How out 2 is apparent, the drain current i _D decreases with decreasing voltage u _GS until it becomes zero at the pinch-off voltage or pinch-off voltage u _PI .

In the example shown, the pinch-off voltage u _{PI is} approximately -18 V.

For negative voltages u _GS , the current through the gate i _G behaves as expected from a pn junction in the reverse direction: The pn junction blocks up to a breakdown voltage u _BR . If the gate-source voltage u _{GS drops} below the breakdown voltage u _BR , the gate current i _G (more precisely, the magnitude | i _G | of the gate current) increases sharply and, for excessively large values i _G <i _{Gcrit_backw,} can Control route and thus thermally destroy the device. In other words, the JFET can be destroyed if the gate current i _{G falls} below a critical value i _{Gkrit_rückw} .

If the gate-source voltage u _GS becomes positive, the current i _G rises rapidly from the threshold voltage of the pn junction and can also destroy the component for excessively large values i _G > i _{Gcrit_vorw} . In other words, the JFET can also be destroyed if the gate current i _G exceeds a second critical value i _{Gkrit_vorw} .

• i) im Ein-Zustand ("on") des JFETs sollte gelten: u_GS > u_PI und i_G < i_{Gkrit_vorw}
• ii) im Aus-Zustand ("off") des JFETs sollte gelten: u_GS < U_PI und i_G > i_{Gkrit_rückw}

From the above considerations, conclusions can be drawn for safe operation of the JFET gate-source control path:

• i) in the on state ("on") of the JFET, the following should apply: u _GS > u _PI and i _G <i _{Gcrit_vorw}
• ii) in the _OFF state ("off") of the JFET should apply: u _GS <U _PI and i _G > i _{Gkrit_rückw}

• i) Gemäß einer ersten, zum Beispiel in [5], [6], [7], [8], [9] beschriebenen, Variante wird zum Abschalten eines JFETs zwischen Gate und Source des JFETs eine Treiber-Spannung u_TR angelegt, deren Wert zwischen der Durchbruchspannung u_BR und der Pinch-off-Spannung u_PI des Transistors liegt, d.h. es gilt uBR < uTR < uPI. (1)

In order to operate a power semiconductor with the properties mentioned, different methods are known from the prior art. In many cases, a drive voltage u _{TR is} applied to critically turn off such a transistor between the gate terminal and the source terminal of the JFET, and the corresponding methods can be essentially divided into two variants.

• i) According to a first variant described, for example, in [5], [6], [7], [8], [9], a driver voltage u _{TR is} applied for switching off a JFET between gate and source of the JFET, the value of which lies between the breakdown voltage u _BR and the pinch-off voltage u _{PI of} the transistor, ie it applies u BR <u TR <u PI , (1)

• ii) Gemäß einer zweiten, zum Beispiel in [10], [11] beschriebenen, Variante wird zum Abschalten ebenfalls eine Treiberspannung u_TR verwendet, diese ist allerdings weitaus kleiner als die Durchbruchspannung u_BR der pn-Steuerstrecke, d.h. es gilt uTR < uBR < uPI. (2)

Since, on the one hand, the pinch-off voltages u _PI and the breakdown voltages u _BR are subject to variations and differ by a few volts depending on the JFET pattern (for example, u _PI can vary between -20 V and -28 V), and on the other hand the breakdown voltage u _{BR has} a temperature dependence (see. 2 ), in this case, for safe switching off, the used driver voltage u _{TR must be} carefully adapted to each individual transistor. Otherwise, there is a risk that the device can no longer safely be switched off or the pn-control path can be interrupted by an excessive current | i _G | thermally overload.

• ii) According to a second variant, described for example in [10], [11], a drive voltage u _{TR is also} used for switching off, but this is much smaller than the breakdown voltage u _{BR of} the pn-control path, ie it applies u TR <u BR <u PI , (2)

ein.Clearly, in variant ii) the JFET is operated in the breakdown region. So that the gate current i _{G is} limited in the breakdown mode, an ohmic resistance R is connected between the voltage source and the gate-source path. With this principle, the JFET is safely shut down regardless of the pinch-off voltage and the breakdown voltage, since the controlling pn junction is operated in the breakdown. Assuming a constant driver voltage u _TR , the gate current i _G is static (simplified) as a function of the pattern and temperature-variable breakdown voltage u _BR

one.

Out [12], [13] it is known to use a JFET by means of a current source turn off at the gate. It does not become the gate voltage, but the gate (leakage) current for switching off the JFET is set. The control current is greater than the normal gate leakage current, but less than the maximum allowable gate current. The pn gate path of the JFET is operated in the breakdown. To turn on the JFET (conductive state), the gate control current off.

adversely however, in the methods disclosed in [12], [13], the For purposes of turning off the JFET an additional measuring device and an elaborate one Control device for the gate current will be necessary.

at Using unregulated power sources to lock a JFET can the case that occurs with certain inverter arrangements (Inverters) a JET just turned off again and turns on a bridge short circuit caused (so-called Miller effect). To avoid this, will in [13] uses a further power source device which is used for safely turn off the JFET temporarily an increased gate current supplies.

at other converters, for example a matrix converter (see e.g. [14]), is the same with the method proposed in [13] called problem of unintentionally restarting a straight However, disconnected JFETs difficult or impossible, because then several transistors as the cause and a complicated commutation apparatus is present.

In [15] is a driver circuit for discloses a circuit breaker having a drain connection, a source connection and a control terminal of the circuit breaker is electrically coupled, the circuit breaker over a buffer amplifier is driven with a voltage. The driver circuit points a power source, as well as a first switch, with its help the power source can be shorted. Furthermore, the driver circuit a capacity on which by means of a second switch to the power source in parallel can be switched. Between the control terminal of the circuit breaker and the capacity a characteristic element and a buffer amplifier are connected. Furthermore, can the power source by means of the first switch in series with the characteristic element and the buffer amplifier be switched.

In [16] is a control circuit for driving an n-channel MOS transistor discloses, wherein a current source formed in the control circuit is coupled to the gate of the n-channel MOS transistor.

Of the The invention is based in particular on the problem of a junction field effect transistor or JFET safely turn off.

The Problem is solved by a junction field effect transistor arrangement and a A method of driving a junction field effect transistor having the features according to the independent claims.

exemplary Embodiments of the invention will become apparent from the dependent claims.

It For example, a junction field effect transistor arrangement is provided. The junction field effect transistor arrangement has at least one junction field effect transistor, as well at least one gate driver having at least a gate terminal and at least one source / drain terminal the at least one junction field effect transistor electrically is coupled.

The Gate drive means comprises a power supply means, which power supply means with a gate terminal and with a source / drain terminal of a junction field effect transistor electrically coupled, for providing an electric current. The gate drive device further comprises a switch means for selectively shorting the current providing means. Farther has the gate driver a charge storage device, which charge storage device to the power providing facility electrically switchable or connected in parallel.

In a method for driving a junction field effect transistor, in a first operating state of the junction field effect transistor, an electric current is provided to the junction field effect transistor, such that the junction field effect transistor is operated in the breakdown region. Further, in a second operating state of the junction field effect transistor, electric charge is applied between wherein at least a portion of the cached electrical charge in the first operating state is provided to the junction field effect transistor.

According to one Embodiment of the invention is the power supply device as an electrical power source formed, for example, as a constant-current electric power source.

One aspect of the invention may be seen in that a constant current source may be used to statically force the control-side pn-junction of one (or more) junction-field-effect transistor (JFET) into the breakdown and thus the transistor for safe turn-off. In other words, the control-side pn junction (gate-source path) of a JFET can be controlled in breakthrough mode by means of a constant current source and thus the JFET can be blocked. A gate current set once (for example, i _G approximately equal to -150 μA) can be impressed in its gate path independently of the breakdown voltage of the JFET, as long as a driver voltage u _TR available to the current source is smaller than the minimum breakdown voltage u _BR is. For turning on the JFET (ie gate-source voltage u _GS is greater than the pinch-off voltage u _PI : u _GS > u _PI ), the current-providing device (current source) and also the gate-source path of the JFETs are short-circuited by means of a switch (ie by means of the switching device), so that the power switch at the gate voltage zero (0 volts) becomes conductive.

In In this context it should be noted that unlike voltage sources, shorting a power source is an uncritical and allowed operating mode.

In certain power electronic circuits (eg voltage DC link converter, matrix converter) may occur the case that a turned-off, but reverse conducting first transistor by a switching action of another transistor in the forward blocking state, and thus that the reverse current of the first transistor commuted (passive switching). Here, changing the voltage ratios between the reverse conducting state and the forward blocking state may change the charge of the parasitic transistor capacitances (ie, the drain-gate capacitance C _DG , the gate-source capacitance C _GS, and the drain-source capacitance C _DS ) result.

In this connection, it has been recognized that - regarding the gate-source path - the drain-gate capacitance C _DG must be reloaded by more than the amount of a blocking voltage u _blocking to be absorbed. This is the result of a shift current i _DG , which inevitably flows through the gate-source capacitance C _GS . The current i _DG from the drain to the gate is generally transiently greater than the current i _G , which is entered by the driver current source in the opposite direction (eg, i _G = -150 μA). This leads to the discharge of the gate-source capacitance C _GS and thus to the increase of the gate-source voltage u _GS . The gate-to-source voltage u _GS can quickly increase beyond the level of the pinch-off voltage u _PI , causing the transistor to turn on and cause a short circuit in the power circuit.

Once the transient charge transfer of the parasitic capacitances has ended, the drive current source again charges the capacitances C _GS and C _DG in such a way that the voltage u _GS becomes smaller than u _PI and statically assumes the value u _BR . However, the process of recovering the blocking capability of the transistor may take a few microseconds (μs) so that unwanted losses in the power device may arise during the short circuit phase and stress the JFET.

One Aspect of the invention can be seen in that a novel static JFET gate driver principle is provided. In which new driver principle can already improve the level of breakdown voltage of the JFET charged charge storage device in off mode parallel to the driver power source and thus to the gate-source path of the JFET be switched.

According to one According to an embodiment of the invention, the charge storage device has at least one capacity.

According to one Another embodiment of the invention is the charge storage device from a capacity, for example, a capacitor.

If a capacitor C _{stat is switched} parallel to the gate-source path of a junction field-effect transistor in the off-state, the gate-source capacitance C _GS 'acting in this case is calculated as follows: C GS '= C GS + C stat , (4)

As the value of C _{stat increases} , the amount of charge transferred to C _GS ', resulting from the transient current i _DG , leads to an ever decreasing voltage drop of the gate-source voltage u _GS and thus prevents possible short-circuiting that occurs briefly.

According to one Another embodiment of the invention, the switching device as electrical switching device or designed as an electrical switch.

According to one Another embodiment of the invention, the current-providing device a first electrical terminal connected to the gate terminal the junction field effect transistor is electrically coupled, and a second electrical connection connected to the source / drain terminal of Junction field effect transistor is electrically coupled.

According to one Another embodiment of the invention, the switching device to the power supply device electrically connected in parallel.

According to one Another embodiment of the invention, the switching device a third electrical connection which connects to the gate terminal the junction field effect transistor electrically coupled, and a fourth electrical connection, which with the source / drain connection the junction field effect transistor is electrically coupled.

According to one Another embodiment of the invention, the charge storage device a fifth electrical connection, which is electrically connected to the gate terminal of the junction field effect transistor can be coupled, and a sixth electrical connection, which to the source / drain terminal of the junction field effect transistor electrically coupled.

According to one Another embodiment of the invention comprises the gate drive device a second switching means for selectively connecting in parallel the charge storage device (for example the capacity) to the power providing facility.

According to one Another embodiment of the invention is the second switching device electrically connected in series to the charge storage device.

According to one Another embodiment of the invention, the second switching device a seventh electrical connection and an eighth electrical Connection to.

According to one In another embodiment, the second switching device is set up such that the seventh electrical connection of the second switching device with the gate terminal the junction field effect transistor is electrically coupled, and that the eighth electrical connection of the second switching device with the fifth electrical connection of the charge storage device electrically is coupled.

According to one In another embodiment, the second switching device is set up such that the seventh electrical connection of the second switching device with the sixth electrical connection of the charge storage device is electrically coupled, and that the eighth electrical connection the second switching device with the source / drain terminal of Junction field effect transistor is electrically coupled.

According to one Another embodiment of the invention is the second switching device as an electrical switching device or as an electrical switch educated.

clear For example, the second switching device may be connected to the charge storage device be connected in series, and with the help of the second switching device can charge the storage device to the power supply device and (if the gate drive device for example, is electrically coupled to a JFET) too the gate-source route the JFETs are electrically connected in parallel.

An aspect of the invention can be seen in that by means of a second switching device (second switch) it can be achieved that, in the case of a JFET switch-on, the charge storage device (for example the capacitance C _stat ) can not be replaced by the parallel switching device. Device (switch) is discharged, but separated or disconnected by means of a capacitance C _stat serially arranged second switch. Thus, the charge amount stored by the charge storage device is maintained and does not have to be dynamically reloaded by the driver, which would make them more demanding in terms of dynamics. On the other hand, the driver performance is unaffected by this measure.

alternative can the charge storage device also in the power of the JFETs, i. with short-circuited power supply device, electrical be connected in parallel to the power supply device.

One Aspect of the invention can be seen in that by means of Gate drive device in the off case of a JFET a already charged to the level of breakdown voltage charge storage device (For example, a charged capacitor) parallel to the gate-source path of the JFET can be actively switched on, whereby the effective gate-source capacitance can be increased from the outside can, and the effect of the Miller effect on the switching state intercepted can be so that a secure passive switching is enabled.

In order to may be an unwanted reconnection of one or more transistors (Miller effect) in certain power electronic circuits (For example, DC link inverters, matrix inverters) and thus shorts be avoided in a power circle. The addition of a charged capacity to the gate-source line can be done immediately in the off-instant, so from this Time an unintentional switching is no longer possible, independently of when a second transistor switches and a reclosure case could cause.

One Another aspect of the invention can be seen in that Turning on a JFET by means of the gate drive means the charge storage device (For example, the capacitor) by means of a second, serially arranged Switch (i.e., the second switching device) are switched off again can and not over the first switch (i.e., the switching device) is discharged. Keep it the charge storage device (capacitor) their charge quantity and does not have to be dynamically reloaded by the driver. For the driver Thus, a lower dynamics or performance is required.

According to one Another embodiment of the invention comprises the gate drive device a switch driver to drive the first switching device and / or the second switching device.

According to one Another embodiment of the invention is the switching-drive device set up so that the switching device and the second switching device can be controlled that either the third electrical connection and the fourth electrical Connection of the switching device electrically conductive with each other or that the seventh electrical connection and the Eighth electrical connection of the second switching device electrically conductive with each other are connected.

clear can the switching device (first switch) and the second switching device (second switch) by means of a switching drive device be controlled so that either the first switch or the second switch is closed (or electrically conductive). With others Words can be achieved by means of the switching drive device be that just one of the two switches at a given time closed (electrically conductive), wherein by means of closing the first switch (or the switching device) at the same time Power supply device can be short-circuited and in addition, if the gate drive device with a junction field effect transistor is electrically coupled, and the gate-source path of the junction field effect transistor can be shorted.

The Driving the switching device and / or the second switching device can be done using a PWM control signal (PWM: Pulse Width Modulation).

One Another aspect of the invention can be seen in that dynamic support immediately while turning off a JFET using a PWM control signal Parallel branch to the power supply device (power source) can be unlocked, which briefly the entire, the Driver available for locking Apply voltage between the gate contact and the source contact of the JFET can. This can additionally to the static gate current of the constant current source a much higher dynamic Gate current component provided as quickly as possible to achieve Transhipment of parasitic capacities of the JFET and thus contributes to very short switching times.

In this connection, another aspect of the invention can be seen in that Ausschaltfall not only the statically impressed constant current and the parallel branch current (dynamic support, see above) cause a rapid transhipment of parasitic capacitances and associated shorter switching times, but that on the capacitor (the charge storage device) C _stat stored charge the The switching process is accelerated when C _{stat is} switched in parallel with the gate-source path of the JFET (for example, using a PWM signal).

According to one Another embodiment of the invention is the at least one junction field effect transistor the junction field effect transistor arrangement formed as a power junction field effect transistor.

According to one Another embodiment of the invention is in the method for driving a junction field effect transistor the electric power by means of a power supply device, for example, a current source or a constant current source provided.

According to one Another embodiment of the invention is the current-providing device in the second operating state of the junction field effect transistor shorted.

One Advantage of the invention can be seen in that to turn off of a JFET does not separately apply drive voltage to each one Transistor must be adjusted.

One Another advantage of the invention can be seen in the fact that no additional consuming measuring devices and / or control devices for the gate current are necessary.

One Another advantage of the invention can be seen in that a Unintentional reconnection of transistors (Miller effect) in certain power electronics circuits (such as DC link converters, Matrix inverters) can be safely avoided, and thus also short circuits in the power circuit safely avoided.

One Another advantage of the invention, especially compared to the in [13] can be seen that the circuit complexity is less, because to avoid the Miller effect or a bridge short circuit no further power source device is necessary for safe shutdown of the JFET increased Gate current leads.

One Another advantage of the invention can be seen in that the Gate drive device is very well suited for matrix converters or DC link converter, where multiple transistors as the cause of a passive switching action come into consideration and a complicated Kommutierungseinrichtung is present.

One Another advantage of the invention can be seen in that means the connection of a capacity to the gate-source line from this point on, no unintentional switching on of the JFET anymore is possible, independently of when a second transistor switches and a reclosure case would require.

A as capacity or capacitor formed charge storage device can at power of the JFET and the gate driver can be arranged so that (for example by means of the second Switching device) the capacity no over discharge the first switching device (or the first switch) becomes. This avoids that the capacity by means of the driver dynamically must be reloaded, so that a more favorable energy balance for the driver results.

One Another advantage of the invention can be seen in that the gate drive device a complex signal fusion and additional Potential separation points (for example in matrix converters) can be avoided.

One Another advantage of the invention can be seen in that a accelerated turn off of a JFET can be achieved by the charged charge storage device (for example, the charged charge storage device) Capacitor) a part of the charge on her (him) to Switching contributed, which part immediately thereafter by the current-providing device (for Example, the power source) is recharged.

The gate drive device or the method for driving a junction field effect transistor may be used for driving an n-channel junction field effect transistor (n-channel JFET) as an alternative to driving a p-channel junction field effect transistor (p-channel JFET). In this regard, it should be noted that both in driving an n-channel JFET and in driving a p-channel JFET, the gate-source path forms the control path, but to block a p-channel JFET, a positive gate is used. Source voltage (u _GS > 0) and thus a positive gate current (i _G > 0) is used.

embodiments The invention is illustrated in the figures and will be described below explained in more detail. In The figures are the same or similar Elements, where appropriate, with the same or identical reference numerals Mistake. The illustrations shown in the figures are schematic and therefore not to scale drawn.

It demonstrate

1A a cross-sectional view of a conventional junction field effect transistor;

1B an electrical schematic to that in 1A shown transistor;

2 a current-voltage diagram illustrating the dependence of a drain current and a gate current of a gate-source voltage in a junction field effect transistor;

3 an electrical circuit diagram;

4 a schematic diagram of a junction field effect transistor for representing parasitic capacitances;

5 a junction field effect transistor arrangement according to a first embodiment of the invention;

6 a junction field effect transistor arrangement according to a second embodiment of the invention;

7 a junction field effect transistor arrangement according to a third embodiment of the invention.

In the following, with regard to the invention underlying gate driver principle based on 3 First, the switching off of a junction field effect transistor (JFET) by means of impressing a static gate current explained in more detail.

3 shows an electrical circuit diagram 300 ' with an n-channel junction field effect transistor (n-channel JFET) 300 and one with the JFET 300 electrically coupled gate drive device 350 , The JFET 300 has a source connection 301 , a drain connection 302 and a gate terminal 303 on. The gate drive device 350 has a constant current source 351 on which constant current source 351 by means of a first electrical connection 351a with the gate connection 303 of the JFET 300 is electrically coupled, and which constant current source 351 further by means of a second electrical connection 351b with the source connection 301 of the JFET 300 is electrically coupled. The constant current source 351 provides a constant current i _G which is the gate 303 of the JFET is impressed statically.

Further, a switching device 352 (Switch S1) to the constant current source 351 electrically connected in parallel, wherein the switching device 352 by means of a third electrical connection 352a with the first electrical connection 351a the constant current source 351 is electrically coupled and wherein the switching device 352 further by means of a fourth electrical connection 352b with the second electrical connection 351b the constant current source 351 is electrically coupled.

The switching device 352 or the switch S1 is by means of a PWM control signal of a switching control device 353 controlled by closing the switch S1, the power source 351 can be shorted.

With the help of in 3 shown gate drive device 350 can JFET's control side pn range 300 Static in the breakthrough and thus the transistor 300 be forced to shut down by means of the constant current source 350 a constant gate current i _G (for example, i _G = -150 μA) into the gate path of the transistor 300 is impressed. In other words, by impressing a constant (negative) gate current, an operating point in the breakdown region of the transistor is set, in other words an operating point which, for example, on the steeply sloping branch of one of the three curves 202a . 202b . 202c However, the current intensity of the gate current i _G is set or limited so that a thermal damage to the transistor is avoided.

In this regard, it should be noted that to safely lock the JFET 300 that of the power source 351 available driver voltage u _TR smaller than the breakdown voltage u _{BR of} the JFETs 300 have to be.

For turning on the JFET 300 (u _GS > u _PI ), the gate-source path is short-circuited by means of the switch S1. The power source 350 This is also short-circuited, but unlike the use of voltage sources, this is an uncritical and allowed operating mode.

As already mentioned above, may be used in certain power electronic circuits (e.g., DC link power converters, Matrix inverter) the case that a switched-off, but backward conducting Transistor by an active switching action of another transistor goes into the forward lock state and thus its backward current commuted (passive switching). From the change of the voltage conditions between reverse conducting and forward blocking state results in a change in charge of the parasitic transistor capacitances.

If the JFET 300 For example, in one of the above-mentioned circuits, therefore, it may be clearly the case that although the JFET 300 is off, due to a switching operation of another transistor of the circuit of the JFET 300 (temporarily) turns on. This can lead to unwanted short circuits in the circuit.

4 shows that in the JFET 300 occurring parasitic capacitances (ie gate-source capacitance C _GS , drain-gate capacitance C _DG , drain-source capacitance C _DS ), in the JFET 300 flowing currents (i _G , i _D , i _GS , i _DG , i _DS ) and the voltages applied to the parasitic capacitances (u _GS , u _DG , u _DS ) The tables Tab. 1 and Tab. 2 show an exemplary assumption Gate-source voltage of u _GS = u _BR = -36 V and a blocking voltage of the transistor u _blocking = 600 V the voltages applied to the parasitic capacitances of the transistor for the reverse conducting state (Tab.1) and for the forward blocking state (Table 2). conducting backwards u _GS u _BR (eg -36 V) u _DS -U _{F diode} (eg -3 V) u _DG U _DS - u _GS (eg 33 V)

Table 1: Voltages at parasitic capacitances of the in 3 shown JFETs 300 in the reverse conducting state for u _GS = -36 V, u _blocking = 600 V. blocking forward u _GS u _BR (eg -36 V) u _DS u _lock (eg 600 V) u _DG u _DS - u _GS (eg 636 V)

Tab.2: Voltages at parasitic capacitances of the in 3 shown JFETs 300 in the forward blocking state for u _GS = -36 V, u _blocking = 600 V.

From Table 1 and Table 2 it can be seen that - regarding the gate-source path - the capacitance C _{DG has} to be reloaded by more than the amount of the off-state blocking voltage u _blocking (600 V). The voltage u _DG increases in the example shown from 33 V to 636 V, ie. around 603 V. This is the result of a displacement current i _DG (cf. 3 ), which inevitably flows through the capacitance C _GS . The current i _DG is usually transiently greater than the current i _G generated by the driver power source (power source 350 in 3 ) is entered in the opposite direction (eg i _G = -150 μA). This leads to the discharge of C _GS and thus to the increase of the gate-source voltage u _GS . The latter can quickly exceed the level of the pinch-off voltage u _{PI of} the Transis tors 300 grow out, leaving the transistor 300 turns on and causes a short circuit in the power circuit. When the transient charge has expired, the driver power source is charging 350 the capacitances C _GS and C _DG again such that the voltage u _{GS is} less than u _PI and statically assumes the value u _BR . The process of recovering the blocking capability of the transistor 300 However, it can take a few μs to cause unwanted losses in the power device during the short circuit phase and the JFET 300 can burden.

5 shows a junction field effect transistor arrangement 500 ' according to a first embodiment of the invention. The junction field effect transistor arrangement 500 ' has a gate driver 550 which is provided with a junction field effect transistor (JFET) 300 is electrically coupled. The junction field effect transistor 300 is as an n-channel junction field effect transistor 300 formed and has a source terminal 301 , a drain connection 302 and a gate terminal 303 on. The JFET 300 may for example be designed as a power JFET.

According to an alternative embodiment of the invention (not shown), the junction field effect transistor 300 be formed as a p-channel junction field effect transistor.

The gate drive device 550 has a power supply device configured as a constant-current electric power source 551 to provide an electric current i _G. The power supply device 551 has a first electrical connection 551a on, which with the gate connection 303 the junction field effect transistor 300 is electrically coupled, and a second electrical connection 551b , which with the source connection 301 the junction field effect transistor 300 is electrically coupled.

The gate drive device 550 also has an interface to the power providing device 551 Parallel switching device 552 (Switch S1) for selectively shorting the power supply device 551 , The switching device 552 has a third electrical connection 552a on, which with the first electrical connection 551a the power delivery facility 551 and with the gate connection 303 the junction field effect transistor 300 is electrically coupled. Furthermore, the switching device 552 a fourth electrical connection 552b on, which with the second electrical connection 551b the power delivery facility 551 and with the source connector 301 the junction field effect transistor 300 is electrically coupled.

The gate drive device 550 furthermore has a charge storage device designed as a capacitance C _stat 554 on which charge storage device 554 to the power supply device 551 electrically switchable in parallel. The charge storage device 554 has a fifth electrical connection 554a on. Further, the charge storage device has 554 a sixth electrical connection 554b on, which with the second electrical connection 551b the power supply device and with the source connection 301 the junction field effect transistor 300 is electrically coupled.

The gate drive device 550 also has a second switching device 555 (second switch S2) for selectively connecting the charge storage device in parallel 554 to the power providing facility 551 , The second switching device 555 has a seventh electrical connection 555a on, which with the first electrical connection 551a the power delivery facility 551 and with the gate connection 303 the junction field effect transistor 300 is electrically coupled. Furthermore, the second switching device 555 an eighth electrical connection 555b on, which with the fifth electrical connection 554a the charge storage device 554 is electrically coupled.

The first switching device 552 (or the switch S1) and the second electrical switching device 555 (or the second switch S2) are designed as electrical switches.

The gate drive device 550 further comprises a switching drive device 553 to drive the first switching device 552 and the second switching device 555 , The switch driver 553 is set up so that the switching device 552 and the second switching device 555 can be controlled so that either the third electrical connection 552a and the fourth electrical connection 552b the switching device 552 electrically connected to each other, or that the seventh electrical connection 555a and the eighth electrical connection 554b the second switching device 555 electrically conductively connected to each other.

In other words, with the aid of the switching drive device 553 the switching device 552 (Switch S1) and the second switching device 555 (second switch S2) are controlled so that only one of the two switches S1, S2 at the same time electrically conductive (illustratively: closed).

The driving of the switching device 552 and the second switching device 555 can be done using a PWM control signal.

The gate drive device 550 According to the illustrated embodiment of the invention differs from the in 3 shown gate drive device 350 essentially in that in the gate drive device 550 in the event of a break in the JFET 300 (ie, switch S1 opens) an already charged to the level of the breakdown voltage capacitance C _stat (charge storage device 554 ) parallel to the power source 551 and thus parallel to the gate-source path of the JFET 300 is switched (ie switch S2 closes). Compared to the gate-source capacitance C _GS of in 3 shown arrangement thus results in the in 5 shown arrangement an increased gate-source capacitance C _GS '= C _GS + C _stat . With increasing value of the capacitance C _stat , the shifted charge quantity leads to C _GS ', resulting from the transient drain gate current i _DG (cf. 4 ), To a decreasing voltage drop of the gate-source voltage u _GS and thus prevents possible short-term occurring short circuits.

Clearly, when you turn off the JFET 300 by simultaneously adding a charged capacitance C _stat (generally a charge storage device 554 ) are provided within a very short time additional electrical charge, which additional electrical charge for compensating a caused by a shift current i _DG charge outflow can be used so that the gate-source voltage u _GS does not _{break down} in the off case or not on the value of Pinch-off voltage u _{PI of} the JFET 300 increases. Clearly a passive switching support is thus created, which is a passive reconnection of the JFETs 300 safely prevented.

In the power-on case of the JFET 300 C _stat (ie the charge storage device 554 ) are not discharged by the parallel switch S1, but separated by means of connected to C _stat in series second switch S2. This keeps the amount of charge and does not have to be through the driver, ie the power supply device 551 be dynamically reloaded.

6 shows a junction field effect transistor arrangement 600 ' according to a second embodiment of the invention, wherein in 6 an exemplary circuit realization of the current source principle and the passive switching support principle is shown.

The junction field effect transistor arrangement 600 ' has a gate driver 650 which is provided with a junction field effect transistor (JFET) 300 is electrically coupled. The junction field effect transistor 300 is as an n-channel junction field effect transistor 300 formed and has a source terminal 301 , a drain connection 302 and a gate terminal 303 on. Alternatively, the junction field effect transistor 300 be formed as a p-channel junction field effect transistor. The JFET 300 may for example be designed as a power JFET.

The gate drive device 650 has a power supply device configured as a constant-current electric power source 651 to provide an electric current i _G. The power supply device 651 has a first electrical connection 651a on, which with the gate connection 303 the junction field effect transistor 300 is electrically coupled, and a second electrical connection 651b , which with the source connection 301 the junction field effect transistor 300 is electrically coupled.

The gate drive device 650 also has an interface to the power providing device 651 Parallel switching device 652 (Switch S1) for selectively shorting the power supply device 651 , The switching device 652 is designed as a p-channel MOSFET (p-MOSFET). The switching device 652 or the p-MOSFET 652 has a third electrical connection 652a (Drain terminal of the p-MOSFET 652 ) and a fourth electrical connection 652b (Source terminal of the p-MOSFET 652 ) on. The fourth electrical connection 652b is with the second electrical connection 651b the power delivery facility 651 electrically coupled. The p-MOSFET 652 further includes a first gate terminal 652c on.

The gate drive device 650 furthermore has a charge storage device designed as a capacitance C _stat 654 on which charge storage device 654 to the electricity provider averaging means 651 electrically switchable in parallel. The charge storage device 654 has a fifth electrical connection 654a and a sixth electrical connection 654b on.

The gate drive device 650 also has a second switching device 655 (second switch S2) for selectively connecting the charge storage device in parallel 654 to the power providing facility 651 , The second switching device 655 is designed as an n-channel MOSFET (n-MOSFET). The second switching device 655 or the n-MOSFET 655 has a seventh electrical connection 655a (Source terminal of n-MOSFET 655 ) as well as an eighth electrical connection 655b (Drain terminal of n-MOSFET 655). The seventh electrical connection 655a is with the second electrical connection 651b the power delivery facility 651 electrically coupled, and the eighth electrical connection 655b is with the sixth electrical connection 654b the charge storage device 654 electrically coupled. The n-MOSFET 655 also has a second gate terminal 655c on which second gate terminal 655c with the first gate connection 652c of the p-MOSFET 652 is electrically coupled.

According to the in 6 In the embodiment shown, the power supply device 651 the gate drive device 650 realized using a first electrical resistance R ₁ , a diode (Zener diode) D ₁ , a first bipolar transistor TR ₁ (npn transistor) and a second electrical resistance R ₂ . The first electrical resistor R ₁ has a ninth electrical connection 661 on which ninth electrical connection 661 with the source connection 301 of the JFET 300 is electrically coupled. Illustratively forms the ninth electrical connection 661 the second electrical connection 651b the power delivery facility 651 or power source 651 , The first electrical resistor R ₁ also has a tenth electrical connection 661b on. The diode D ₁ has an eleventh electrical connection 671a on, which with the tenth electrical connection 661b of the first electrical resistor R _{1 is} electrically coupled. Furthermore, the diode D _{1 has} a twelfth electrical connection 671b which is electrically coupled to a first low electrical supply potential GND _TR . The first bipolar transistor TR ₁ has a first base terminal 681a , a first collector connection 681b and a first emitter terminal 681c on, with the first base connector 681a with the eleventh electrical connection 671a the diode D _{1 is} electrically coupled, and wherein the first collector terminal 681b with the gate connection 303 of the JFET 300 is electrically coupled. The second electrical resistor R ₂ has a thirteenth electrical connection 662a and a fourteenth electrical connection 662b on, with the thirteenth electrical connection 662a with the first emitter terminal 681c of the first bipolar transistor TR _{1 is} electrically coupled, and wherein the fourteenth electrical connection 662b is electrically coupled to the first low electrical supply potential GND _TR .

The gate drive device 650 also has a third electrical resistance R ₃ which is connected between the charge storage device 654 and the gate terminal 303 the JFET is switched. The third electrical resistor R ₃ has a fifteenth electrical connection 663a and a sixteenth electrical connection 663b on, with the fifteenth electrical connection 663a with the fifth electrical connection 654a the charge storage device 654 is electrically coupled, and wherein the sixteenth electrical connection 663b with the gate connection 303 of the JFET 300 is electrically coupled.

The gate drive device 650 also has a fourth electrical resistance R ₄ which is connected between the switching device 652 and the gate terminal 303 the JFET is switched. The fourth electrical resistor R ₄ has a seventeenth electrical connection 664a and an eighteenth electrical connection 664b on, with the seventeenth electrical connection 664a with the third electric 652a the switching device 652 is electrically coupled, and wherein the eighteenth electrical connection 664b with the gate connection 303 of the JFET 300 is electrically coupled.

The gate drive device 650 also has a capacity 674 (Capacitance C ₁ ), which has a nineteenth electrical connection 674a and a twentieth electrical connection 674b wherein the nineteenth electrical connection 674a with the first gate connection 652c of the p-MOSFET 652 and with the second gate terminal 655c of the n-MOSFET 655 is electrically coupled.

The gate drive device 650 also has a fifth electrical resistance R ₅ , which has a twenty-first electrical connection 665a and a twenty-second electrical connection 665b having the twenty-first electrical connection 665a with the twentieth electrical connection 674b the capacity 674 is electrically coupled, and wherein the twenty-second electrical connection 665b is electrically coupled to the first low electrical supply potential GND _TR .

The gate drive device 650 further comprises a second bipolar transistor TR ₂ (npn transistor) having a second base terminal 682a , a second collector connection 682b and a second emitter terminal 682c has, wherein the second base terminal 682a with the twentieth electrical connection 674b the capacity 674 and electrically coupled, and wherein the second collector terminal 682b with the gate connection 303 of the JFET 300 ' is electrically coupled, and wherein the second emitter terminal 682c is electrically coupled to the first low electrical supply potential GND _TR .

The fourth electrical connection 652b the switching device 652 (Source terminal of the p-MOSFET S ₁ ), the eighth electrical connection 655a the second switching device 655 (Source terminal of the n-MOSFET S ₂ ) and the ninth electrical connection 661 of the first electrical resistor R ₁ are further electrically coupled to a first high electrical supply potential u _TR .

The gate drive device 650 further comprises a switching drive device 653 to drive the first switching device 652 and the second switching device 655 , The switch driver 653 is set up so that the switching device 652 and the second switching device 655 can be controlled so that either the third electrical connection 652a and the fourth electrical connection 652b the switching device 652 electrically connected to each other, or that the seventh electrical connection 655a and the eighth electrical connection 655b the second switching device 655 electrically conductively connected to each other.

In other words, with the aid of the switching drive device 653 the switching device 652 (Switch S ₁ ) and the second switching device 655 (second switch S2) are controlled so that only one of the two switches S1, S2 is electrically conductive at the same time.

The switch driver 653 has a first electrical output 653 and a second electrical output 653b on, with the first electrical output 653 with the first gate connection 652c of the p-MOSFET 652 and with the second gate terminal 655c of the n-MOSFET 655 is electrically coupled, and wherein the second electrical output 653b with the source connection 652b (fourth electrical connection 652b ) of the p-MOSFET 652 , with the source connection 655a (seventh electrical connection 655a ) of the n-MOSFET 655 and with the second electrical connection 651b the power delivery facility 651 is electrically coupled.

The following is the operation of the in 6 shown circuit 650 explained in more detail.

According to the in 6 In the embodiment shown, the power supply device 651 the gate drive device 650 realized as a constant current source with the components R ₁ (first electrical resistance) and D ₁ (Z-diode) and TR ₁ (first bipolar transistor) and R ₂ (second electrical resistance). While R ₁ limited in a first approximation only the current through the Zener diode D ₁ , the Z voltage across D ₁ together with the resistor R _{2 is} responsible for the collector current through TR ₁ and thus in the OFF case for the static gate current i _G.

In this context, it should be noted that instead of in 6 example shown power source 651 Any other power source can be used.

The capacity 674 , the fifth electrical resistance R ₅ and the second bipolar transistor TR ₂ are illustratively provided to provide an off-instantaneous view of the JFET 300 significantly higher gate current and dynamic recharging the charge storage device 654 (Capacity C _stat ).

As power supply to the gate driver 650 serve two potential-separated voltage sources, ie a first voltage source 610 with the voltage u _TR opposite GND _TR and a second voltage source 620 with the voltage u _SIG opposite GND _SIG . The first voltage source 610 feeds the power section of the driver circuit (TR), while the second voltage source 620 is used for signal processing (SIG).

The p-channel MOSFET S ₁ (first switching device 652 ) is connected to the n-channel MOSFET S ₂ (second switching device 655 ) by means of the gate connections 652c . 655c and by means of the source connections 652b . 655a connected. These two potentials are from a corresponding circuit in the operation of a cross switch 653 (ie, the switching drive device 653 ). The control signal of this circuit 653 corresponds to the isolated driver input signal.

By means of the cross-switching mode in conjunction with the different channel types of S ₁ and S _{2, it} can be achieved that only a single MOSFET (ie S ₁ or S ₂ ) is conductive while the other transistor is turned off.

When the driver circuit is first started up, the JFET is used to achieve a safe state in the converter circuit 300 locked, so that S _{1 is} turned off and S _{2 are} turned on. Thus, via S ₂ and the third electrical resistance R _3, the capacitance C _stat (charge storage device 654 ) to the value of the breakdown voltage of the source-gate path u _BR and from this point on can ensure the dynamic switch-off support.

To turn on the JFET 300 S ₁ and S _{2 can} be controlled so that S _{1 is} conductive and S ₂ blocking. Thus, the series connection of the source-gate path of the JFET 300 short-circuited to the fourth electrical resistance R ₄ . The resistor R ₄ has the function of a gate series resistor and can determine the dynamic switch-on behavior. In this state, the static current of the power source flows 651 via R ₄ and S ₁ . The charge of C _stat is retained.

To turn off the JFET 300 For example, S ₁ and S _{2 can} be controlled such that S _{1 is} blocking and S _{2 is} conducting. The third electrical resistor R ₃ serves to adapt the dynamic switch-off behavior, since C _stat remains charged even in the switch-on case and thus can provide the majority of the transient gate charging current when switched off.

The series connection of capacitance C ₁ and fifth electrical resistance R ₅ is voltage-wise between the gate terminals 652c . 655c from S ₁ and S ₂ as well as to GND _TR . The base-emitter path of the npn transistor TR ₁ is parallel to R ₅ . Changes due to an active switching action of the JFET 300 the gate potential of S ₁ and S ₂ , C _{1 is} forcibly reloaded and a transient current flows through R ₅ . This requires the switching on of the first bipolar transistor TR ₁ and thus a transient short-circuiting of the static current source. The current flowing through TR ₁ is also at the dynamic gate charging current of the JFET 300 and also serves to quickly reload C _stat , which has provided the immediate first gate charge portion. Thus, the gate driver with the capacitance C _{stat is} immediately able to respond to passive switching operations and the JFET 300 safely left in the off state.

7 shows a junction field effect transistor arrangement 700 ' according to a third embodiment of the invention. The junction field effect transistor arrangement 700 ' has a gate driver 750 which is provided with a junction field effect transistor (JFET) 300 is electrically coupled. The gate drive device 750 is different from the one in 5 shown gate drive device 550 in that in the gate drive means 750 no second switching device is formed, so that the charge storage device 554 to the power providing facility 551 is connected in parallel.

• [1] H. Mitlehner et al., "Ultra low loss and fast switching unipolar SiC-devices", PCIM 2002, Nürnberg, Deutschland, Mai 2002.
• [2] B. Ozpineci, L. M. Tolbert, S. K. Islam, M. Chinthavali, "Comparison of wide bandgap semiconductors for power applications", EPE 2003, Toulouse, Frankreich, September 2003.
• [3] M. Bakowski, "Status and prospects of SiC power devices", IPEC 2005, Niigata, Japan, April 2005.
• [4] P. Friedrichs et al., "The vertical silicon carbide JFET – a fast and low loss solid state power switching device", EPE 2001, Graz, Österreich, August 2001.
• [5] B. Allebrand, H.-P. Nee, "Design of a gate drive circuit for use with SiC JFET's", Nordic workshop an power and industrial electronics NORPIE 2002, Stockholm, Schweden, August 2002.
• [6] C. Rebbereh, H. Schierling, M. Braun, "First inverter using silicon carbide power switches only", EPE 2003, Toulouse, Frankreich, September 2003.
• [7] A. Orellana, B. Piepenbreier, "Fast gate drive for SiC-JFET using a conventional driver for MOSFETs and additional protections. IECON 2004, Busan, Korea, November 2004.
• [8] I. Koch, F. Hinrichsen, W.-R. Canders, "Application of SiC-JFETs in current source inverter topologies", EPE 2005, Dresden, Deutschland, September 2005.
• [9] I. W. Hofsajer, A. Melkonyan, M. Mantel, S. Round, J. W. Kolar, "A simple, low cost gate drive method for practical use of SiC JFETs in SMPS, EPE 2005, Dresden, Deutschland, September 2005.
• [10] K. Mino, S. Herold, J. W. Kolar, "A gate drive circuit for silicon carbide JFET", IECON 2003, Roanoke, Virginia, USA, November 2003.
• [11] M. L. Heldwein, J. W. Kolar, "A novel SiC J-FET gate drive circuit for sparse matrix converter applications", APEC 2004, Anaheim, Californien, USA, Februar 2004.
• [12] DE 102 12 863 A1
• [13] DE 102 12 869 A1
• [14] M. Ziegler, "Untersuchungen zur gestaffelten Kommutierung in Matrixumrichtern mit Pulsweitenmodulation", Fortschritt-Berichte VDI, Reihe 21, Nr. 352, Düsseldorf, VDI Verlag 2003.
• [15] DE 101 43 432 C1
• [16] US 2002/0190779 A1

This document cites the following publications:

• [1] H. Mitlehner et al., "Ultra low loss and fast switching unipolar SiC devices", PCIM 2002, Nuremberg, Germany, May 2002.
• [2] B. Ozpineci, LM Tolbert, SK Islam, M. Chinthavali, "Comparison of wide bandgap semiconductors for power applications", EPE 2003, Toulouse, France, September 2003.
• [3] M. Bakowski, "Status and prospects of SiC power devices", IPEC 2005, Niigata, Japan, April 2005.
• [4] P. Friedrichs et al., "The vertical silicon carbide JFET - a fast and low loss solid state power switching device", EPE 2001, Graz, Austria, August 2001.
• [5] B. Allebrand, H.-P. Nee, "Design of a gate drive circuit for use with SiC JFETs", Nordic workshop on power and industrial electronics NORPIE 2002, Stockholm, Sweden, August 2002.
• [6] C. Rebbereh, H. Schierling, M. Braun, First inverter using silicon carbide power switches only, EPE 2003, Toulouse, France, September 2003.
• [7] A. Orellana, B. Piepenbreier, "Fast gate drive for SiC-JFET using a conventional driver for MOSFETs and additional protections." IECON 2004, Busan, Korea, November 2004.
• [8] I. Koch, F. Hinrichsen, W.-R. Canders, "Application of SiC JFETs in Current Source Inverter Topologies", EPE 2005, Dresden, Germany, September 2005.
• [9] IW Hofsajer, A. Melkonyan, M. Mantel, S. Round, JW Kolar, "A simple, low cost gate drive method for practical use of SiC JFETs in SMPS, EPE 2005, Dresden, Germany, September 2005.
• [10] K. Mino, S. Herold, JW Kolar, "A gate drive circuit for silicon carbide JFET", IECON 2003, Roanoke, Virginia, USA, November 2003.
• [11] ML Heldwein, JW Kolar, "A novel SiC J-FET gate drive circuit for sparse matrix converter applications", APEC 2004, Anaheim, California, USA, February 2004.
• [12] DE 102 12 863 A1
• [13] DE 102 12 869 A1
• [14] M. Ziegler, "Studies on staggered commutation in matrix converters with pulse width modulation", Progress Reports VDI, Series 21, No. 352, Dusseldorf, VDI Verlag 2003.
• [15] DE 101 43 432 C1
• [16] US 2002/0190779 A1

Claims (20)

JFET arrangement, With • at least a junction field effect transistor; At least one gate drive device, which has: - one Electricity supply device for providing an electrical stream - one Switching device for selectively short-circuiting the current-providing device, and - one Charge storage device connected to the power supply device electrically switchable or connected in parallel; • where the Power supply device with at least one gate connection and at least one source / drain terminal of the at least one Blocking field effect transistor is electrically coupled, in such a way that provided by the power providing device electrical current at least partially into a control-side pn junction between the gate terminal and the source / drain terminal of the junction field effect transistor imprinted can be. A junction field effect transistor arrangement according to claim 1, wherein the current-providing device as an electrical power source is trained. A junction field effect transistor arrangement according to claim 2, wherein the electric current source as electric) constant current source is trained. A junction field effect transistor arrangement according to a the claims 1 to 3, wherein the charge storage device at least one capacity having. A junction field effect transistor arrangement according to claim 4, wherein the charge storage device consists of a capacitor. A junction field effect transistor arrangement according to a the claims 1 to 5, wherein the switching device as an electrical switching device is trained. A junction field effect transistor arrangement according to a the claims 1 to 6, wherein the power supply device has a first electrical Having connection, which with the gate terminal of the junction field effect transistor is electrically coupled, and wherein the power supply device having a second electrical terminal connected to the source / drain terminal of the junction field effect transistor is electrically coupled. A junction field effect transistor arrangement according to a the claims 1-7, wherein the switching device to the power supply device electrically connected in parallel. A junction field effect transistor arrangement according to claim 8, wherein the switching device has a third electrical connection which is connected to the gate terminal is electrically coupled, and wherein the switching device has a fourth electrical Terminal which is electrically connected to the source / drain terminal is coupled. A junction field effect transistor arrangement according to a the claims 1 to 9, wherein the charge storage device has a fifth electrical Has terminal which can be electrically coupled to the gate terminal and wherein the charge storage device has a sixth electrical connection, which is electrically coupled to the source / drain terminal. A junction field effect transistor arrangement according to claim 10, with a second switching device for optional parallel connection the charge storage device to the power supply device. A junction field effect transistor arrangement according to claim 11, wherein the second switching device to the charge storage device electrically connected in series. A junction field effect transistor arrangement according to claim 12, wherein the second switching device has a seventh electrical Connection and an eighth electrical connection, wherein either • of the seventh electrical connection to the gate terminal of the junction field effect transistor is electrically coupled and the eighth electrical connection with the fifth electrical connection of the charge storage device is electrically coupled, or • of the seventh electrical connection with the sixth electrical connection the charge storage device is electrically coupled and the eighth electrical connection to the source / drain terminal of the junction field effect transistor is electrically coupled. A junction field effect transistor arrangement according to a the claims 11 to 13, wherein the second switching device as an electrical switching device is trained. A junction field effect transistor arrangement according to a the claims 1 to 14, with a switching drive means for driving the first Switching device and / or the second switching device. A junction field effect transistor arrangement according to claim 15, wherein the switching drive means is arranged that the switching device and the second switching device so can be controlled that either the third electrical connection and the fourth electrical Connection of the switching device electrically conductive with each other or that the seventh electrical connection and the Eighth electrical connection of the second switching device electrically are conductively connected to each other. A junction field effect transistor arrangement according to a the claims 1 to 16, wherein the at least one junction field effect transistor as a power junction field effect transistor is trained. Method for driving a junction field-effect transistor, in which • in a first operating state of the junction field effect transistor is an electrical Current is provided to the junction field effect transistor, such that the junction field effect transistor is in the breakdown region is operated; and • in a second operating state of the junction field effect transistor electric charge is cached, wherein at least a portion of the cached electric charge in the first operating state of the junction field effect transistor provided. Method according to claim 18, wherein the electric current by means of a current-providing device provided. Method according to claim 19, wherein the power supply device in the second operating state of the junction field effect transistor shorted.