DE102006025028B4 - Output power stage current monitoring circuitry and method of operating output power stage current monitoring circuitry - Google Patents

Abstract

Output power stage current monitoring circuitry with
An output transistor (T),
A switching terminal for applying a switching voltage to the output transistor;
A monitor chain (M) having at least two monitor transistors in parallel with the output transistor (T) for outputting a control variable,
- A reference chain (R) with at least two reference transistors (R1, ... R (n-1)), wherein the switching voltage (Vs) in addition to the gate terminals of the reference transistors (R1, ... R (n-1)) applied is for passing a reference current (Ir) through the reference transistors (R1, ..., R (n-1)) and
- a comparator (K) to which a second node (b) at the input of the reference chain (R) and a first node (a) for tapping the control variables are connected, wherein the comparator (K) depending on a ratio of the reference current (Ir) to the monitor current (Im) in the monitor chain (M) as the control quantity outputs a control signal (s),
characterized in that
A diode circuit with a diode (D1) or a transistor circuit with diode configuration between the reference chain ...

Description

The This invention relates to output power stage current monitoring circuitry with the above-conceptual features according to claim 1 or on a method of operating such output power stage current monitoring circuitry.

To the Measuring currents in output power stage current monitoring circuitry based on MOS (Metal Oxide Semiconductor / Metal Oxide Semiconductor) becomes a voltage drop between drain and source of an output transistor measured and compared with a reference size. To compare a comparator is used whose input is opposite one potential Voltage drop between drain and source are fully protected must, because in such a case, the gate breakdown voltage exceeded would become.

A Shielding is achieved by a combination of high resistance and Zener diode, as disclosed in P. Morrow, E. Gaalaas, O. McCarthy, "A 20-W Stereo Class-D Audio Output Power Stage in 0.6-μm BCDMOS Technologies ", IEEE JSSC, Vol. 39, no. Nov. 11, 2004, pp. 1948-1958, is known.

In addition, the implementation of shielding using pure MOS interconnects is known from M. Berkout, "Integrated Overcurrent Protection System for Class-D Audio Power Amplifiers", IEEE JSSC, Vol. 11, Nov. 2005, pp. 2237-2245. Such an exemplary circuit arrangement is based on 2 outlined. At a switching connection 1 , which is connected to a node d, a switching voltage Vs for switching an output transistor T can be applied. The output transistor T is connected between an output current terminal connected to another node c and a base voltage VSS. At the output power terminal is to be switched to an external low-impedance load, via the output transistor T a current Io to be switched flows when the switching voltage Vs is applied to a gate terminal of the output transistor T. Between the further node c and the base voltage VSS is also a monitor chain M of a first and a second monitor transistor M1, M2 connected. The monitor chain M, which is connected in parallel to the output transistor T, serves to output a control variable in the form of a monitored monitor current Im. The first of the two monitor transistors M2, whose drain terminal is applied directly to the further node c, is likewise switched by the switching voltage Vs which can be applied to its gate connection connected. The second monitor transistor M1 is switched over a constant voltage so that it is permanently open. As a result, a monitor voltage Vs1 which can be tapped off between the two monitor transistors M1, M2 can not go into the floating state. In addition, in addition to the gate terminals of the output transistor T and the first monitor transistor M2, a gate terminal of a first reference transistor R (n-1) is connected to the node d. This first reference transistor R (n-1) is a first transistor of a reference string R of a plurality of reference transistors (R1, ..., R (n-1)). This reference chain R is connected between a current or voltage source for applying a reference current Ir and the base voltage VSS. The gate terminals of all reference transistors R1, R (n-1) are all connected to node d, which is at the switch terminal 1 and the gate terminals of the output transistor T and the first monitor transistor M2 is applied. At the drain terminal of the first reference transistor R (n-1), ie between the reference chain R and the source for the reference current Ir, a tap or further node b is connected, which serves as a second connection point for tapping a reference voltage and also an input of a comparator circuit for evaluating the monitor voltage Vs1 can be applied.

A based on the principle set out above circuitry is, for example, from the WO 03/098804 A2 known, wherein the monitor chain M and the output transistor T coincide in this example.

The However, the circuit arrangement described above has disadvantages. there while the length of time while which the output transistor T is turned off, the voltage at the second node b for picking up the monitor voltage Vs1 increases, until the reference current Ir is turned off. As a result, must the whole circuit will be completely reloaded when switching on, allowing a restart of the power monitoring circuitry only takes place slowly. Another disadvantage is that while the length of time while which the output transistor T is turned off, the node a for providing the monitor voltage Vs1 to the floating state, which causes problems in the required determination circuit for determining the voltages at the two monitor voltage nodes a, b prepare can. Another disadvantage is in such a circuit arrangement in that while the power-on a review of the to be tested Electricity not possible is and a short circuit in the circuit with the low-impedance load delayed after the complete Turning on the power monitoring circuitry is detectable.

The object of the invention is to improve such an output power stage current monitoring circuitry such that a more stable operation is enabled and preferably a faster complete turn-on of this circuitry is enabled. In particular, a current monitoring should already be enabled as early as possible during the switching on of the circuit arrangement.

These The object is achieved by an output power stage current monitoring circuit with the features according to claim 1 or by a method of operating output power stage current monitoring circuitry with the features according to claim 7 solved. Advantageous embodiments are the subject of dependent claims.

Prefers is accordingly an output power stage current monitoring circuit with an output transistor, with a switching connection for application a switching voltage to the output transistor, with a monitor chain with at least two monitor transistors in parallel with the output transistor to output a control size and with a reference chain having at least two reference transistors, wherein the switching voltage in addition is applied to one of the reference transistors for conducting a Reference current through the reference transistors. Becomes advantageous This circuit arrangement characterized in that a diode circuit with a Diode or a transistor circuit with diode configuration between the reference chain and the switching connection are connected in such a way, that the reference current is not switched off. The reference transistors are connected between an operating voltage and a base voltage and the gate connections all of the reference transistors are preferred for switching means the switching voltage switched. A monitored monitor stream in the monitor chain serves as the control size.

One second node is at the entrance of the reference chain and a first node for tapping the control variables applied to a comparator to a control signal depending on a relationship of To output reference current to monitor current as the control quantity.

Preferred according to the method is accordingly Furthermore a method of operating such output power stage current monitoring circuitry, in which a first node for tapping a control variable during a turned off state of the monitor chain to a base voltage is placed and / or a second node for tapping a reference current is limited with respect to a voltage there by a bypass reference current to the switching connection.

The Diode prevents in connection with the input or reference chain, that the reference current is switched off, in particular completely switched off becomes. As a result, the circuit arrangement does not have to be switched on be completely reloaded, so that switching on can be faster. Another particular advantage is that even during the Power on a test to be monitored Electricity possible is, with even a short circuit during power-up could be detected. A dynamic shielding of the current monitoring circuitry allows a surveillance the output current state very fast and preferably under all potential Initial state conditions.

The Diode is preferably between a source terminal of one of the switching voltage switched reference transistors and at least a gate of one of these reference transistors connected.

The gates at least two, in particular all of the monitor transistors are preferably switched for switching by means of the switching voltage. In the monitor chain, a first of the monitor transistors is preferred between an output power terminal and a first node for tapping the control size switched is and the switching transistor is preferably between the output power terminal and a base voltage switched.

One Another transistor is preferably between a first node to Tapping the control size and a Base voltage switched and an inverter circuit is preferred between the switching voltage and a gate terminal of the other Transistor switched to suppress floating of the first node.

One embodiment will be explained in more detail with reference to the drawing. Show it:

1 a preferred output power stage current monitoring circuitry and

2 a circuit arrangement according to the prior art.

1 FIG. 10 shows exemplary output power stage monitoring circuitry for monitoring an output current Io from an external low-impedance load. The output current Io is applied to an output current connection or to a third node c connected thereto. For monitoring the output current Io serve control variables, which at a first and a second node a, b tapped the. The control variables may in particular be a monitored monitor current Im and a reference current Ir, which are tapped off at the first and the second node a, b.

Of the Monitor current Im and the reference current Ir are preferably inputs of a Comparator K created. A status signal or control signal s is the comparator K depending from the relationship of the monitor current Im and the reference current Ir output to each other. Preferably, the control signal s is then in the high state switched when the monitored Monitor current Im is smaller than the reference current Ir.

Whether the output current Io flows through the circuit depends on the switching state of an output transistor T. The output transistor T is connected between the third node c and a base voltage VSS. In this case, the drain terminal of the output transistor T is applied to the third node c. A gate of the output transistor T is at a switching terminal 1 for applying a switching voltage Vs applied. The switching connection 1 at the same time forms a fourth node or is associated with such a fourth node d.

At the fourth node d are also gate terminals one Variety of monitor transistors M1, ..., M (n-1), Mn applied. this will make them Monitor transistors M1-Mn, which form a monitor chain M, simultaneously with the output transistor T on and off. A first of the monitor transistors Mn is between the third node c and the first node a switched, wherein the source terminal is applied to the first node a. The other monitor transistors M (n-1), ... M1 are connected in series between the first node a and the base voltage VSS switched. By the monitor chain M flows in the switched state the supervised Monitor current Im. The monitor chain M is thus parallel to the output transistor T switched.

Gate terminals of a plurality of input and reference transistors R1,..., R (n-1), which form a reference string R, are also connected to the fourth node d. The reference chain R is connected between the second node b and the base voltage VSS. The one from a voltage source or power source 3 Applied reference current Ir is applied to the second node b, so that the reference current Ir in the on state of the reference transistors R1-R (n-1) flows through them, preferably without loss of resistance. In the on state, ie applied switching voltage Vs thus the transistors of the reference chain R are turned on together with the output transistor T and the transistors of the monitor chain M.

Optionally is between the power source 3 and the second node b, which is connected to the drain terminal of the first reference transistor R (n-1), a further circuit arrangement of a transistor Rn connected. The further transistor is thus between the power source 3 or an operating voltage VDD on the one hand and on the other hand via the reference chain R, the base voltage VSS connected. This further transistor Rn is switched by an applied voltage Vein less than an operating voltage VDD. This further transistor Rn is advantageous, but not mandatory in particular for circuit arrangements and switching states of a first approximation.

Regarding the Terms of operating voltage and base voltage should be noted that the sketched circuit arrangement in principle as a component of a parent Circuit arrangement can be used and the operating voltage VDD and the base voltage VSS thus not necessarily absolute voltage values but may also represent relative voltage values View of the parent Form circuit arrangement.

Next the most preferred drive both the output transistor T and the transistors of the reference chain R and the monitor chain M over the switching voltage Vs by a common switching of the gate terminals to the fourth Node d as a particularly advantageous feature of the circuit arrangement has this circuit as a further feature of independently advantageous Meaning a diode circuit with a diode D1.

The Diode D1 is between the second node b and the fourth node d, thereby preventing the reference current Ir Completely can be turned off. This causes in an advantageous manner, when switching on the circuit arrangement by applying the Switching voltage Vs the circuitry is not completely reloaded must become.

One further admitted Advantageous aspect of the circuit arrangement is an inverter circuit, which, for example, an inverter INV and yet another Transistor Ts is formed. The still further transistor Ts is connected between the first node a and the base voltage VSS. The inverter INV is between the fourth node d and a gate terminal the still further transistor Ts connected. This provides the functional Advantage that the first node a not uncontrolled in a floating Condition can occur.

In such an output power stage current monitoring circuit, the reference circuit having the reference string R becomes thus in the same way as the monitor path is switched to the monitor chain M. Assuming an inductive load applied to the third node c, an output current Io applied there can be regarded as constant during a turn-on process of the output transistor T and the monitor transistors M1-Mn. Since the charge states at the third node c and at the output of the power source 3 or at the second node b are different and can not be made equal, parasitic capacitances at the first and second nodes a, b are charged differently. As a result, even a small current flow through the further monitor transistors M (n-1) -M1 connected downstream of the first monitor transistor Mn, as forced by an inductive load, can cause the voltage at the first node a to be higher than the voltage at the second node b. This would lead to a wrong output value during the switching operation. In addition, during the off state, the first node a would be in the floating state while the voltages at the second node b and at the output of the current source 3 or at the input of the further transistor Rn increases until the reference current Ir of the power source 3 would be turned off. These two mechanisms cause problems during the power up cycle.

To avoid these problems, the first node a is grounded or connected to the base voltage VSS, while the transistors of the monitor chain M are turned off. In addition, the voltage at the second node b is limited by the fact that a bypass reference current flows into or through the diode D1. This prevents the power source 3 or whose reference current Ir leaves its operating point, which would slow down the reference circuit from the input chain R. The diode D1 can be equivalently converted by another suitable matching transistor circuit in a diode configuration.

By The addition These components must be the output of the circuit during a Switching cycle can not be hidden, as with other Applications is required. Accordingly, already during the Be turned on, if the output current Io much too is high, which is the case for example in the case of a short circuit is, so that the switch-on process are interrupted immediately can. This reduces the risk of damage to the circuit arrangement and a parent Circuit due to an error condition.

Claims (7)

Output power stage current monitoring circuit comprising - an output transistor (T), - a switching terminal ( 1 , d) for applying a switching voltage (Vs) to the output transistor (T), - a monitor chain (M) with at least two monitor transistors in parallel with the output transistor (T) for outputting a control variable, - a reference chain (R) with at least two reference transistors (R1 , ... R (n-1)), wherein the switching voltage (Vs) in addition to the gate terminals of the reference transistors (R1, ... R (n-1)) is applied to conduct a reference current (Ir) through the reference transistors ( R1, ..., R (n-1)) and - a comparator (K) to which a second node (b) at the input of the reference chain (R) and a first node (a) are connected for tapping the control variables, the comparator (K) outputs a control signal (s) as the control variable depending on a ratio of the reference current (Ir) to the monitor current (Im) in the monitor chain (M), characterized in that - a diode circuit having a diode (D1) or a diode circuit Transistor circuit with diode configuration zwisc hen the reference chain (R) and the switch connection ( 1 , d) is switched such that the reference current (Ir) is not turned off. Circuit arrangement according to Claim 1, in which the diode (D1) between a source terminal of one of the switching voltage (Vs) switched reference transistors (R (n-1)) and at least one gate terminal of one of these reference transistors (R (n-1)) is switched. Circuit arrangement according to any preceding claim with a supervised Monitor current (Im) as the control size. Circuit arrangement according to any preceding claim, at which gate connections at least two, in particular all of the monitor transistors (M1-Mn) for Switching means of the switching voltage (Vs) are connected. Circuit arrangement according to any preceding claim, in which in the monitor chain (M) a first of the monitor transistors (Mn) between an output power terminal (c) and a first one Node (a) for tapping the control variable (Im) is connected and the switching transistor (T) between the output power connection (c) and a base voltage (VSS) is connected. Circuit arrangement according to any preceding claim, in which a further transistor (Ts) is connected between a first node (a) for picking up the control variable and a base voltage (VSS) and in which an inverter circuit (INV) interposes the switching voltage (Vs) and a gate connection the further transistor (Ts) is connected to suppress a floating of the first node (a). A method of operating output power stage current monitoring circuitry according to any preceding claim, in which - a first Node (a) for picking up a control variable during an off Condition of the monitor chain (M) to a base voltage (VSS) will and / or - one second node (b) for picking up a reference current (Ir) with respect to a local voltage is limited by a bypass reference current to Switching connection (d).