DE102005055302B4 - Multi-bit memory element having a trench structure and method of manufacturing a multi-bit memory element having a trench structure - Google Patents

Abstract

A multi-bit memory element (500) having a trench structure (501), comprising: • an electrically conductive region (502); • an electrically insulating region (503) formed on the electrically conductive region (502); A first floating gate region (504a) formed in the electrically insulating region (503), the first floating gate region (504a) being formed at least partially over a first side surface (502a) of the electrically conductive region (502); A second floating gate region (504b) formed in the electrically insulating region (503), which second floating gate region (504b) lies at least partially over a second side surface (502b) of the first side surface (502a) electrically conductive region (502) is formed; • a third floating gate region (514a) formed in the electrically insulating region (503), the third floating gate region (514a) being formed at least partially over the first side surface (502a) of the electrically conductive region (502); A fourth floating gate region (514b) formed in the electrically insulating region (503), which fourth floating gate region (514b) is formed at least partially over the second side surface (502b) of the electrically conductive region (502), wherein, with respect to a vertical axis (170) of the trench structure (501): • the first floating gate region (504a) is formed over the third floating gate region (514a); The second floating gate region (504b) is formed over the fourth floating gate region (514b); and wherein • the floating gate regions (504a, 504b, 514a, 514b) are electrically isolated from each other and from the electrically conductive region (502) by the electrically insulating region (503).

Description

The invention relates to a multi-bit memory element with a trench structure and to a method for producing a multi-bit memory element having a trench structure.

An important branch of semiconductor technology is the development of memory cells (memory cells), i. H. Elements for storing data, usually in the form of binary information units, i. e. Bits (binary digits). In this context, writing (program) of a memory cell means that a data (eg, a bit) is "written" into the cell, i. H. is stored. Furthermore, reading (read) or erase (erase) of a memory cell means that the content of the memory cell, i. e. the stored information is read out or deleted. Furthermore, a read / write operation is also referred to as a cycle, and the time between the start of a read / write operation and the beginning of another read / write operation is called a cycle time. designated.

An important goal in the development of memory elements is the development and improvement of so-called non-volatile memory cells (NVM cells), d. H. Memory elements in which a state stored by once programming / writing the cell is maintained over a long period of time (typically ≥ 10 years) without requiring a regular refresh of the cell contents, i. H. rewriting with the same information is necessary.

Examples of non-volatile memory technologies include Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable ROM (EEPROM), or Flash memory.

In a typical form of NVM cells, the representation of a bit is realized by influencing the state of charge of this gate on an additional electrically insulated gate of a field-effect transistor (FET) by introducing positive charge carriers or negative charge carriers. The additional gate is called an electrically floating gate or floating gate.

The floating gate of a memory cell transistor may, for. B. in a loaded state or in an unloaded state. Depending on the charge state of the floating gate, the field effect transistor has a higher or lower threshold voltage, which is detected in a read process and can be used, for example, to distinguish between two binary states ("0" and "1") , In other words, for example, the state in which a memory cell FET has a low threshold voltage can be identified with a logical "1" stored in the memory cell. Conversely, a higher threshold voltage of the FET then corresponds to a logical "0" stored in the memory cell.

Conventional NVM cells based on floating gate technology can only store one bit per cell. Increasing the number of stored bits per cell is desirable.

An alternative concept for using floating gates is to use so-called charge trapping layers (charge traps). In this case, the charges are collected on, for example, a nitride layer within an oxide-nitride-oxide (ONO) stack.

Currently, using ONO storage layers, NVM cells can be realized which NVM cells can store one or two bits. In the latter case, one also speaks of double-bit memory cells or twin-bit memory cells (eg Twin-Flash). In general, memory cells that can store multiple bits are also referred to as multi-bit memory cells.

A disadvantage of using ONO layers is that during a programming or erasing process so-called hot electrons (hot electrons) or hot holes (hot holes), d. H. Electron or hole electrons with high kinetic energy are usually never introduced or injected exactly at the same point of the nitride layer. Consequently, the charge distribution in the nitride layer may widen and / or shift during a read / write cycle of the cell.

When using a floating gate made of metallic material such. B. polysilicon, however, the exact location of the charge carrier injection plays no decisive role, since the charges can move freely on the metallic floating gate. Therefore, the problem of broadening or shifting the charge distribution does not occur in this case.

As in other areas of semiconductor technology as well, the further development of the memory cells is largely determined by the Technology Nodes specified in the International Technology Roadmap for Semiconductors (ITRS), and the associated requirement of continuous miniaturization.

A major challenge in this context is the development of memory cell arrays with high density cell arrays, ie, maximum information stored per area, while at the same time minimizing the feature size (F) of memory toes should be possible.

In concrete terms, "as small as possible" means that, as part of the development of double-bit NVM cell transistors, feature sizes of F ≈ 60 nm are currently being sought. In particular, the separation of the two bits (two bit separation) and the retention of the data (retention) after a cycle represent major challenges in the development of high-density memory cell arrays.

Conventional memory cell transistors are designed as planar transistors. A disadvantage of planar transistors is that the channel length of the transistor must scale with the feature size F. However, with the miniaturization of the components accordingly shorter and shorter channels have problems, which are caused by the occurring during programming or deleting the cell high voltages.

One way to avoid the problem of extremely short channel lengths is to use so-called trench transistors or trench transistors, which have a U-shaped channel (so-called UMEM cells). In this case, the channel length does not have to scale with F.

In US Pat. No. 6,798,013 B2 discloses a double-bit flash memory cell having a vertically integrated transistor with a U-shaped trench structure and two floating gates formed on opposite sidewalls of the trench structure.

In US Pat. No. 6,762,955 B2 there is disclosed a memory cell transistor having a trench structure and two floating gates formed on opposite sidewalls of the trench structure.

The invention is based on the problem of specifying a non-volatile memory element or an NVM memory cell for storing four bits, which has good scalability and at least partially reduces or circumvents the above-mentioned disadvantages of memory cells known from the prior art.

The problem is solved by a multi-bit memory element with a trench structure and a method for producing a multi-bit memory element with a trench structure with the features according to the independent patent claims.

Exemplary embodiments of the invention will become apparent from the dependent claims. The further embodiments of the invention, which are described in connection with the multi-bit memory element, apply mutatis mutandis to the method for producing the multi-bit memory element.

A multi-bit memory element having a trench structure is provided which has an electrically conductive region and an electrically insulating region formed on the electrically conductive region. Furthermore, the trench structure has four floating gate regions formed on or in the electrically insulating region, which floating gate regions are electrically insulated from one another and from the electrically conductive region by the electrically insulating region.

In a method of manufacturing a multi-bit memory element having a trench structure, a trench is formed in a substrate. An electrically conductive region is formed in the trench. An electrically insulating region is formed on the electrically conductive region. Furthermore, four floating gate regions are formed on or in the electrically insulating region, such that the at least two floating gate regions are electrically insulated from one another and from the electrically conductive region by the electrically insulating region.

One aspect of the invention can be seen by providing a multi-bit memory cell or a multi-bit memory cell having a trench structure and four floating gate regions or floating gates.

The multi-bit memory element may be for use as a memory cell transistor, wherein four bits may be simultaneously stored in the multi-bit memory element using the four floating gate regions. More specifically, the multi-bit memory element can be used as an NVM cell transistor (non-volatile memory cell transistor), i. H. as a nonvolatile memory cell transistor.

An advantage of using a trench structure is that the channel length of a multi-bit memory element configured as a memory cell transistor does not have to scale with the feature size. In other words, if a memory cell transistor is reduced by a scaling factor f, the channel length does not necessarily have to be reduced by a factor of f. This avoids problems associated with very short channel lengths and high programming or erase voltages. Another advantage is that four bits per memory cell transistor can be stored.

In one embodiment of the invention, the electrically insulating region of a multi-bit memory element has a plurality of electrically insulating partial regions.

The electrically insulating region or the electrically insulating subregions can be formed by means of a deposition method and / or a growth method and / or an oxidation method. As the deposition method, a vapor deposition method such as Chemical Vapor Deposition (CVD) may be used.

According to another embodiment, the trench structure may have a U-shaped structure with a curved lower portion.

In another embodiment, for example, for a feature size of 60 nm, the trench structure of the multi-bit memory element along a horizontal axis, which horizontal axis is perpendicular to the first side wall and the second side wall of the electrically conductive region, a maximum extent of 60 nm ± 5 nm.

In another embodiment, for example for a feature size of 60 nm, the trench structure has an extension of 160 nm ± 10 nm along a vertical axis, which vertical axis is perpendicular to the horizontal axis.

In another embodiment, for example for a feature size of 60 nm, an electrically insulating edge region is formed in the electrically insulating region, the electrically insulating edge region having a thickness of 6 nm ± 1 nm.

The multi-bit memory element comprises: a first floating gate region formed in the electrically insulating region, the first floating gate region being formed at least partially over the first side surface of the electrically conductive region; a second floating gate region formed in the electrically insulating region, the second floating gate region being formed at least partially over the second side surface opposite to the first side surface of the electrically conductive region; a third floating gate region formed in the electrically insulating region, the third floating gate region being formed at least partially over the first side surface of the electrically conductive region; and a fourth floating gate region formed in the electrically insulating region, the fourth floating gate region being formed at least partially over the second side surface of the electrically conductive region. With respect to the vertical axis of the trench structure, the first floating gate region is formed over the third floating gate region, and the second floating gate region is formed over the fourth floating gate region.

According to another embodiment, the multi-bit memory element comprises a substrate, wherein the trench structure of the multi-bit memory element is at least partially formed in the substrate, and wherein the electrically conductive region and the floating gate regions through the electrically insulating region are electrically isolated from the substrate.

In one embodiment of the invention it is provided that the multi-bit memory element is designed as a memory cell transistor, wherein in the substrate, a first source / drain region and a second source / drain region are formed, wherein the trench structure at least partially between the first source / drain region and the second source / drain region is formed, and wherein the first source / drain region and the second source / drain region are electrically insulated from the floating gate regions.

In another embodiment, it is provided that a first bit line region is formed at least partially on the first source / drain region, and that a second bit line region is formed at least partially on the second source / drain region.

According to another embodiment of the invention, a word line region formed at least partially on the electrically conductive region may be formed.

The first and / or the second source / drain region may be doped, for example n-doped, wherein the dopant concentration may be between 10 ¹⁶ cm ^-3 and 10 ²¹ cm ^-3 . The doping of the source / drain regions can be done by means of an ion implantation process.

In another embodiment of the invention, the multi-bit memory element may have a third bit line region, which is formed at least on a partial region of the trench structure. The third bit line region may be formed in the substrate and at least partially below the trench structure. Illustratively, the third bit line region may be formed as a buried bit line region.

The third bit line region may be on a portion of the electrically insulating Area be formed such that the third bit line region of the electrically conductive region and the floating gate regions is electrically isolated.

The third bit line region may be doped, for example n-doped, wherein the dopant concentration may be between 10 ¹⁶ cm ^-3 and 10 ²¹ cm ^-3 .

The doping of the third bit line region can be carried out by means of an ion implantation method.

The shape of the doping profile in the two source / drain regions and / or the third bit line region, similar to the dimensions of the trench structure or the dimensions of the regions formed in the trench structure (floating gate regions, electrically conductive region, electrical Insulating area or electrically insulating portions) a strong impact on the efficiency of programming or erasing operations in the multi-bit memory cell. Both the dimensions of the multi-bit memory cell or the trench structure and the data schemes or doping profiles can therefore be optimized with respect to the functionality of the multi-bit memory cell.

An advantage of the invention can be seen in the fact that the shape of the doping profile can be optimized without there being any increase in the feature size of the multi-bit memory element.

In another embodiment of the invention, it is provided that in the first source / drain region and / or in the second source / drain region, the dopant concentration increases towards the substrate surface.

In another embodiment of the invention it is provided that a doped well region is formed in the substrate at least below the trench structure, wherein the doped well region may be formed, for example, as a p-doped well region.

The dopant concentration in the doped well region may be between 5 × 10 ¹⁶ cm ^-3 and 5 × 10 ¹⁷ cm ^-3 .

The doping of the well region can be done by means of an ion implantation process.

The floating gate regions formed in the trench structure preferably comprise polysilicon material. Alternatively, the floating gate regions may also comprise electrically conductive carbon material or titanium nitride (TiN).

One aspect of the invention can be seen in the fact that in a multi-bit memory element, the introduced (injected) charge carriers (eg electrons) are collected or stored on floating gates, which floating gates an electrically conductive material such , As polysilicon, electrically conductive carbon material or titanium nitride (TiN) have.

In contrast to the prior art, in which charge carriers are collected on a nitride layer of an oxide-nitride-oxide layer stack (ONO layer stack), it is when using floating gates made of an electrically conductive material such. B. polysilicon (also called floating poly) uncritical, where exactly get the charge carriers in or on the floating gate, since the charge carriers can move freely on the metallic floating gate.

The electrically conductive region formed in the trench structure may also comprise polysilicon material.

Illustratively, the electrically conductive region formed in the trench structure serves as a control gate of a memory cell transistor, which is electrically insulated from the floating gates by the electrically insulating region.

The electrically insulating region may include an oxide material (eg, silicon dioxide) or a nitride material (eg, silicon nitride), generally a dielectric material.

In the event that a plurality of electrically insulating partial regions are formed in the trench structure, one or more of the electrically insulating partial regions may comprise an oxide material (eg silicon dioxide) and / or a nitride material (eg silicon nitride).

A substrate in which the trench structure of the multi-bit memory element is formed comprises, for example, one of the following materials: silicon, germanium, SiGe, gallium arsenide, indium phosphide, an IV-IV semiconductor material, a III-V semiconductor material, a II -VI semiconductor material.

According to one embodiment of the invention, in a method for producing a multi-bit memory element having a trench structure, the formation of the trench can be effected by means of a lithography method and / or an etching method.

In another embodiment, the formation of the floating gate regions in the Trench structure by means of forming at least one spacer layer or at least one spacer, wherein the at least one spacer layer (or spacer) is formed at least over a portion of the inner side walls of the trench.

The formation of the at least one spacer layer can take place with the aid of a deposition method. As a deposition method, a gas phase separation method such. B. Chemical Vapor Deposition (CVD) can be used.

The at least one spacer layer may comprise a polysilicon material. In other words, the at least one spacer layer can be formed as a polysilicon layer.

Illustratively, in a method for producing a multi-bit memory element by forming at least one spacer layer (or at least one spacer) made of polysilicon material over a partial region of the inner sidewalls of the trench structure, the floating poly regions can be easily produced. i. e. the floating gates are made of polysilicon.

In another embodiment of the invention, in a method of manufacturing a multi-bit memory element after forming the trench and before forming the electrically insulating region, a sacrificial oxide layer may be formed over at least a portion of the sidewalls and / or bottom of the trench.

The sacrificial oxide layer can be removed again after the formation. The removal of the sacrificial oxide layer can be effected by means of an etching process.

Embodiments of the invention are illustrated in the figures and are explained in more detail below. In the figures, the same elements are provided with the same reference numerals. The illustrations shown in the figures are schematic and therefore not drawn to scale.

Show it

1 a conventional multi-bit memory element with a trench structure as a comparative example for explaining the invention;

2A a simulation of the electron temperature distribution during a programming process for the in 1 shown multi-bit memory element;

2 B a simulation of the distribution of electric field strength during the programming process for the in 1 shown multi-bit memory element;

3A a time course of the electric charge amount on the first floating gate region and the second floating gate region of in 1 shown multi-bit memory element during the programming process;

3B Current-voltage characteristics for various read operations in the multi-bit memory element 1 ;

3C Current-voltage characteristics for further reads in the multi-bit memory element 1 ;

3D a dependence of the threshold voltage of the source / drain potential for forward and backward reads in the multi-bit memory element 1 ,

4A to 4J different times during a process for producing the in 1 shown conventional multi-bit memory element having a trench structure as a comparative example for explaining the invention;

5 a multi-bit memory element having a trench structure according to an embodiment of the invention;

6A to 6D schematic representations of programming operations for the in 5 shown multi-bit memory element;

7A to 7D schematic representations of reads for the in 5 shown multi-bit memory element;

8A to 8P different times during a process for producing the in 5 shown multi-bit memory element having a trench structure according to an embodiment of the invention.

1 shows a conventional multi-bit memory element 100 with a trench structure 101 as a comparative example to illustrate the invention. The trench structure 101 has a U-shaped structure with a curved lower portion, the lowest point of the trench structure 101 , vividly the vertex of the curved portion or the "U's" of the trench structure 101 , by the arrow 150 is marked. The trench structure 101 has an electrically conductive area 102 on and one on the electrically conductive area 102 trained electrically insulating area 103 , Furthermore, the trench structure has 101 a first floating gate region 104a and a second floating gate region 104b on which floating gate areas 104a . 104b on or in the electrically insulating region 103 are formed and which floating gate areas 104a . 104b through the electrically insulating area 103 from each other and from the electrically conductive region 102 are electrically isolated.

The first floating gate area 104a and the second floating gate region 104b serve illustratively as first and second floating gates, respectively, for storing a first bit and a second bit, and the electrically conductive region 102 serves as a control gate, with the help of which write, read and erase operations in the multi-bit memory element 100 can be controlled.

In the example shown, the first floating gate region is 104a at least partially over a first side surface 102 of the electrically conductive region 102 formed, and the second floating gate area 104b is at least partially over a second side surface 102b of the electrically conductive region 102 formed, wherein the second side surface 102b the first side surface 102 opposite.

The first floating gate area (first floating gate) 104a and the second floating gate region (second floating gate) 104b have polysilicon material. Alternatively, the floating gate areas 104a . 104b but also, for example, electrically conductive carbon material or titanium nitride (TiN).

The electrically conductive area (control gate) 102 also has polysilicon material.

The electrically insulating area 103 the trench structure 101 is formed such that it has a plurality of electrically insulating portions, wherein a first electrically insulating portion 103a between the first floating gate area 104a and the electrically conductive region 102 is formed, a second electrically insulating portion 103b between the second floating gate region 104b and the electrically conductive region 102 is formed, and further comprising an electrically insulating edge region 103c is trained.

The electrically insulating subregions, ie the first electrically insulating subregion 103a , the second electrically insulating subregion 103b and the electrically insulating edge region 103c are formed of an oxide material (eg, silicon dioxide). The electrically insulating area 103 is therefore also called gate oxide 103 designated.

The multi-bit memory element 100 has a substrate 105 on, which is formed as a silicon substrate. In the substrate 105 are a first source / drain region 106a and a second source / drain region 106b educated. The trench structure 101 is at least partially in the substrate 105 formed such that the trench structure 101 at least partially between the first source / drain region 106a and the second source / drain region 106b is trained. The trench structure 101 is through the electrically insulating area 103 , more precisely through the electrically insulating edge region 103c , from the substrate 105 or the first source / drain region 106a and the second source / drain region 106b electrically isolated.

The first source / drain region 106a and the second source / drain region 106b are doped, wherein in both areas, the dopant concentration to the substrate surface, vividly "from bottom to top", increases. In other words, the first source / drain region 106a or the second source / drain region 106b each have a variable dopant profile, wherein the doping strength increases from bottom to top.

This is done by the in 1 shown superimposed seven sections of the first source / drain region 106a or the second source / drain region 106b FIG. 2 illustrates which seven partial regions each have an approximately constant dopant concentration, the dopant concentration increasing from the lowest partial region to the uppermost partial region.

cm^–3 bezeichnet, kann beispielsweise gelten: 17 ≤ n₁ ≤ 17,5, 17,5 ≤ n₂ ≤ 18, 18 ≤ n₃ ≤ 18,5, 18,5 ≤ n₄ ≤ 19, 19 ≤ n₅ ≤ 19,5, 19,5 ≤ n₆ ≤ 20, 20 ≤ n₇ ≤ 20,5.Taking the subregions of the first source / drain region 106a or the second source / drain region 106b Numbered from bottom to top with 1 to 7, and the doping strength of the ith area (1 ≤ i ≤ 7) with D _i =

cm ^-3 , for example, 17 ≤ n ₁ ≤ 17.5, 17.5 ≤ n ₂ ≤ 18, 18 ≤ n ₃ ≤ 18.5, 18.5 ≤ n ₄ ≤ 19, 19 ≤ n ₅ ≤ 19.5, 19.5 ≤ n ₆ ≤ 20, 20 ≤ n ₇ ≤ 20.5.

In this context, it should be noted that the subdivision of the doped source region 106a or the doped drain region 106b in each case seven subregions, each with approximately constant data strength, are to be understood as exemplary only. It is also possible to form other dopant profiles, the exact shape of the dopant profile or the location dependence of the doping strength in the first source / drain region 106a or the second source / drain region 106b in terms of the functionality of the multi-bit memory element 100 can be optimized.

The multi-bit memory element 100 also has a word line area 110 on, which at least partially on the electrically conductive region 102 or the control gate 102 is trained. The word line area 102 serves as a word line for electrical contacting or driving of the control gate 102 , The word line area 110 has polysilicon material.

Furthermore, the multi-bit memory element 100 a first bitline area 111 which is on a part of the source area 106a is formed, and a second bit line area 112 which is on a part of the second source / drain region 106b is trained. The first bitline area 111 and the second bit line area 112 serve as bit lines for electrically contacting or driving the first source / drain region 106a or the second source / drain region 106b , The first bitline area 111 and the second bit line area 112 have polysilicon material.

The first bitline area 111 is from the word line area 110 through additional electrically insulating areas 107a . 108a and 109a electrically isolated, and the second bit line area 112 is from the word line area 110 through the electrically insulating areas 107b . 108b and 109b electrically isolated, the electrically insulating areas 107a . 107b . 109a and 109b an oxide material (eg, silicon dioxide), and the electrically insulating regions 108a and 108b a nitride material (eg, silicon nitride).

The below the trench structure 101 , the first source / drain region 106a and the second source / drain region 106b located subregion of the substrate 105 is as a doped well area 120 formed, wherein the dopant concentration in the doped well region 120 between 5 × 10 ¹⁶ cm ^-3 and 5 × 10 ¹⁷ cm ^-3 .

The transition between the first source / drain region 106a and the doped well area 120 of the substrate 105 gets through the thick printed line 130a and the transition between the second source / drain region 106b and the doped well area 120 of the substrate 105 gets through the thick printed line 130b illustrated. The transitions 130a respectively. 130b are also referred to as bitline junctions or bitline junctions.

This in 1 shown multi-bit memory element 100 is illustratively designed as a memory cell transistor or as a non-volatile memory cell transistor (NVM cell transistor), with a trench structure 101 and two poly-floating gates 104a . 104b (ie polysilicon floating gates).

In 1 are still characteristic dimensions of the trench structure 101 of the multi-bit memory element 100 illustrated.

The arrow 160 indicates an axis or direction which is perpendicular to the side walls 102 . 102b of the electrically conductive region 102 stands and thus, for example, runs parallel to the substrate surface. The axis 160 is hereafter referred to as horizontal axis 160 designated.

The arrow 170 indicates an axis or direction which is perpendicular to the horizontal axis 160 stands and in the in 1 shown section plane of the trench structure 101 lies. The axis 170 thus runs perpendicular to the substrate surface and is hereinafter referred to as a vertical axis 170 designated.

In the example shown, for example, for a feature size of 60 nm, the first floating gate area 104a and the second floating gate region 104b along the horizontal axis 160 each have a maximum extent d ₁ , where d ₁ = 10 nm ± 2 nm. The first electrically insulating subregion 103a and the second electrically insulating portion 103b point along the horizontal axis 160 in each case a maximum extent d ₂ , where d _{2 is} 6 nm ± 1 nm. The electrically insulating edge area 103c has a thickness d ₃ = 6 nm ± 1 nm. The trench structure 101 points along the horizontal axis 160 a maximum extent d ₄ . Illustratively, d ₄ corresponds to the feature size of the multi-bit memory element 100 , In the example shown, the feature size d _{4 is} 60 nm.

In this context, it should be noted that the feature size usually has no tolerances, whereas technological parameters such as etch depths or layer thicknesses fluctuate.

The maximum extent of the trench structure 101 along the vertical axis 170 is 160 nm ± 10 nm.

By applying a positive voltage to the word line 110 is clearly below the curved portion of the trench structure 101 a conductive channel in the substrate 105 or in the substrate 105 trained tub area 120 formed, wherein the length of the channel by the difference between the depth of the bit line transitions 130a respectively. 130b and the depth of the trench or trench structure 101 ie the vertex 150 the trench structure 101 , given is. In the example shown, the channel length is about 100 nm to 120 nm.

If the channel length is too large, unwanted carrier injection into adjacent memory cells occurs. In the reverse case, ie with too short a channel length, similar problems occur as with planar memory elements. Consequently, it is it is necessary to know the exact dimensions of characteristic features of the trench structure 101 , such as the channel length, in terms of the functionality of the multi-bit memory element or the multi-bit memory cell 100 to optimize, for example with the help of computer simulations.

It should therefore be noted at this point that the above-mentioned ranges for the dimensions d ₁ , d ₂ , d ₃ and d ₄ are to be understood as exemplary. For example, modified extents may be selected for other feature sizes.

Based on the following 2A to 3D results of computer simulations are presented, with which computer simulations the functionality of the related 1 described multi-bit memory element 100 was investigated.

2A shows a distribution of the electron temperature T _e in the multi-bit memory element or memory cell transistor 100 for a programming operation or under programming conditions, in which the first source / drain region 106a has an electric potential V _s = 0 V at which the second source / drain region 106b has an electric potential V _d = 5 V, and at the word line area 110 or the control gate 102 an electric potential V _wl = _3V is applied. It is shown that the high electron temperature regions T _{e are} near the bit line transition 130b and near the second floating gate region and second floating gate, respectively 104b lie. In other words, there are hot electrons (hot electrons), ie, electrons with high kinetic energy, preferably near the bit line transition 130b and near the second floating gate 104b , These areas thus have a high injection probability. In other words, the likelihood that hot electrons are relatively high on the second floating gate is relatively high 104b (through so-called Channel Hot Electron (CHE) Injection). The probability of charge carrier or electron injection onto the first floating gate 104a is, on the other hand, low under the conditions shown, since the electrons are close to the first floating gate 104a essentially only have thermal energy.

2 B shows in analogy to 2A the distribution of the electric field strength E in the multi-bit memory element determined from the computer simulation 100 during the programming process. The figure shows that the electric field strength E in the electrically insulating region or gate oxide 103 between the second source / drain region 106b and the word-line area 110 not high enough for a dielectric breakthrough. When forming the trench structure 101 It may also be due to increased oxide growth on the highly doped (eg n-doped) portion of the second source / drain region 106b (eg, the top portion of the second source / drain region 106b with a dopant concentration of about 10 ²⁰ cm ^-3 , cf. 1 ) to a local thickening of the gate oxide, whereby the field strength E is additionally reduced in this area.

The diagram 300 in 3A shows the time course of the electric charge Q _FG on the first (source side) floating gate 104a (Curve 301 : "Charge on source sided floating gate") and on the second (drain-side) floating gate 104b (Curve 302 : "Charge on drain sided floating gate") of the multi-bit memory element 100 while in connection with the 2A and the 2 B Programmed programming operation, ie under the above-mentioned programming conditions, ie electrical potentials at source / drain regions or control gate. 3A shows the transient or transient behavior of the electric charge on the two floating gates 104a and 104b during the programming process.

From the curve shown in the figure 301 It can be seen that no carrier injection on the (source side) first floating gate 104a takes place, whereas on the (drain side) second floating gate 104b negative charge carriers, ie electrons, are injected (see curve 302 ). The programming process thus becomes the charge state of the second (drain-side) floating gate 104b changed by injection of hot electrons from the channel (Channel Hot Electron Injection, CHE), while the charge state of the first (source side) floating gate 104a remains unchanged.

Generally, the programming of the multi-bit memory cell is done 100 hot-electron injection onto the floating gates, and erasure is made by injecting hot holes onto the floating gates.

The diagram 310 in 3B shows in semilogarithmic plot the dependence of the drain current I _d , ie the current between the source region 106a and drain area 106b from the word line area 110 or at the control gate 102 applied electric potential V _wl for different read operations in the multi-bit memory _element or the multi-bit memory cell 100 ,

The curve labeled "virgin" 311 shows the dependence of the drain current I _d on the gate potential V _wl when reading out an unrecorded multi-bit memory _element 100 ie a multi-bit memory element in which both floating Gates 104a and 104b are uncharged. In this case, the second source / drain region was added 106b an electrical potential V _d = 2.3 V is applied, and to the first source / drain region 106a An electrical potential V _s = 0 V was applied.

The curve labeled "forward read" 312 shows the dependence of the drain current I _d on the gate potential V _wl in the forward readout of a multi-bit memory _element 100 , which is an electrically uncharged source-side floating gate 104a and an electrically charged drain-side floating gate 104b having. The term "forward read-out" indicates that the current flow, more specifically the flow of electrons, during the read-out process from the first source / drain region 106a with low electrical potential (V _s = 0 V) to the second source / drain region 106b with higher electrical potential (V _d = 2.3 V).

In other words, in the case of the designation "forward read" or "forward read", the direction is related to the direction in the programming operation: When programming the multi-bit memory cell 100 for example, let V _s = 0 V and V _d = 5 V (cf. 2A ). In this case, a charge on the side of the second source / drain region 106b More specifically, on the drain-side floating gate 104b injected. For example, in "forward read", V _s = 0 V and V _d = 2.3 V (ie same direction as in programming, but insensitive to the injected charge).

The curve labeled "reverse read" 313 shows the dependence of the drain current I _d on the gate potential V _wl in the backward readout of the multi-bit memory _element 100 with electrically uncharged source-side floating gate 104a and electrically charged drain-side floating gate 104b , The term "backward readout" indicates that the current flow, more precisely the electron flow, during the read-out process from the second source / drain region 106b with low electrical potential (V _d = 0 V) to the first source / drain region 106a with higher electrical potential (V _s = 2.3 V).

In other words, in the "reverse read" or "reverse read", the direction of the direction in the programming operation of the multi-bit memory cell is again 100 (see. 2A For example, in "reverse read", V _s = 2.3 V and V _d = 0 V (ie opposite direction as in programming, but sensitive to the injected charge).

In 3B is shown that the threshold voltage of the multi-bit memory element 100 or the memory cell transistor 100 , ie the voltage at which a significant drain current I _{d is} to be recorded, for the reverse read-out operation (curve 313 ) is about 2 volts higher than for the forward read (curve 312 ). The multi-bit memory element 100 therefore has a very good separation of two on the two floating gates 104a and 104b storable bits on (Two Bit Separation).

The diagram 320 in 3C shows the dependence of the drain current I _d on the gate potential V _wl for forward readout of one on the drain-side floating gate 104b stored bits (Bit2) and backward read one of the source-side floating gate 104a stored bits (Bit1), wherein in the forward readout, the first source / drain region 106a has an electrical potential V _s = 0 V and the second source / drain region 106b has an electric potential of 0.2 V ≦ V _d ≦ 4.2 V, and wherein in the reverse readout, the second source / drain region 106b has an electrical potential V _d = 0 V and the first source / drain region 106a has an electric potential of 0.2V ≦ V _s ≦ 4.2V.

From the in 3C shown diagram 320 is read that the threshold voltage V _{th of} the multi-bit memory element 100 when read forward with increasing drain potential V _d significantly reduced, whereas the backward readout the threshold voltage V _th only slightly decreases with increasing source potential V _s .

The situation just mentioned is also indicated by the in 3D shown diagram 330 illustrates in which the threshold voltage V _{th of} the multi-bit memory element 100 with electrically uncharged source-side floating gate 104a and electrically charged drain-side floating gate 104b against the absolute value of the source / drain voltage | V _{s / d} | (with V _{s / d} = V _d - V _s ) for forward read-out (curve 331 : "Forward read") and backward readout (curve 332 : "Reverse read") is applied. In the diagram 330 It is shown that the threshold voltage V _th for a forward read operation (with V _d > V _s ) increases with | V _{s / d} | strongly decreases, whereas in a reverse read operation (with V _d <V _s ), the threshold voltage V _th increases as | V _{s / d} | only slightly decreases.

The following is based on the 4A to 4J a method for producing the in 1 shown conventional multi-bit memory element 100 or memory cell transistor 100 as a comparative example to illustrate the invention.

For the production of the multi-bit memory element 100 will, as in 4A shown a substrate 105 provided, which is formed as a silicon substrate. On the substrate 105 using a deposition process, a first oxide layer 107 (also referred to as pad oxide) formed. As the deposition method, a vapor deposition method such as a chemical vapor deposition (CVD) method can be used.

Alternatively, the first oxide layer 107 or the pad oxide 107 also be formed by a thermal oxidation.

In the substrate 105 Furthermore, by introducing doping atoms, a p-doped well region is formed 120 educated.

The doping takes place with the aid of an ion implantation method (so-called well implantation). The dopant concentration in the doped well region 120 may be about 5 × 10 ¹⁶ cm ^-3 to 5 × 10 ¹⁷ cm ^-3 .

Furthermore, by introducing doping atoms, an n-doped region is formed 106 in the substrate 105 formed, from which n-doped region 106 in subsequent process steps, source / drain regions 106a and 106b (see. 1 ) are formed. In the in 4A As shown, the formation of the n-doped region takes place 106 such that the dopant concentration in the doped region 106 towards the substrate surface, ie from "bottom to top" increases. In other words, the doped region 106 a variable dopant profile, wherein the doping strength increases from bottom to top.

cm^–3 bezeichnet, kann beispielsweise gelten: 17 ≤ n₁ ≤ 17,5, 17,5 ≤ n₂ ≤ 18, 18 ≤ n₃ ≤ 18,5, 18,5 ≤ n₄ ≤ 19, 19 ≤ n₅ ≤ 19,5, 19,5 ≤ n₆ ≤ 20, 20 ≤ n₇ ≤ 20,5.In 4A are in the doped area 106 For example, seven subregions drawn in, each having an approximately constant doping strength. If one numbered the areas from bottom to top with 1 to 7, and the doping strength of the ith area (1 ≤ i ≤ 7) with D _i =

cm ^-3 , for example, 17 ≤ n ₁ ≤ 17.5, 17.5 ≤ n ₂ ≤ 18, 18 ≤ n ₃ ≤ 18.5, 18.5 ≤ n ₄ ≤ 19, 19 ≤ n ₅ ≤ 19.5, 19.5 ≤ n ₆ ≤ 20, 20 ≤ n ₇ ≤ 20.5.

In this context, it should be noted that the subdivision of the doped region 106 is to be understood in seven sub-regions, each with approximately constant doping only by way of example. Other dopant profiles may also be formed, with the exact shape of the dopant profile or the location dependence of the datier strength with respect to the functionality of the multi-bit memory element 100 to optimize.

After forming the n-doped region 106 in the substrate 105 there is a tempering or a so-called Anneal, ie a heating of the doped region 106 , The implanted dopants are electrically activated.

The transition between the doped region 106 and the doped well area 120 is in 4A schematically through the thick black line 130 clarified.

In a further method step, as in 4B shown a nitride layer 108 (also referred to as pad nitride) on the first oxide layer 107 or the pad oxide 107 formed, for example, using a vapor deposition method such as Chemical Vapor Deposition.

In further process steps, as in 4C a ditch 101 ' in the substrate 105 educated. The ditch 101 ' is as a U-shaped ditch 101 ' formed, with vertical side walls 101a ' and a curved bottom 101b ' , The arrow 150 marks the lowest point of the trench 101 ' or the curved bottom 101b ' , Forming the trench 101 ' can be done by means of a lithography process and an etching process, wherein the nitride layer 108 serves as a hard mask.

By forming the trench 101 ' be simultaneously from the doped area 106 a doped source region 106a and a doped drain region 106b formed with corresponding dopant profiles. The transition between the first source / drain region 106a and the tub area 120 is through the thick printed line 130a characterized, the transition between the second source / drain region 106b and the tub area 120 is corresponding to the thick printed line 130b characterized.

By forming the trench 101 ' are further made of the first oxide layer 107 two oxide sublayers 107a and 107b formed, and from the nitride layer 108 become two nitride sublayers 108a and 108b educated.

In a further process step may be on the side walls 101a ' and the floor 101b ' of the trench 101 ' a sacrificial oxide layer may be formed (not shown). The sacrificial oxide layer can be removed again in a subsequent method step.

In another, in 4D shown, process step is a second oxide layer 103 ' on the side walls 101a ' and the floor 101b ' of the trench 101 ' , as well as on the nitride partial layers 108a and 108b educated. Forming the second oxide layer 103 ' takes place, for example, by a growth process or by thermal oxidation. Part of the second oxide layer 103 ' Illustratively, it forms a part of the gate oxide, which forms the floating gate regions to be formed in further method steps from that in the substrate 105 trained tub area 120 and the first source / drain region 106a and the second source / drain region 106b electrically isolated. Instead of a single oxide layer 103 ' can also be several (electrically insulating) layers, which may also have different materials are formed.

In another, in 4E shown, process step is a spacer layer 104 on the second oxide layer 103 ' educated. The formation of the spacer layer 104 takes place for example by means of a deposition method, z. As a gas phase deposition method such as chemical vapor deposition. The spacer layer 104 preferably comprises polysilicon material, and is therefore also referred to as poly-spacer or poly-liner. Alternatively, the spacer layer 104 but also another material such. B. electrically conductive carbon or titanium nitride (TiN).

In another, in 4F shown process step is the spacer layer 104 etched anisotropically using a dry etching process (so-called spacer etching), so that floating gate areas 104a and 104b be formed of polysilicon. In the example shown, a first floating gate region becomes 104a and a second floating gate region 104b formed by the second oxide layer 103 ' from the substrate 105 or in the substrate 105 trained doped tub area 120 and the first source / drain region 106a and the second source / drain region 106b are electrically isolated. The polysilicon material of the spacer layer 104 will also be in the bottom of the trench 101 ' etched so that two separate floating gate regions, ie the first floating gate region 104a and the second floating gate region 104b to be formed.

In another, in 4G shown process step is a third oxide layer 103 '' on the two floating gate areas 104a and 104b and on portions of the second oxide layer 103 ' educated. Forming the third oxide layer 103 '' can be carried out by means of a deposition process (eg vapor deposition method, chemical vapor deposition), alternatively for example by thermal oxidation.

The third oxide layer 103 '' forms together with the second oxide layer 103 ' an electrically insulating area 103 such that the floating gate areas 104a and 104b in the electrically insulating region 103 are trained, cf. 4J , The second oxide layer 103 ' and the third oxide layer 103 '' clearly illustrate electrically insulating portions of the electrically insulating region 103 represents.

In another, in 4H shown, process step becomes a layer 121 made of electrically conductive material, preferably polysilicon material, over the entire surface of the in 4G deposited arrangement, so that the trench 101 ' is filled with the polysilicon material. In 4H are the second oxide layer 103 ' and the third oxide layer 103 '' to the electrically insulating area 103 summarized. By depositing the layer 121 is in the ditch 101 ' an electrically conductive area 102 formed, which electrically conductive area 102 at least partially between the two floating gate regions 106a and 106b is formed and of these by the electrically insulating region 103 is electrically isolated. In other words, the electrically insulating area 103 on the electrically conductive area 102 formed, and in the electrically insulating region 103 trained floating gate areas 106a and 106b be through the electrically insulating area 103 from each other and from the electrically conductive region 102 electrically isolated.

The electrically conductive area 102 which consists of a part of the layer 121 is formed, illustratively serves as a control gate 102 of the memory cell transistor formed as a multi-bit memory element 100 ,

Out 4H it can be seen that the first floating gate area 106a at least partially over a first side surface 102 of the electrically conductive region or of the control gate 102 is formed while the second floating gate region 106b at least partially over a second side surface 102b of the electrically conductive region or of the control gate 102 is formed, wherein the second side surface 102b the first side surface 102 is opposite.

In further process steps is on the electrically conductive layer 121 a hard mask (not shown), and the electrically conductive layer 121 is patterned using a lithography process and an etching process so that parts of the electrically insulating region 103 be exposed as in 4I shown. After structuring the electrically conductive layer 121 an electrically conductive area remains 110 , also word line area 110 or word line 110 called, which for electrically contacting the electrically conductive region 102 or control gates 102 of the multi-bit memory element or memory cell transistor 100 serves.

In further process steps, the floating gate polysilicon material is in the trench adjacent to the wordline 110 separated by reactive ion etching. The on the word line area 110 trained hard mask is removed, and the Digging will be next to the wordline 110 filled with oxide material, creating electrically insulating areas 109a and 109b are formed, cf. 4J , Furthermore, by removing portions of the oxide sublayers 107a and 107b , the nitride sublayers overlying it 108a and 108b as well as the subsections of the electrically insulating region formed above it 103 (For example, by an etching method) a part of the surface of the first source / drain region 106a and a part of the surface of the second source / drain region 106b exposed. On the exposed part of the surface of the first source / drain region 106a becomes a first bit line area 111 formed, which first bit line area 111 for electrically contacting the first source / drain region 106a serves, and on the exposed part of the surface of the second source / drain region 106b becomes a second bit line area 112 formed, which second bit line area 112 for electrically contacting the second source / drain region 106b serves. The first bitline area 111 is through the electrically insulating areas 103 . 107a . 108a and 109a from the word line area 110 electrically isolated, and the second bit line area 112 is through the electrically insulating areas 103 . 107b . 108b and 109b from the word line area 110 electrically isolated.

The multi-bit memory cell obtained by the above-described process steps 100 with the finished trench structure 101 is in 4J shown and corresponds to the in 1 shown multi-bit memory element 100 ,

In this context, it should be noted that in the method described above, for reasons of clarity, an indication of parameter ranges in the case of temperature steps such as, for example, inert anneals or thermal oxidations was dispensed with. It is possible to select the parameter ranges generally used in the corresponding process technology.

With regard to the reference to the 4A to 4J schematically illustrated method for producing a multi-bit memory element 100 with a trench structure 101 It should be noted that under real process conditions, the gate oxide on regions of heavily n-doped (n ⁺ ) silicon (ie the heavily doped portions of the first source / drain region 106a or the second source / drain region 106b ) is usually formed almost twice as thick as in areas with moderate doping. This is advantageous since it is precisely in these areas that a high electric field strength occurs (cf. 2 B ). In a thicker oxide layer, the electric field strength decreases.

It should also be noted that when a sacrificial oxide layer is formed and the gate oxide is formed by thermal oxidation or thermal growth, the interface between the gate oxide and silicon automatically shifts towards the source / drain regions. This is advantageous since it increases the channel length but not the opening of the trench or the trench structure, which opening is correlated with the feature size.

In the schematic representations of 1 and 4J has the electrically insulating edge region 103c near the crest 150 the trench structure 101 a double thickness. The reason for this is that in the example shown, the third oxide layer 103 '' is formed using a deposition method (see. 4G ). If the third oxide layer 103 '' however, is formed by thermal oxidation, it does not come to the above-mentioned effect of a "double-thick" oxide layer.

5 shows a multi-bit memory element 500 with a trench structure 501 according to an embodiment of the invention. The trench structure 501 has a U-shaped structure with a curved lower portion, the lowest point of the trench structure 501 , vividly the vertex of the curved portion or the "U's" of the trench structure 501 , by the arrow 550 is marked.

The trench structure 501 has an electrically conductive area 502 on and one on the electrically conductive area 502 trained electrically insulating area 503 , Furthermore, the trench structure has 501 a first floating gate region 504a , a second floating gate region 504b , a third floating gate area 514a and a fourth floating gate region 514b which is in the electrically insulating region 503 are formed and through the electrically insulating region 503 from each other and from the electrically conductive region 502 are electrically isolated.

The four floating gate areas 504a . 504b . 514a and 514b serve illustratively as floating gates for storing four bits, and the electrically conductive area 502 serves as a control gate, with the help of which write, erase and read operations in the multi-bit memory element 500 can be controlled.

Analogous to 1 the arrow indicates 160 the horizontal axis, which is perpendicular to the side walls 502a . 502b of the electrically conductive region 502 stands. The arrow 170 denotes the vertical axis, which is perpendicular to the horizontal axis stands and in the in 5 shown section plane of the trench structure 501 lies.

In the embodiment shown, the first floating gate region 504a and the third floating gate region 514a at least partially over a first side surface 502a of the electrically conductive region 502 formed during the second floating gate area 504b and the fourth floating gate region 514b at least partially over a second side surface 502b of the electrically conductive region 502 are formed, wherein the second side surface 502b the first side surface 502a opposite. Furthermore, with respect to the vertical axis 170 the trench structure that is the first floating gate area 504a over the third floating gate area 514a is formed, and that the second floating gate area 504b above the fourth floating gate area 514b is trained.

The four floating gate areas (floating gates) 504a . 504b . 514a and 514b have polysilicon material. Alternatively, however, the floating gates may also include, for example, electrically conductive carbon material or titanium nitride (TiN).

The electrically conductive area (control gate) 502 also has polysilicon material.

The electrically insulating area 503 is formed of an oxide material (eg, silicon dioxide). The electrically insulating area 503 is therefore also called gate oxide 503 designated.

Generally, the electrically insulating region 503 comprise a dielectric material.

The multi-bit memory element 500 has a substrate 505 on, which is formed as a silicon substrate. In the substrate 505 are a first source / drain region 506a and a second source / drain region 506b educated. The trench structure 501 is in the substrate 505 formed such that the trench structure 501 at least partially between the first source / drain region 506a and the second source / drain region 506b is trained. The trench structure 501 is through the electrically insulating area 503 from the substrate 505 or the first source / drain region 506a and the second source / drain region 506b electrically isolated.

The first source / drain region 506a and the second source / drain region 506b are doped, wherein in both areas, the dopant concentration to the substrate surface, vividly "from bottom to top", increases. In other words, the first source / drain region 506a or the second source / drain region 506b each have a variable dopant profile, wherein the doping strength increases from bottom to top.

This is done by the in 5 shown stacked six sections of the first source / drain region 506a or the second source / drain region 506b FIG. 2 illustrates which six partial regions each have an approximately constant dopant concentration, the dopant concentration increasing from the lowest partial region to the uppermost partial region.

cm^–3 bezeichnet, kann beispielsweise gelten: 17,5 ≤ n₁ ≤ 18, 18 ≤ n₂ ≤ 18,5, 18,5 ≤ n₃ ≤ 19, 19 ≤ n₄ ≤ 19,5, 19,5 ≤ n₅ ≤ 20, 20 ≤ n₆ ≤ 20,5.Taking the subregions of the first source / drain region 506a or the second source / drain region 506b numbered from bottom to top with 1 to 6, and the doping strength of the i-th region (1 ≤ i ≤ 6) with D _i =

cm ^-3 , for example, 17.5 ≦ n ₁ ≦ 18, 18 ≦ n ₂ ≦ 18.5, 18.5 ≦ n ₃ ≦ 19, 19 ≦ n ₄ ≦ 19.5, 19.5 ≦ n ₅ ≤ 20, 20 ≤ n ₆ ≤ 20.5.

In this context, it should be noted that the subdivision of the doped source region 506a or the doped drain region 506b in each case six subregions, each with approximately constant doping intensity, are to be understood by way of example only. It is also possible to form other dopant profiles, the exact shape of the dopant profile or the location dependence of the doping strength in the first source / drain region 506a or the second source / drain region 506b in terms of the functionality of the multi-bit memory element 500 can be optimized.

The multi-bit memory element 500 also has a word line area 510 on, which at least partially on the electrically conductive region 502 or the control gate 502 is trained. The word line area 502 serves as a word line for electrically contacting or driving the control gate 502 , The word line area 510 has polysilicon material.

Furthermore, the multi-bit memory element 500 a first bitline area 511 which is on a part of the first source / drain region 506a is formed, and a second bit line area 512 which is on a part of the second source / drain region 506b is trained. The first bitline area 511 and the second bit line area 512 serve as bit lines for electrically contacting or driving the first source / drain region 506a or the second source / drain region 506b , The first bitline area 511 and the second bit line area 512 have polysilicon material.

The first bitline area 511 is from the word line area 510 through an electrically insulating area 509a electrically isolated, and the second bitline area 512 is from the word line area 510 through an electrically insulating area 509b electrically isolated, the electrically insulating areas 509a and 509b have an oxide material. In general, the electrically insulating areas 509a and 509b comprise a dielectric material.

The multi-bit memory element 500 also has a third bit line area 513 on, which on a lower portion of the trench structure 501 is trained. As in 5 is the third bitline area 513 partly below the trench structure 501 is formed and is therefore also referred to as a buried bit line area.

The third bitline area 513 is on a portion of the electrically insulating region 503 formed such that the third bit line area 513 from the electrically conductive region 502 and the four floating gate areas 504a . 504b . 514a and 514b is electrically isolated.

The third bitline area 513 is n-doped, wherein the dopant concentration is between 10 ¹⁷ cm ^-3 and 10 ²¹ cm ^-3 and the dopant profile in the third bit line region is indicated by the contour lines: the dopant concentration in the third bit line region 513 decreases from the inside to the outside, in other words, the portion of the third bit line area 513 , which portion is bounded by the surface of the trench structure and the innermost contour line, the highest dopant concentration on (10 ²¹ cm ^-3 ), while the dopant concentration in the adjacent portions of the third bit line region 513 decreases.

The doping of the third bit line region 513 can be done for example by means of an ion implantation method. Alternatively, the doping can be effected by outdiffusion from a material acting as a dopant source.

The below the trench structure 501 , the first source / drain region 506a and the second source / drain region 506b located subregion of the substrate 505 is as a p-doped well area 520 formed, wherein the dopant concentration in the doped well region 520 between 5 × 10 ¹⁶ cm ^-3 and 5 × 10 ¹⁷ cm ^-3 .

The transition between the first source / drain region 506a and the doped well area 520 of the substrate 505 gets through the thick printed line 530a and the transition between the second source / drain region 506b and the doped well area 520 of the substrate 505 gets through the thick printed line 530b illustrated. The transitions 530a respectively. 530b are also referred to as bitline junctions or bitline junctions.

This in 5 shown multi-bit memory element 500 is illustratively designed as a non-volatile memory cell (NVM cell), with a trench structure 501 as well as four poly-floating gates 504a . 504b . 514a and 514b (ie polysilicon floating gates) for storing four bits. The multi-bit memory element 500 or the multi-bit memory cell 500 clearly shows two vertical MOS field effect transistors (MOSFET), with three bit line areas or bit lines 511 . 512 and 513 where the third bit line 513 is designed as a buried bit line.

The trench structure 501 For example, at a feature size, F indicates 60 nm along the horizontal axis 160 a maximum extension d ₄ = 60 nm ± 5 nm. Illustratively, d ₄ corresponds to the feature size of the multi-bit memory element 500 ,

Furthermore, the trench structure 501 at F = 60 nm along the vertical axis 170 for example, a maximum extension of 200 nm ± 15 nm.

When applying a positive voltage to the word line 510 becomes apparent between the first source / drain region 506a and the third bit line area 513 a first conductive channel in the substrate 505 or in the substrate 505 trained tub area 520 formed, and between the second source / drain region 506b and the third bit line area 513 becomes a second conductive channel in the substrate 505 or in the substrate 505 trained tub area 520 educated.

With regard to the functionality of the multi-bit memory cell 500 it is necessary to know the exact dimensions of characteristic features of the trench structure 501 such as the lengths of the first conductive channel and the second conductive channel, the dimensions of the floating gates 504a . 504b . 514a and 514b , etc., for example, with the help of computer simulations.

It should therefore be noted at this point that the above values for the dimensions of the multi-bit memory cell 500 along the horizontal axis 160 or along the vertical axis 170 are to be understood as exemplary. For other feature sizes, modified extents can be selected.

Based on the following 6A to 7D is the functioning, more precisely the realization of programming operations and read operations, the in 5 shown multi-bit memory cell 500 schematically explained in more detail.

Illustratively, the multi-bit memory cell 500 two vertical transistors (MOSFETs) with a common control gate 502 and a common bit line, ie the buried third bit line 513 , on. Programming the multi-bit memory cell 500 This is done by injecting hot electrons (Channel Hot Electron Injection) onto the floating gates and erasing them by injecting hot holes onto the floating gates.

The exact voltage conditions for read / write operations and the exact dimensions of the multi-bit memory cell 500 can be optimized. For example, the quantum mechanical tunneling of electrons through the electrically insulating region 503 (Fowler-Nordheim Tunneling) are suppressed.

A fundamental principle in the operation of the multi-bit memory cell 500 is that during operation of one of the two vertical transistors on the one side of the trench or the trench structure 501 (eg to perform a program, erase or read operation) the transistor on the other side of the trench structure 501 Is "deactivated". The deactivation of this transistor is achieved in that the associated upper bit line, ie the first bit line area 511 in the case of the "left" transistor or the second bit line area 512 in the case of the "right" transistor, and thus the first source / drain region 506a or drain area 506b be set to the same electrical potential as the buried bit line 513 ,

6A shows a program operation ("Program") in the multi-bit memory element 500 in which the charge state of the first floating gate 504a is changed by injection of hot electrons (indicated by the arrow "Hot Electron Injection"). This is due to the first source / drain region 506a an electric potential of about +5 V on, at the control gate 502 is an electric potential of about +4 V, and at the second source / drain region 506b and the third bit line area 513 in each case an electrical potential of 0 V is applied.

Due to the positive bias of the first source / drain region 506a opposite the third bitline area 513 the electrons are "left next to" the trench structure in the direction of the first source / drain region 506a accelerated, and by the positive bias of the control gate 502 accelerated simultaneously towards the trench structure. Near the first floating gate area 504a the electrons have gained enough kinetic energy to pass through the electrically insulating region 503 on the first floating gate 504a to reach (arrow "Hot Electron Injection"), whereby the charge state of the first floating gate 504a will be changed. Near the third floating gate 514a The kinetic energy of the electrons is still insufficient to make an injection of electrons onto the third floating gate 514a to effect.

Because the second source / drain region 506b has the same electric potential (ie, 0 V) as the third bit line region 513 In the area to the right of the trench structure there is no significant heating up of the electrons located there (indicated by the double arrow "No Heating of Electrons") and thus also not an injection of electrons on the second floating gate 504b or the fourth floating gate 514b , Illustratively, the right vertical transistor of the multi-bit memory cell 500 disabled.

6B shows you one 6A analog programming process ("Program") of the multi-bit memory cell 500 in which the charge state of the second floating gate 504b will be changed. In contrast to 6A are in 6A the electrical potentials of source region 506a and drain area 506b interchanged, allowing it to inject hot electrons on the second floating gate 504b comes while the left vertical transistor of the multi-bit memory cell 500 is disabled.

6C shows another program operation ("Program") of the multi-bit memory cell 500 in which the state of charge of the third floating gate 514a is changed by injection of hot electrons (indicated by the arrow "Hot Electron Injection"). Compared to the in 6A shown programming process here are the electrical potentials of the first source / drain region 506a (0V) and the third bit line area 513 (+5 V), so that clearly electrons "to the left of" the trench structure in the direction of the third bit line area 513 be accelerated and close to the third floating gate 514a have enough kinetic energy to access the third floating gate 514a to get. Further, at the second source / drain region 506b the same electric potential, ie +5 V, as at the third bit line area 513 so that there is no heating of the electrons "to the right of" the trench structure (indicated by the double arrow "No Heating of Electrons"). Clearly, the right vertical transistor is deactivated.

6D shows you one 6C analog programming process ("Program") of the multi-bit memory cell 500 in which the charge state of the fourth floating gate 514b will be changed. in the difference to 6C are in 6D the electrical potentials of source region 506a and drain area 506b interchanged, allowing it to inject hot electrons on the fourth floating gate 514b comes while the left vertical transistor is disabled.

7A shows a reverse read in the multi-bit memory cell 500 in which the charge state of the first floating gate 504a determined (read) is. To do this, go to the first source / drain area 506a an electrical potential of 0 V, to the second source / drain region 506b an electric potential of + 2V, to the control gate 502 an electric potential of +3 V and to the third bit line area 513 an electrical potential of +2 V applied. Because the second source / drain region 506b the same electric potential, ie +2 V, as the third bit line region 513 , the right vertical transistor is disabled.

7B shows a reverse read in the multi-bit memory cell 500 in which analogous to the in 7A illustrated situation, the state of charge of the second floating gate 504b determined (read) is. Unlike the in 7A Therefore, here are the electrical potentials of source region 506a and drain area 506b interchanged, and the left vertical transistor is disabled.

7C shows a reverse read in the multi-bit memory cell 500 in which the state of charge of the third floating gate 514a determined (read) is. To do this, go to the first source / drain area 506a an electric potential of +2 V, to the second source / drain region 506b an electrical potential of 0 V, to the control gate 502 an electric potential of +3 V and an electric potential of 0 V applied to the third bit line area. Because the second source / drain region 506b the same electric potential, ie 0 V, as the third bit line region 513 , the right vertical transistor is disabled.

7D shows a reverse read in the multi-bit memory cell 500 in which analogous to the in 7C illustrated situation, the charge state of the fourth floating gate 504b determined (read) is. Unlike the in 7C Therefore, here are the electrical potentials of source region 506a and drain area 506b interchanged, and the left vertical transistor is disabled.

In connection with the description of the 7A to 7D It should be noted that in these figures only reverse reads are described, since only these reverse reads are sensitive to injected charges.

As related to the multi-bit memory element 100 has already been described with two floating gates, it is generally the case that with the terms "forward read" and "reverse read" the direction is related to the programming direction (see description of 3B ).

The following is based on the 8A to 8P a method for producing the in 5 shown multi-bit memory element 500 or memory cell transistor 500 described according to an embodiment of the invention.

For the production of the multi-bit memory element 500 will, as in 8A shown a substrate 505 provided, which is formed as a silicon substrate. On the substrate 505 becomes a first oxide layer 507 (also referred to as pad oxide) formed, for example, using a deposition method.

As the deposition method, a vapor deposition method such as a chemical vapor deposition (CVD) method can be used.

Alternatively, the first oxide layer 507 or the pad oxide 507 also be formed by a thermal oxidation.

In the substrate 505 Furthermore, by introducing doping atoms, a p-doped well region is formed 520 educated. The doping may be by means of an ion implantation process
take place (so-called well implants) and the dopant concentration in the doped well region 520 may be between 5 × 10 ¹⁶ cm ^-3 and 5 × 10 ¹⁷ cm ^-3 .

Furthermore, by introducing doping atoms, an n-doped region is formed 506 in the substrate 505 formed, from which doped region 506 in subsequent process steps, source / drain regions 506a and 506b (see. 5 ) are formed. In the in 8A In the embodiment shown, the formation of the doped region takes place 506 such that the dopant concentration in the doped region 506 towards the substrate surface, ie from "bottom to top" increases. In other words, the doped region 506 a variable dopant profile, wherein the doping strength increases from bottom to top.

cm^–3 bezeichnet, kann beispielsweise gelten: 17,5 ≤ n₁ ≤ 18, 18 ≤ n₂ ≤ 18,5, 18,5 ≤ n₃ ≤ 19, 19 ≤ n₄ ≤ 19,5, 19,5 ≤ n₅ ≤ 20, 20 ≤ n₆ ≤ 20,5.In 8A are in the n-doped region 506 For example, six subregions drawn, each having an approximately constant doping strength exhibit. If one numbered the areas from bottom to top with 1 to 6, and the doping strength of the ith area (1 ≤ i ≤ 6) with D _i =

cm ^-3 , for example, 17.5 ≦ n ₁ ≦ 18, 18 ≦ n ₂ ≦ 18.5, 18.5 ≦ n ₃ ≦ 19, 19 ≦ n ₄ ≦ 19.5, 19.5 ≦ n ₅ ≤ 20, 20 ≤ n ₆ ≤ 20.5.

In this context, it should be noted that the subdivision of the doped region 506 is to be understood in six sub-regions, each with approximately constant doping only by way of example. It is also possible to form other dopant profiles, with the exact shape of the dopant profile or the spatial dependence of the doping strength with regard to the functionality of the multi-bit memory element 500 to optimize.

After forming the doped region 506 in the substrate 505 there is a tempering or a so-called Anneal, ie heating the doped region 506 , The implanted dopants are electrically activated.

The transition between the doped region 506 and the doped well area 520 is in 8A schematically through the thick black line 530 clarified.

In a further method step, as in 8B shown a nitride layer 508 (also referred to as pad nitride) on the first oxide layer 507 or the pad oxide 507 formed, for example, using a vapor deposition method such as Chemical Vapor Deposition.

In further process steps, as in 8C shown a ditch 501 ' in the substrate 505 educated. The ditch 501 ' is as a U-shaped ditch 501 ' formed, with vertical side walls 501a ' and a curved bottom 501b ' , The arrow 550 marks the lowest point of the trench 501 ' or the curved bottom 501b ' , Forming the trench 501 ' can be done by means of a lithography process and an etching process, wherein the nitride layer 508 serves as a hard mask.

By forming the trench 501 ' be simultaneously from the doped area 506 a doped source region 506a and a doped drain region 506b formed with corresponding dopant profiles. The transition between the first source / drain region 506a and the tub area 520 is through the thick printed line 530a characterized, the transition between the second source / drain region 506b and the tub area 520 is corresponding to the thick printed line 530b characterized.

By forming the trench 501 ' are further made of the first oxide layer 507 two oxide sublayers 507a and 507b formed, and from the nitride layer 508 or the hard mask 508 become two nitride sublayers 508a and 508b educated.

In a further process step is on the side walls 501a ' and the floor 501b ' of the trench 501 ' a sacrificial oxide layer is formed (not shown).

In another, in 8D shown process step is the third bit line area 513 educated. The third bitline area 513 is on a lower portion of the trench 501 ' is formed and partially below the trench 501 ' educated. The third bitline area 513 is therefore illustratively formed as a buried bit line region.

The third bitline area 513 is n-doped, with the dopant concentration between 10 ¹⁷ cm ^-3 and 10 ²¹ cm ^-3 and the dopant profile in the third bit line region 513 indicated by the contour lines: the dopant concentration in the third bit line region 513 decreases from the inside to the outside, in other words, the portion of the third bit line area 513 , which portion is bounded by the surface of the trench and the innermost contour line, the highest dopant concentration on (10 ²¹ cm ^-3 ), while the dopant concentration in the adjacent portions of the third bit line region 513 decreases.

The doping of the third bit line region 513 is done by means of an ion implantation method. Alternatively, the doping can be effected by outdiffusion from a material acting as a dopant source.

After forming the doped bitline region 513 in the substrate 505 there is a tempering or a so-called Anneal, ie heating the doped bit line area 513 , The implanted dopants are electrically activated.

After the bit line anneal, the sacrificial oxide layer is removed.

In a further method step, a second oxide layer 503 ' on the side walls 501a ' and the floor 501b ' of the trench 501 ' , as well as on the nitride partial layers 508a and 508b educated. Forming the second oxide layer 503 ' is preferably carried out by a growth process or by thermal oxidation. Part of the second oxide layer 503 ' clearly illustrates one Part of the gate oxide, which is to be formed in further process steps floating gate regions of the in the substrate 505 trained tub area 520 , the first source / drain region 506a , the second source / drain region 506b and the third bit line area 513 electrically isolated. Instead of a single oxide layer 503 ' can also be several (electrically insulating) layers, which may also have different materials are formed.

In a further method step, a first electrically conductive layer 514 of polysilicon material on the second oxide layer 503 ' formed, such that the trench 501 ' with the first polysilicon layer 514 is replenished. Forming the first polysilicon layer 514 is preferably carried out by means of a deposition method, z. As a gas phase deposition method such as chemical vapor deposition. From the first polysilicon layer 514 become in further process steps, the third floating gate region 514a and the fourth floating gate region 514b formed (cf. 5 ). Alternatively, the first electrically conductive layer 514 also another electrically conductive material such. B. electrically conductive carbon or titanium nitride (TiN).

After forming the first polysilicon layer 514 in the ditch 501 ' becomes a part of the first polysilicon layer 514 removed by etching away, leaving only in a lower portion of the trench 501 ' Polysilicon material of the layer 514 remains as in 8E shown.

Clearly, therefore, a recess (recess) is formed, wherein the formation of the depression can take place with the aid of methods known from DRAM deep trench technology.

In another, in 8F shown, process step is on the first polysilicon layer 514 and on the second oxide layer 503 ' a third oxide layer 503 '' deposited, leaving the ditch 501 ' is filled again with oxide material.

In another, in 8G shown, step becomes a part of the oxide material of the third oxide layer 503 '' and the second oxide layer 503 ' removed by etching, so that in turn a recess (recess) is formed, but now on the first polysilicon layer 514 Oxide material of the second oxide layer 503 ' and the third oxide layer 503 '' is trained. Upon removal of the oxide material by etchback, the nitride sublayers also become 508a . 508b as well as parts of the side walls 501a ' . 501b ' of the trench 501 ' exposed.

In a further method step, a fourth oxide layer 503 ''' or liner layer 503 ''' on the exposed nitride sublayers 508a and 508b , as well as on the exposed parts of the side walls 501a ' . 501b ' of the trench 501 ' formed using a deposition method (for example, chemical vapor deposition), so that the in 8H shown arrangement results.

In a further method step, a second electrically conductive layer 504 of polysilicon material on the third oxide layer 503 '' and the liner layer 503 ''' formed, such that the trench 501 ' with the second polysilicon layer 504 is replenished. Forming the second polysilicon layer 514 Again, preferably by means of a deposition method, z. As a gas phase deposition method such as chemical vapor deposition. From the second polysilicon layer 504 become in further process steps, the first floating gate region 504a and the second floating gate region 504b formed (cf. 5 ). Alternatively, the second electrically conductive layer 504 also another electrically conductive material such. B. electrically conductive carbon or titanium nitride (TiN).

After forming the second polysilicon layer 504 in the ditch 501 ' becomes a part of the second polysilicon layer 504 removed by etching back, leaving the ditch 501 ' only to just below the substrate surface is filled with material, as in 8I shown.

In another, in 8J shown process step become the exposed areas of the liner layer 503 ''' removed using an etching process.

The ditch 501 ' is filled by the deposition of a layer of nitride material, and the nitride layer are spacer by an etching process 515 trained, see 8K ,

In another, in 8L shown, process step is parallel to the sidewalls of the spacer 515 etched anisotropically, thereby Material of the second polysilicon layer 504 , the third oxide layer 503 '' and the first polysilicon layer 514 is removed, and a portion of the second oxide layer 503 ' is exposed. The etching is preferably carried out by a dry etching process.

The etching also creates a first floating gate region 504a , a second floating gate area 504b , a third floating gate area 514a and a fourth floating gate region 514b educated. The first floating gate area 504a and the second floating gate region 504b become clear from the material remaining after the etching of the second polysilicon layer 504 formed while the third floating gate area 514a and the fourth floating gate region 514b from the material remaining after the etching of the first polysilicon layer 514 be formed.

In another, in 8M shown process step become the remainders of the hardmask, ie the two nitride partial layers 508a and 508b , as well as the nitride spacer 515 removed, leaving the two oxide sublayers 507a . 507b , Parts of the ditch 501 ' directed side surfaces of the first source / drain region 506a or the second source / drain region 506b and the upper surfaces of the first floating gate region 504a , the second floating gate region 504b and the fourth oxide layer 503 ''' (Liner layer 503 ''' ) are exposed.

In another, in 8N shown, process step is in the trench 501 ' a fifth oxide layer 503 '''' formed on the inner side surfaces of the floating gate regions 504 . 504b . 514a and 514b , on the exposed area of the second oxide layer 503 ' as well as on the areas exposed in the preceding process step (see the above comments on 8M ) is formed. The formation of the fifth oxide layer 503 '''' takes place by means of a deposition process (eg chemical vapor deposition), alternatively by thermal oxidation.

By forming the fifth oxide layer 503 '''' an electrically insulating area is clearly created 503 which is the floating gate areas 504a . 504b . 514a and 514b includes, cf. 8O , The electrically insulating area 503 is composed of the second oxide layer 503 ' , the third oxide layer 503 '' , the fourth oxide layer 503 ''' (Liner layer 503 ''' ) and the fifth oxide layer 503 '''' , The floating gate areas 504a . 504b . 514a and 514b be through the electrically insulating area 503 from each other and from the first source / drain region 506a , the second source / drain region 506b , the buried third bit line area 513 and the tub area 520 electrically isolated.

In another, in 8O shown process step, a third electrically conductive layer 521 made of polysilicon on the fifth oxide layer 503 '''' formed, such that the trench 501 ' is filled. From the third polysilicon layer 521 become clearly the electrical conductive area 502 or the control gate 502 the trench structure 501 as well as the word line area 510 formed, cf. 5 ,

In 8O is also the electrically insulating region 503 shown which the floating gate areas 504a . 504b . 514a and 514b also from the third polysilicon layer 521 electrically isolated.

In further process steps, the third polysilicon layer 521 structured and parts of the polysilicon layer 521 are removed by etching so that underlying portions of the electrically insulating region 503 be exposed, see 8P , In 8P are also the electrically conductive area 502 or the control gate 502 the multi-bit memory cell 500 as well as the word line area 510 shown. In addition, the finished trench structure is formed by the dotted line 501 characterized. Furthermore, a first side surface 502a as well as one of the first side surface 502a opposite second side surface 502b of the electrically conductive region 502 shown. The arrow 160 indicates the horizontal axis, which is on the side surfaces 502a . 502b of the electrically conductive region 502 is vertical. The arrow 170 indicates the vertical axis which is perpendicular to the horizontal axis 160 stands and in the in 8P shown section plane of the trench structure 501 lies.

In further process steps, the exposed parts of the electrically insulating region 503 (please refer 8P ) and on the first source / drain region 506a becomes the first bitline area 511 formed and on the second source / drain region 506b becomes the second bit line area 512 educated. Further, between the first bit line area 511 and the wordline area 510 an electrically insulating area 509a formed of oxide material, and between the second bit line region 512 and the wordline area 510 becomes an electrically insulating area 509b made of oxide material.

Overall, the results in 5 shown multi-bit memory cell 500 with the trench structure 501 ,

LIST OF REFERENCE NUMBERS

100

Multi-bit storage element

101

grave structure

101 '

dig

101a '

Side wall

101b '

ground

103 '

second oxide layer

103 ''

third oxide layer

102

electrically conductive area

102

first side surface

102b

second side surface

103

electrically insulating area

103a

first electrically insulating portion

103b

second electrically insulating portion

103c

electrically insulating edge area

104

Spacer layer

104a

first floating gate area

104b

second floating gate area

105

substratum

106

doped area

106a

first source / drain region

106b

second source / drain region

107

first oxide layer

107a

Oxide sublayer

107b

Oxide sublayer

108

Nitride layer

108a

Nitride sublayer

108b

Nitride sublayer

109a

electrically insulating area

109b

electrically insulating area

110

Word line region

111

first bitline area

112

second bitline area

120

well region

121

electrically conductive layer

130

Transition between well area and doped area

130a

Transition between well region and first source / drain region

130b

Transition between well region and second source / drain region

150

vertex

160

horizontal axis

170

vertical axis

300

diagram

301

Curve

302

Curve

310

diagram

311

Curve

312

Curve

313

Curve

320

diagram

330

diagram

331

Curve

332

Curve

500

Multi-bit storage element

501

grave structure

501 '

dig

501a '

Side wall

501b '

ground

502

electrically conductive area

503

electrically insulating area

503 '

second oxide layer

503 ''

third oxide layer

503 '' '

fourth oxide layer

503 '' ''

fifth oxide layer

504

second electrically conductive layer

504a

first floating gate area

504b

second floating gate area

505

substratum

506

doped area

506a

first source / drain region

506b

second source / drain region

507

first oxide layer

508

Nitride layer

508a

Nitride sublayer

508b

Nitride sublayer

509a

electrically insulating area

509b

electrically insulating area

510

Word line region

511

first bitline area

512

second bitline area

513

third bit line area

514

first electrically conductive layer

514a

third floating gate area

514b

fourth floating gate area

515

spacer

520

well region

521

electrically conductive layer

530

Transition between well area and doped area

530a

Transition between well region and first source / drain region

530b

Transition between well region and second source / drain region

550

vertex

Claims (36)

Multi-bit memory element ( 500 ), with a trench structure ( 501 ), comprising: • an electrically conductive region ( 502 ); • one on the electrically conductive area ( 502 ) formed electrically insulating area ( 503 ); A first in the electrically insulating region ( 503 ) formed floating gate area ( 504a ), which first floating gate region ( 504a ) at least partially over a first side surface ( 502a ) of the electrically conductive region ( 502 ) is trained; A second in the electrically insulating region ( 503 ) formed floating gate area ( 504b ), which second floating gate region ( 504b ) at least partially over a second, the first side surface ( 502a ) opposite side surface ( 502b ) of the electrically conductive region ( 502 ) is trained; A third in the electrically insulating region ( 503 ) formed floating gate area ( 514a ), which third floating gate region ( 514a ) at least partially over the first side surface ( 502a ) of the electrically conductive region ( 502 ) is trained; A fourth in the electrically insulating region ( 503 ) formed floating gate area ( 514b ), which fourth floating gate region ( 514b ) at least partially over the second side surface ( 502b ) of the electrically conductive region ( 502 ) is formed, with respect to a vertical axis ( 170 ) of the trench structure ( 501 ): • the first floating gate area ( 504a ) over the third floating gate region ( 514a ) is trained; The second floating gate area ( 504b ) over the fourth floating gate region ( 514b ) is trained; and wherein • the floating gate regions ( 504a . 504b . 514a . 514b ) through the electrically insulating region ( 503 ) from each other and from the electrically conductive region ( 502 ) are electrically isolated. Multi-bit memory element ( 500 ) according to claim 1, wherein the trench structure ( 501 ) has a U-shaped structure with a curved lower portion. Multi-bit memory element ( 500 ) according to one of claims 1 or 2, wherein the electrically insulating region ( 503 ) has a plurality of electrically insulating portions. Multi-bit memory element ( 500 ) according to claim 3, wherein the electrically insulating region ( 503 ) has an electrically insulating edge region, which electrically insulating edge region has a thickness of 6 nm ± 1 nm. Multi-bit memory element ( 500 ) according to one of claims 1 to 4, wherein the trench structure ( 501 ) along the vertical axis ( 170 ) has a maximum extension of, 200 nm ± 15 nm. Multi-bit memory element ( 500 ) according to one of claims 1 to 5, wherein the trench structure ( 501 ) along a horizontal axis ( 160 ), which horizontal axis ( 160 ) perpendicular to the first side surface ( 502a ) and the second side surface ( 502b ) of the electrically conductive region ( 502 ) has a maximum extension of 60 nm ± 5 nm. Multi-bit memory element ( 500 ) according to one of claims 1 to 6, with a substrate ( 505 ), wherein • the trench structure ( 501 ) at least partially in the substrate ( 505 ) is trained; • the electrically conductive region ( 502 ) and the floating gate areas ( 504a . 504b . 514a . 514b ) through the electrically insulating region ( 503 ) from the substrate ( 505 ) are electrically isolated. Multi-bit memory element ( 500 ) according to claim 7, which is designed as a memory cell transistor, wherein • in the substrate ( 505 ) a first source / drain region ( 506a ) and a second source / drain region ( 506b ) are formed; • the trench structure ( 501 ) at least partially between the first source / drain region ( 506a ) and the second source / drain region ( 506b ) is trained; The first source / drain region ( 506a ) and the second source / drain region ( 506b ) from the floating gate areas ( 504a . 504 . 514a . 514b ) are electrically isolated. Multi-bit memory element ( 500 ) according to claim 8, having at least partially on the first source / drain region ( 506a ) formed first bit line area ( 511 ); At least partially on the second source / drain region ( 506b ) formed second bit line area ( 512 ). Multi-bit memory element ( 500 ) according to one of claims 7 to 9, with an at least partially on the electrically conductive region ( 502 ) formed word line area ( 510 ). Multi-bit memory element ( 500 ) according to one of claims 8 to 10, wherein the first source / drain region ( 506a ) and / or the second source / drain region ( 506b ) are doped. Multi-bit memory element ( 500 ) according to any one of claims 7 to 11, with at least a portion of the trench structure ( 501 ) formed third bit line area ( 513 ). Multi-bit memory element ( 500 ) according to claim 12, wherein the third bit line region ( 513 ) on the electrically insulating region ( 503 ) is formed, such that the third bit line region ( 513 ) of the electrically conductive region ( 502 ) and the floating gate areas ( 504a . 504b . 514a . 514b ) is electrically isolated. Multi-bit memory element ( 500 ) according to one of claims 12 or 13, wherein the third bit line region ( 513 ) is doped. Multi-bit memory element ( 500 ) according to one of claims 11 to 14, wherein in the first source / drain region ( 506a ) and / or in the second source / drain region ( 506b ) and / or in the third bit line area ( 513 ) the dopant concentration increases toward the substrate surface. Multi-bit memory element ( 500 ) according to claim 15, wherein the dopant concentration is between 10 ¹⁶ cm ^-3 and 10 ²¹ cm ^-3 . Multi-bit memory element ( 500 ) according to any one of claims 7 to 16, wherein in the substrate ( 505 ) at least below the trench structure ( 501 ) a doped well area ( 520 ) is trained. Multi-bit memory element ( 500 } according to claim 17, wherein the dopant concentration in the doped well area ( 520 ) between 5 × 10 ¹⁶ cm ^-3 and 5 × 10 ¹⁷ cm ^-3 . Multi-bit memory element ( 500 ) according to one of claims 1 to 18, wherein the floating gate regions ( 504a . 504b . 514a . 514b ) Polysilicon material and / or electrically conductive carbon material and / or titanium nitride. Multi-bit memory element ( 500 ) according to one of claims 1 to 19, wherein the electrically conductive region ( 502 ) Has polysilicon material. Multi-bit memory element ( 500 ) according to one of claims 3 to 20, wherein at least one of the electrically insulating portions comprises an oxide material and / or a nitride material. Multi-bit memory element ( 500 ) according to any one of claims 7 to 21, wherein the substrate ( 505 ) of one of the following materials: • silicon, • germanium, • SiGe, • gallium arsenide, • indium phosphide, • an IV-IV semiconductor material, • a III-V semiconductor material, • an II-VI semiconductor material. Method for producing a multi-bit memory element ( 500 ) with a trench structure ( 501 ), in which • in a substrate ( 505 ) a ditch ( 501 ' ) is formed; An electrically conductive area ( 502 ) in the trench ( 501 ' ) is formed; An electrically insulating area ( 503 ) on the electrically conductive region ( 502 ) is formed; A first floating gate region ( 504a ) is formed, which at least partially over a first side surface ( 502a ) of the electrically conductive region ( 502 ) is formed; A second floating gate region ( 504b ) is formed, which at least partially over a second side surface ( 502b ) of the electrically conductive region ( 502 ) is formed; A third floating gate region ( 514a ) is formed, which at least partially over the first side surface ( 502a ) of the electrically conductive region ( 502 ) is formed; A fourth floating gate area ( 514b ) is formed, which at least partially over the second side surface ( 502b ) of the electrically conductive region ( 502 ) is formed, with respect to a vertical axis ( 170 ) of the trench structure ( 501 ): • the first floating gate area ( 504a ) over the third floating gate region ( 514a ) is formed; The second floating gate area ( 504b ) over the fourth floating gate region ( 514b ) is formed; and wherein the floating gate areas ( 504a . 504b . 514a . 514b ) are formed such that they pass through the electrically insulating region ( 503 ) from each other and from the electrically conductive region ( 502 ) are electrically isolated. Method according to claim 23, in which the electrically insulating region ( 503 ) has a plurality of electrically insulating portions. Method according to one of claims 23 or 24, in which the formation of the trench ( 501 ' ) by means of a lithography process and / or an etching process. Method according to one of Claims 23 to 25, in which a first electrically conductive layer ( 514 ) in the trench ( 501 ' ) is formed, wherein from the first electrically conductive layer ( 514 ) the third floating gate region ( 514a ) and the fourth floating gate region ( 514b ) are formed; A second electrically conductive layer ( 504 ) in the trench ( 501 ' ) is formed, wherein from the second electrically conductive layer ( 504 ) the first floating gate region ( 504a ) and the second floating gate region ( 504b ) are formed. A method according to claim 26, wherein forming the first electrically conductive layer ( 514 ) and / or forming the second electrically conductive layer ( 504 ) by means of a deposition process. Method according to one of claims 26 or 27, in which the first electrically conductive layer ( 514 ) and / or the second electrically conductive layer ( 504 ) Comprise polysilicon, electrically conductive carbon or titanium nitride. Method according to one of claims 23 to 28, wherein a first source / drain region ( 506a ) and a second source / drain region ( 506b ) be formed. The method of claim 29, wherein the first source / drain region ( 506a ) and / or second source / drain region ( 506b ). A method according to claim 30, wherein the doping is carried out by means of an ion implantation method. Method according to one of claims 23 to 31, wherein in the substrate ( 505 ) at least below the trench structure ( 501 ) a doped well area ( 520 ) is formed. The method of claim 32, wherein forming the doped well region ( 520 ) by means of an ion implantation process. Method according to one of claims 24 to 33, wherein at least one electrically insulating portion is formed as an oxide layer. Method according to one of claims 24 to 34, wherein the at least one electrically insulating portion is formed by means of a deposition method and / or a growth method and / or an oxidation method. Method according to one of claims 24 to 35, wherein after the formation of the trench ( 501 ' ) and before forming the electrically insulating region ( 503 ) a sacrificial oxide layer at least over a portion of the sidewalls ( 501a ' ) and / or the soil ( 501b ' ) of the trench ( 501 ' ) is formed.

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