CN1992285A

CN1992285A - Multi-bit memory element with groove structure and method for manufacturing same

Info

Publication number: CN1992285A
Application number: CNA2006100642954A
Authority: CN
Inventors: F·刘
Original assignee: Qimonda AG
Current assignee: Qimonda AG
Priority date: 2005-11-21
Filing date: 2006-11-21
Publication date: 2007-07-04
Also published as: DE102005055302A1; DE102005055302B4

Abstract

A multi-bit memory element comprise a trench structure comprising an electrically conductive region on which is an insulating region in or on which are at least two floating gate regions that are electrically isolated from one another and from the electrically conductive region.

Description

Multi-bit memory element having trench structure and method of manufacturing the same

Technical Field

The present invention relates to a multi-bit memory element having a trench structure and a method for manufacturing a multi-bit memory element having a trench structure.

Background

The most important sub-field in semiconductor processing is the development of memory elements or cells (memorylcells), i.e. elements for storing data, usually in the form of binary information cells, i.e. bits (binary bits). In this regard, a Write (Write) or Program (Program) memory cell is understood to mean a cell into which data (e.g., a bit) is "written", i.e., stored. Furthermore, reading (Read) or deleting (Erase) a memory cell is to be understood as reading or deleting the content of the memory cell, i.e. the stored information. Furthermore, the read/write processes are also referred to as cycles (cycles), and the Time between the start of one read/write process and the start of another read/write process is referred to as Cycle duration (Cycle Time).

An important goal in the development of Memory cells is to develop and improve so-called Non-Volatile Memory cells, that is, Memory cells, in which the Cell remains in the stored state for a very long period of time (typically ≧ 10 years) by programming/writing it once, without the need to refresh the Cell contents periodically, that is, without having to rewrite it with the same contents. For example, as the nonvolatile Memory technology, there are EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), and flash Memory.

In a typical form of NVM cell, the representation of a bit is achieved by influencing the charge state of an additional, electrically insulated gate of a Field Effect Transistor (FET) by introducing positive or negative charge carriers on the gate. This additional Gate is called an electrically Floating-Gate (Floating-Gate).

The floating gate of the memory cell transistor may be in a charged state or an uncharged state, for example. Depending on the charge state of the floating gate, the field effect transistor has a higher or lower threshold voltage, which is detected in the Read process (Read process) and is used, for example, to distinguish between two binary states ("0" and "1"). In other words, for example, a state in which the memory cell FET has a low threshold voltage can be identified with a logic "1" stored in the memory cell. The higher threshold voltage of the FET, in turn, then corresponds to a logic "0" stored in the memory cell.

Conventional NVM cells based on floating gate technology can only store one bit per cell. It is desirable to increase the number of stored bits per cell.

An alternative concept of applying a floating gate is to apply a so-called Charge storage Layer (Charge trapping Layer) or Charge Traps). In this case, charge is accumulated, for example, on the nitride layer of an oxide-nitride-oxide layer stack (ONO stack).

Currently, NVM cells can be implemented where an ONO storage layer is applied, which are capable of storing one or two bits. The latter case is also referred to as a dual Bit cell or Twin-Bit cell (e.g., dual flash memory). Generally referred to as multi-bit memory cells for memory cells that can store multiple bits.

A disadvantage when using an ONO layer is that during programming or erasing so-called Hot electrons (Hot electrons) or Hot Holes (Hot Holes), i.e. electrons or Holes with high kinetic energy, are often never introduced or injected exactly at the same location of the nitride layer. Thus, the charge distribution in or on the nitride layer may widen and/or shift during the write/read cycle of the cell.

In the case of floating gates made of a metallic material such as polysilicon, in contrast, the exact location of the charge carrier injection does not play a decisive role, since the charge itself can move freely over the metallic floating gate. Therefore, no broadening or shifting of the charge distribution occurs in this case.

As also in other fields of Semiconductor Technology, the design of the memory cell is decisively determined by the Technology Node (Technology Node) predefined in the International Technology Roadmap for Semiconductor and the requirements for continued miniaturization connected therewith.

In this regard, it is a great challenge to develop a memory Cell device (high density Cell Array) having a high memory density, that is, a memory Cell device having the largest stored information per plane, wherein the Feature Size (Feature Size F) of the memory Cell should be as small as possible at the same time.

"as small as possible" specifically means that feature sizes currently strive to reach F ≈ 60nm within the scope of developing dual bit NVM cell transistors. Particularly in developing a high density memory cell array, Two Bit Separation (Two Bit Separation) and Retention of data after one cycle (Retention) are a big challenge.

Conventional memory cell transistors are implemented as planar transistors. A disadvantage of planar transistors is that the channel length of the transistor has to be scaled by the feature size F (skalieren). However, the channel, which is becoming shorter and shorter as the device is miniaturized, has a problem in that the channel is determined by a high voltage occurring when a cell is programmed or deleted.

One possibility to avoid the problem of extremely short channel lengths is to apply so-called channel transistors with U-shaped channels (Trench transistors). In this case, the channel length does not have to scale with F.

Disclosure of Invention

The object on which the invention is based is to specify a non-volatile memory element or NVM memory cell for storing at least two bits, which has good scalability and at least partially reduces or circumvents the above-mentioned disadvantages of memory cells known from the prior art.

This problem is solved by a multi-bit memory element having a trench structure and by a method for manufacturing a multi-bit memory element having a trench structure having the features according to the independent claims.

Exemplary developments of the invention result from the dependent claims. The other refinements of the invention described in conjunction with the multi-bit memory elements are also applicable to the method for manufacturing the multi-bit memory elements in the sense that they are applicable.

A multi-bit memory element having a trench structure is provided, the multi-bit memory element having a conductive region and an electrically insulating region constructed over the conductive region. Furthermore, the trench structure has at least two floating gate regions which are formed on or in an electrically insulating region and are electrically insulated from one another and from the electrically conductive region by the electrically insulating region.

In a method for fabricating a multi-bit memory element having a trench structure, a trench is formed in a substrate. A conductive region is configured in the trench. An electrically insulating region is constructed over the electrically conductive region. Furthermore, at least two floating gate regions are formed on or in the electrically insulating region in such a way that they are electrically insulated from one another and from the electrically conductive region by the electrically insulating region.

An aspect of the present invention can be seen to provide a multi-bit storage element or multi-bit storage cell having a trench structure and at least two floating gate regions or floating gates.

A multi-bit storage element in which at least two bits can be stored simultaneously by means of at least two floating gate regions can be used as a memory cell transistor. More specifically, the multi-bit Memory device can be used as a Non-Volatile-Memory-Cell-Transistor (NVM Cell-Transistor), i.e. as a Non-Volatile Memory Cell Transistor.

An advantage of applying a trench structure is that the channel length of a multi-bit memory element constructed as a memory cell transistor does not have to be scaled in feature size. In other words, when scaling the memory cell transistors by a scaling factor f, it is not necessary to scale the channel length by the factor f. Problems associated with very short channel lengths and high programming or erase voltages can thereby be avoided. Another advantage is that each memory cell transistor can store at least two bits.

In a development of the invention, the electrically insulating region of the multi-bit memory element has a plurality of electrically insulating sub-regions.

The electrically insulating regions or electrically insulating sub-regions can be formed by means of an isolation method and/or a growth method and/or an oxidation method. As the deposition method, a vapor deposition method such as Chemical Vapor Deposition (CVD) may be applied.

According to a further development, the channel structure has a U-shaped structure with a curved lower section.

According to a further refinement, the trench structure has a first floating gate region which is formed in the electrically insulating region and which is formed at least partially above the first side of the conductive region. Furthermore, the trench structure in this refinement has a second floating gate region which is formed in the electrically insulating region and which is formed at least partially above a second side of the electrically conductive region which is located opposite the first side.

The electrically insulating region may have a first electrically insulating partition configured between the first floating gate region and the conductive region and a second electrically insulating partition configured between the second floating gate region and the conductive region.

It is obvious that the multi-bit memory element in the described modification is constructed as a double-gate memory cell with two floating gates, wherein two bits can be stored by means of two floating gates electrically insulated from each other (so-called dual-bit memory cell).

In another refinement, for example for a feature size of 60nm, the trench structure of the multi-bit storage element has a maximum elongation of 60nm ± 5nm along a horizontal axis perpendicular to the first and second sidewalls of the conductive region.

In a further development, for example for a feature size of 60nm, the trench structure has an elongation of 160nm ± 10nm along a vertical axis perpendicular to the horizontal axis.

In a further development, for example for a feature size of 60nm, the first electrically insulating partition and the second electrically insulating partition have a maximum elongation along the horizontal axis of 6nm ± 1 nm.

In a further development, for example for a feature size of 60nm, an electrically insulating edge region is formed in the electrically insulating region, which has a thickness of 6nm ± 1 nm.

According to a further refinement, for example for a feature size of 60nm, the first floating gate region and the second floating gate region each have a maximum elongation of 10nm ± 2nm along the horizontal axis.

In a further development of the invention, the multi-bit memory element has: a first floating gate region configured in the electrically insulating region, the first floating gate region configured at least partially over the first side of the electrically conductive region; a second floating gate region formed in the electrically insulating region, the second floating gate region being at least partially formed over a second side of the electrically conductive region opposite the first side; a third floating gate region formed in the electrically insulating region, the third floating gate region being at least partially formed over the first side of the electrically conductive region; and a fourth floating gate region formed in the electrically insulating region, the fourth floating gate region being at least partially formed over the second side of the conductive region. With regard to the vertical axis of the trench structure, this refinement applies: the first floating gate region is configured above the third floating gate region and the second floating gate region is configured above the fourth floating gate region.

According to a further refinement, the multi-bit storage element has a substrate, wherein the trench structure of the multi-bit storage element is at least partially structured in the substrate, and wherein the conductive region and the at least two floating gate regions are electrically insulated from the substrate by an electrically insulating region.

In a further development of the invention, the multi-bit memory element is designed as a memory cell transistor, wherein a first source/drain region and a second source/drain region are designed in the substrate, wherein a trench structure is designed at least partially between the first source/drain region and the second source/drain region, and wherein the first source/drain region and the second source/drain region are electrically insulated from the at least two floating gate regions.

In a further refinement, the first bit line region is formed at least partially on the first source/drain region, and the second bit line region is formed at least partially on the second source/drain region.

According to a further development of the invention, a word line region can be formed which is formed at least partially on the conductive region.

The first and/or second source/drain region may be doped, for example n-doped, with a dopant concentration of 10¹⁶cm^-3And 10²¹cm^-3In the meantime. The doping of the source/drain regions may be achieved by means of ion implantation methods.

In a further development of the invention, the multi-bit memory element can have a third bit line region which is formed at least over a partition of the trench structure. The third bit line region may be configured in the substrate and at least partially under a trench structure. Obviously, the third bit line region is configured as a bit line region forming a trench.

The third bitline region may be configured on a partition of the electrically insulating region such that the third bitline region is electrically insulated from the electrically conductive region and the at least two floating gate regions.

The third bit line region may be doped, for example n-doped, with a dopant concentration of 10¹⁶cm^-3And 10²¹cm^-3In the meantime.

The doping of the third bit line region can be achieved by means of ion implantation.

The shape of the doping profile in the two source/drain regions and/or in the third bitline region has a strong influence on the efficiency of the programming or erasing process in the multi-bit memory cell, similar to the dimensions of the trench structure or the dimensions of the regions (floating gate region, conductive region, electrically insulating region or electrically insulating partition) constructed in the trench structure. Whether the dimensions of the multi-bit memory cell or the trench structure or the doping pattern or doping profile are thus optimized in terms of the functionality of the multi-bit memory cell.

The advantages of the present invention can be seen herein as the ability to optimize the shape of the doping profile without having to enlarge the feature size of the multi-bit memory element.

In a further development of the invention, the dopant concentration in the first source/drain region and/or in the second source/drain region increases toward the substrate surface.

In a further development of the invention, a doped well region is formed in the substrate at least below the trench structure, wherein the doped well region is formed, for example, as a p-doped well region.

The concentration of the doping substance in the doped well region is 5 × 10¹⁶cm^-3And 5X 10¹⁷cm^-3In the meantime.

The doping of the well region may be achieved by means of ion implantation.

The at least two floating gate regions constructed in the trench structure are preferably of polysilicon material. Alternatively, the at least two floating gate regions may also have a conductive carbon material or titanium nitride (TiN).

One aspect of the present invention can be viewed as a multi-bit memory element in which introduced (injected) charge carriers (e.g., electrons) are collected or stored onto a floating gate having a conductive material such as polysilicon, a conductive carbon material, or titanium nitride (TiN).

In contrast to the prior art, in which charge carriers are concentrated onto the nitride layer of an oxide-nitride-oxide layer stack (ONO layer stack), in the case of application of a Floating gate consisting of an electrically conductive material, such as polysilicon, also called Floating-Poly (Floating polymer), in which the charge carriers reach exactly into or onto the Floating gate, this is not very critical, since the charge carriers are free to move on the metallic Floating gate.

The conductive regions formed in the trench structure may likewise have a polysilicon material.

It is apparent that the conductive region constructed in the trench structure serves as the control gate of the memory cell transistor, which is electrically insulated from the floating gate by an electrically insulating region.

The electrically insulating region may have an oxide material (e.g., silicon dioxide) or a nitride material (e.g., silicon nitride), which are collectively referred to as dielectric materials.

For the case of constructing a plurality of electrically insulating partitions in the trench structure, one or more of the electrically insulating partitions may have an oxide material (e.g., silicon dioxide) and/or a nitride material (e.g., silicon nitride).

The substrate in which the trench structure of the multi-bit memory element is constructed has, for example, one of the following materials: silicon, germanium, SiGe, gallium arsenide, indium phosphide, IV-IV-semiconductor materials, III-V-semiconductor materials, II-VI-semiconductor materials.

According to a further development of the invention, in a method for producing a multi-bit memory element having a trench structure, the structuring of the trenches is effected by means of a photolithographic method and/or an etching method.

In a further refinement, the at least two floating gate regions in the trench structure are constructed by constructing at least one spacer or at least one spacer, wherein the at least one spacer (or spacer) is constructed at least over one partition of the inner side walls of the trench.

The structuring of the at least one spacer layer can be effected by means of a segregation method. As the separation method, a Vapor Deposition method such as Chemical Vapor Deposition (CVD) can be applied.

The at least one spacer layer may have a polysilicon material. In other words, the at least one spacer layer may be structured as a polysilicon layer.

It is clear that in a method for manufacturing a multi-bit memory element by structuring at least one spacer layer (or at least one spacer) made of polysilicon material over one partition of the inner sidewalls of the trench structure, a floating polymer region, i.e. a floating gate made of polysilicon, can be structured in a simple manner.

In a further development of the invention, in the method for producing a multi-bit memory element, a sacrificial oxide layer (Operoxiditscicht) is formed after formation of the trenches and before formation of the electrically insulating regions at least over the partial regions of the sidewalls of the trenches and/or over the bottoms of the trenches.

The sacrificial oxide layer may be removed again after construction. The removal of the sacrificial oxide layer may be achieved by means of an etching method.

Drawings

Embodiments of the invention are illustrated in the drawings and described further below. In the figures like elements are provided with the same reference signs. The figures shown in the drawings are schematic and thus are not shown to scale.

FIG. 1 shows a multi-bit memory element having a trench structure in accordance with a first embodiment of the present invention.

FIG. 2A shows a simulation of electron temperature distribution during a programming process for the multi-bit storage element shown in FIG. 1.

FIG. 2B illustrates a simulation of the electric field strength distribution during the programming process for the multi-bit storage elements shown in FIG. 1.

Fig. 3A shows a time variation curve of the amount of charge on the first and second floating gate regions of the multi-bit storage element shown in fig. 1 during a programming process.

FIG. 3B illustrates current-voltage characteristics for different read processes in the multi-bit storage element of FIG. 1.

FIG. 3C illustrates current-voltage characteristics for other read processes in the multi-bit storage element of FIG. 1.

FIG. 3D illustrates the dependence of threshold voltage on source/drain potential for read-forward and read-backward processes in the multi-bit storage element of FIG. 1.

Fig. 4A to 4J show different moments during a method for manufacturing a multi-bit memory element having a trench structure according to a first embodiment of the present invention.

FIG. 5 illustrates a multi-bit memory element having a trench structure in accordance with a second embodiment of the present invention.

FIGS. 6A through 6D illustrate schematic diagrams of a programming process of the multi-bit storage element shown in FIG. 5.

FIGS. 7A through 7D illustrate a schematic diagram of a read process of the multi-bit storage element shown in FIG. 5.

Fig. 8A to 8P show different moments during a method for manufacturing a multi-bit memory element having a trench structure according to a second embodiment of the present invention.

Detailed Description

FIG. 1 shows a multi-bit memory element 100 having a trench structure 101 in accordance with a first embodiment of the present invention. The trench structure 101 has a U-shaped structure with a curved lower section, wherein the deepest point of the trench structure 101 (obviously the curved section or "U" vertex of the trench structure 101) is characterized by an arrow 150. The trench structure 101 has a conductive region 102 and an electrically insulating region 103 constructed over the conductive region 102. Furthermore, the trench structure 101 has a first floating gate region 104a and a second floating gate region 104b, which floating

gate regions

104a, 104b are constructed on or in the electrically insulating region 103, and which floating

gate regions

104a, 104b are electrically insulated from each other and from the conductive region 102 by the electrically insulating region 103.

The first floating gate region 104a and the second floating gate region 104b obviously serve as either a first or second floating gate for storing a first bit and a second bit, while the conductive region 102 obviously serves as a control gate by which the write, read and erase processes in the multi-bit memory element 100 can be controlled.

In the embodiment shown, the first floating gate region 104a is at least partially configured above a first side 102a of the conductive region 102, and the second floating gate region 104b is at least partially configured above a second side 102b of the conductive region 102, wherein the second side 102b is located opposite the first side 102 a.

The first floating gate region (first floating gate) 104a and the second floating gate region (second floating gate) 104b have a polysilicon material. Alternatively, however, the floating

gate regions

104a, 104b may also have a conductive carbon material or titanium nitride (TiN), for example.

The conductive region (control gate) 102 also has a polysilicon material.

The electrically insulating region 103 of the trench structure 101 is formed in such a way that the electrically insulating region 103 has a plurality of electrically insulating sections, wherein a first electrically insulating section 103a is formed between the first floating gate region 104a and the electrically conductive region 102, a second electrically insulating section 103b is formed between the second floating gate region 104b and the electrically conductive region 102, and wherein, in addition, an electrically insulating edge region 103c is formed.

The electrically insulating sections, i.e. the first electrically insulating section 103a, the second electrically insulating section 103b and the electrically insulating edge section 103c, are constructed of an oxide material, e.g. silicon dioxide. Thus, the electrically insulating region 103 is also referred to as gate oxide 103.

The multi-bit memory element 100 has a substrate 105, the substrate 105 being constructed as a silicon substrate. A first source/drain region 106a and a second source/drain region 106b are constructed in the substrate 105. The trench structure 101 is at least partially formed in the substrate 105 such that the trench structure 101 is at least partially formed between the first source/drain region 106a and the second source/drain region 106 b. The trench structure 101 is electrically insulated from the substrate 105 or from the first and second source/

drain regions

106a, 106b by the electrically insulating region 103, more precisely by the electrically insulating edge region 103 c.

The first source/drain region 106a and the second source/drain region 106b are doped, wherein in both regions the dopant concentration increases towards the substrate surface (illustratively "bottom-up"). In other words, the first source/drain region 106a or the second source/drain region 106b has a variable dopant profile, wherein the doping intensity increases from bottom to top.

This is illustrated by the seven regions of the first source/drain region 106a or the second source/drain region 106b shown in fig. 1, which are arranged one above the other and each have an approximately constant dopant concentration, wherein the dopant concentration increases from the lowermost region to the uppermost region.

If the first source/drain region 106a or the second source/drain region 106b is numbered consecutively from bottom to top with 1 to 7 divisions

D_{i} = 10^{n_{i}} {cm}^{- 3};

The doping intensity of the i-th zone (1. ltoreq. i. ltoreq.7) is then, for example, applied: n is more than or equal to 17₁≤17.5，17.5≤n₂≤18，18≤n₃≤18.5，18.5≤n₄≤19，19≤n₅≤19.5，19.5≤n₆≤20，20≤n₇≤20.5。

It should be noted at this point that the subdivision of the doped source region 106a or the doped drain region 106b into seven regions each having an approximately constant doping strength should be understood as merely exemplary. Other dopant profiles may also be constructed in which the exact shape of the dopant profile or the position dependence of the doping intensity in the first source/drain region 106a or the second source/drain region 106b may be optimized in terms of the functionality of the multi-bit memory element 100.

In addition, multi-bit memory element 100 has a word line region 110, which word line region 110 is at least partially formed over conductive region 102 or control gate 102. The word line region 102 serves as a word line that electrically contacts or drives the control gate 102. The word line region 110 has a polysilicon material.

Furthermore, the multi-bit memory element 100 has a first bit line region 111 and a second bit line region 112, the first bit line region 111 being configured on a portion of the source region 106a, the second bit line region 112 being configured on a portion of the second source/drain region 106 b. The first and second

bit line regions

111 and 112 function as bit lines that electrically contact or drive the first or second source/

drain regions

106a or 106 b. The first and second

bit line regions

111 and 112 have a polysilicon material.

The first bit line region 111 is electrically insulated from the word line region 110 by further electrically insulating

regions

107a, 108a and 109a, and the second bit line region 112 is electrically insulated from the word line region 110 by electrically insulating

regions

107b, 108b and 109b, wherein the electrically insulating

regions

107a, 107b, 109a and 109b have an oxide material (e.g. silicon dioxide) and the electrically insulating

regions

108a and 108b have a nitride material (e.g. silicon nitride).

The region of the substrate 105 lying below the trench structure 101, the first source/drain region 106a and the second source/drain region 106b is configured as a doped well region 120, wherein the doped well region 120 has a dopant concentration of 5 × 10¹⁶cm^-3And 5X 10¹⁷cm^-3In the meantime.

The junction between the first source/drain region 106a and the doped well region 120 of the substrate 105 is represented by a thick line 130a, and the junction between the second source/drain region 106b and the doped well region 120 of the substrate 105 is represented by a thick line 130 b. The

Junction

130a or 130b is also referred to as a bit-line Junction (Bitline-Junction).

The multi-bit memory element 100 shown in fig. 1 is obviously formed as a memory Cell Transistor having a trench structure 101 and two

polymer floating gates

104a, 104b (i.e. floating gates made of polysilicon) or as a non-volatile memory Cell Transistor (NVM Cell Transistor).

Further, the feature size of the trench structure 101 of the multi-bit memory element 100 is shown in fig. 1.

The arrow 160 characterizes an axis or direction which is perpendicular to the sidewalls 102a, 102b of the conductive region 102 and thus, for example, also parallel to the substrate surface. The shaft 160 is also referred to below as the horizontal shaft 160.

Arrow 170 represents an axis or direction that is perpendicular to horizontal axis 160 and lies in the cross-sectional plane of trench structure 101 shown in fig. 1. The axis 170 is thus perpendicular to the substrate surface and is referred to below as the vertical axis 170.

In the illustrated embodiment, for example for a feature size of 60nm, the first and second floating gate regions 140a and 140b, respectively, have a maximum extension d along the horizontal axis 160₁In which d applies₁10nm ± 2 nm. The first electrically insulating section 103a and the second electrically insulating section 103b each have a maximum extension d along the horizontal axis 160₂In which d applies₂6nm ± 1 nm. The electrically insulating edge region 103c has a thickness d₃＝6nm±1nm。The channel structure 101 has a maximum elongation d along the horizontal axis 160₄. Obviously, d₄Corresponding to the feature size of multi-bit storage element 100. In the illustrated embodiment, the characteristic dimension d₄Is 60 nm.

It should be noted at this point that feature sizes are generally not subject to tolerances, in contrast to technical quantities such as etch depth or layer thickness subject to fluctuations.

The maximum elongation of the trench structure 101 along the vertical axis 170 is 160nm + -10 nm.

By applying a positive voltage on the word line 110, it is apparent that a conductive channel is formed in the substrate 105 or in the well region 120 formed in the substrate 105, under the curved partition of the trench structure 101, wherein the length of the channel is given by the difference between the depth of the

bit line junction

130a or 130b and the depth of the trench or trench structure 101 (i.e., the apex 150 of the trench structure 101). In the embodiment shown, the channel length is about 100nm to 120 nm.

If the channel length is too large, unwanted injection of charge carriers into adjacent memory cells occurs. In the opposite case, i.e. in the case of channel lengths which are too short, similar problems arise as in planar memory elements. Accordingly, it is desirable to optimize the precise dimensions of features characterizing trench structure 101, such as channel length, in terms of the functionality of a multi-bit storage element or multi-bit memory cell 100, for example, by computer simulation.

It should therefore be noted at this point that the above-mentioned region is for the elongation d₁、d₂、d₃And d₄Must be understood as exemplary. For example, the respective modified elongation may be selected for other feature sizes.

The results of a computer simulation with which the function of the multi-bit memory element 100 described in connection with fig. 1 was investigated are shown in accordance with fig. 2A to 3D below.

FIG. 2A shows the distribution of electron temperature Te in a multi-bit storage element or memory cell transistor 100 for a programming process or under programming conditionsThe first source/drain region 106a has a potential V_s0V, wherein the second source/drain region 106b has a potential V _d5V, and wherein a potential V is applied to the word line region 110 or the control gate 102_wl3V. The region showing high electron temperature Te is near the bitline junction 130b and near the second floating gate region or second floating gate 140 b. In other words, hot electrons (HotElectrons), i.e., electrons having high kinetic energy, are preferably located near the bit line junction 130b and near the second floating gate 140 b. Therefore, this region has a high probability of injection. In other words, the probability of Hot electrons (via Channel Hot Electron Injection) reaching the second floating gate 140b is relatively high. In contrast, the probability of charge carriers or electrons being injected into the first floating gate 104a is small under the illustrated conditions because electrons in the vicinity of the first floating gate 104a have substantially only thermal energy.

Like fig. 2A, fig. 2B shows the distribution of the electric field strength E in the multi-bit storage element 100 determined by computer simulation during the programming process. The figure shows that the electric field strength E in the electrically insulating region or gate oxide 103 between the second source/drain region 106b and the word line region 110 is not high enough for dielectric breakdown. Furthermore, in the case of constructing the trench structure 101, it is possible to pass high doping (e.g., n) at the second source/drain region 106b⁺Doped) sub-regions (e.g., dopant concentration of about 10²⁰cm^-3The uppermost partition of the second source/drain region 106b, see fig. 1), the enhanced oxide growth results in a local thickening of the gate oxide, thereby additionally reducing the field strength E in this region.

The graph 300 in FIG. 3A shows the charge Q on the first (source-side) floating gate 104a of the multi-bit storage element 100 during the programming process described in connection with FIGS. 2A and 23 (i.e., under the programming conditions described above, i.e., the potential on the source/drain region or control gate)_FGTime curve of (a curve 301: "Charge on source side floating gate") and the Charge Q on the second (drain side) floating gate 104b_FGTime curve (curve)302: "charge drain side floating gate". Fig. 3A illustrates the transfer or transition characteristics of charge on the two floating

gates

104a and 104b during the programming process.

As can be seen from the curve 301 shown in the figure, no charge carriers are injected onto the first floating gate 104a (on the source side), whereas negative charge carriers, i.e. electrons, are injected onto the second floating gate 104b (on the drain side) (see curve 302). That is, through the programming process, the charge state of the second (drain-side) floating gate 104b is changed by injecting hot electrons (Channel hot electron Injection), CHE) from the Channel, while the charge state of the first (source-side) floating gate 104a remains unchanged.

The programming process of the multi-bit memory cell 100 is typically accomplished by injecting Hot electrons (Hot electrons) onto the floating gate, while erasing is accomplished by injecting Hot holes (Hot holes) onto the floating gate.

Graph 310 in FIG. 3B illustrates drain current I for different read processes in a multi-bit storage element or multi-bit memory cell 100 in a semi-logarithmic curve_d(i.e., the current flow between the source region 106a and the drain region 106 b) and the potential V applied to the word line region 110 or to the control gate 102_wlThe correlation of (c).

Curve 311, identified by "unwritten" (virgen), shows the drain current I when reading an unwritten multi-bit storage element 100 (i.e., a multi-bit storage element in which neither floating gate 104a nor 104b is loaded)_dAnd the gate potential V_wlThe correlation of (c). In this case, a potential V is applied to the second source/drain region 106b_d2.3V, and a potential V is applied to the first source/drain region 106a_S＝0V。

Curve 312, identified with "Forward read", illustrates the drain current I when reading in the forward direction for a multi-bit storage element 100 having an uncharged source side floating gate 104a and a charged drain side floating gate 104b_dAnd gridPole potential V_wlThe correlation of (c). The concept "forward read" describes that the current (more precisely the electron flow) is driven from a low potential (V) during the read-out process_S0V) to a higher potential (V)_d2.3V) to the second source/drain region 106 b.

In other words, when identifying "forward read" or "forward read", the direction refers to the direction in the programming process: in programming multi-bit memory cell 100, for example, V_S0V and V _d5V (see fig. 2A). Here, charge is injected to the second source/drain region 106b side (more precisely, to the drain side floating gate 104 b). In "read-in-the-forward", e.g. V_S0V and V_d2.3V (i.e., in the same direction as during programming, but insensitive to the injected charge).

Curve 313, identified by "reverse read", shows the drain current I when reversely reading out a multi-bit storage element 100 having an uncharged source-side floating gate 104a and a charged drain-side floating gate 104b_dAnd the gate potential V_wlThe correlation of (c). The concept "reverse sensing" describes that the current (more precisely the electron flow) is driven from a low potential (V) during the sensing process_d0V) to a higher potential (V)_S2.3V) of the first source/drain region 106 a.

In other words, at "reverse sensing" or "reverse reading", the direction again relates to the direction during programming of the multi-bit memory cell 100 (see FIG. 2A): in "reverse read" e.g. V_S2.3V and V_d0V (that is, the opposite direction to that at the time of programming, but sensitive to the injected charge).

In FIG. 3B, the threshold voltage of the multi-bit memory element 100 or memory cell transistor 100 is shown (i.e., where the meaningful drain current I is recorded)_dIs about 2 volts higher for the reverse sensing process (curve 313) than for the forward sensing process (curve 312). Thus, a plurality of bitsThe memory element 100 is capable of well separating Two bits that can be stored on the Two floating

gates

104a and 104b (Two-Bit Separation).

Graph 320 in fig. 3C shows drain current I for forward sensing of a bit stored on the drain-side floating gate 104b (bit 2) and reverse sensing of a bit stored on the source-side floating gate 104a (bit 1)_dAnd the gate potential V_wlWherein the first source/drain region 106a has a potential V at the time of forward readout_S0V and the second source/drain region 106b has a potential of 0.2V ≦ V_d4.2V, and wherein the second source/drain region 106b has a potential V during reverse readout_d0V and the first source/drain region 106a has a potential of 0.2 V.ltoreq.V_S≤4.2V。

As can be seen in the graph 320 shown in FIG. 3C, the threshold voltage V of the multi-bit storage element 100_thIn the forward direction of readout with the drain potential V_dIs significantly reduced, and in contrast, in the reverse sense, the threshold voltage V is reduced_thWith source potential V_SThe increase in (c) is only slightly reduced.

The fact just mentioned is also illustrated by the graph 330 shown in FIG. 3D, where the absolute value of the source/drain voltage | V is relative to the forward sense (curve 331: "forward read") and reverse sense (curve 332: "reverse read")_S/dL (wherein V)_S/d＝V_d-V_S) The threshold voltage V of a multi-bit storage element 100 having an uncharged source-side floating gate 104a and a charged drain-side floating gate 104b is plotted_th. Shown in graph 330, threshold voltage V_thFor a forward read process (where V_d＞V_S) With | V_S/dThe increase in | drops strongly, in contrast to the reverse read process (where V is_d＜V_S) Middle, threshold voltage V_thWith | V_S/dThe increase in | decreases only slightly.

A method for fabricating a multi-bit memory element or memory cell transistor 100 shown in fig. 1 according to an embodiment of the present invention is described below with respect to fig. 4A through 4J.

To fabricate the multi-bit memory element 100, as shown in FIG. 4A, a substrate 105 is provided, the substrate 105 being configured as a silicon substrate. On the substrate 105, a first oxide layer 107 (also referred to as Pad-oxide) is structured with the application of a segregation method. As the separation method, a vapor phase separation method such as a chemical vapor deposition method (CVD) may be applied.

Alternatively, the first oxide layer 107 or the pad oxide 107 may also be formed by thermal oxidation.

In the substrate 105, a p-doped well region 120 is furthermore constructed by introducing doping atoms.

The doping is effected by means of an ion implantation method, the so-called well implantation. The dopant concentration in the doped well region 120 may be about 5 x 10¹⁶cm^-3To 5X 10¹⁷cm^-3。

Furthermore, an n-doped region 106 is formed in the substrate 105 by introducing doping atoms. The source/

drain regions

106a and 106b are formed from this n-doped region 106 in the following method steps (see fig. 1). In the exemplary embodiment shown in fig. 4A, the configuration of the n-doped region 106 is implemented such that the dopant concentration in the doped region 106 increases toward the substrate surface (i.e., from "bottom to top"). In other words, the doped region 106 has a variable dopant profile, wherein the doping intensity increases from bottom to top.

In fig. 4A, seven regions are exemplarily shown in the doped region 106, and each of the seven regions has an approximately constant doping intensity. If the zones are numbered consecutively from 1 to 7 from bottom to top and are used

D_{i} = 10^{n_{i}} {cm}^{- 3}

It should be noted at this point that the subdivision of the doped region 106a into seven partitions each having an approximately constant doping intensity should be understood to be merely exemplary. Other dopant profiles are also constructed in which the exact shape of the dopant profile or the positional dependence of the doping intensity is optimized in terms of the functionality of the multi-bit memory element 100.

After the formation of the n-doped region 106 in the substrate 105, an annealing or so-called annealing is carried out, i.e. the doped region 106 is heated. In this case, the implanted dopant species is electrically activated.

The junction between the doped region 106 and the doped well region 120 is schematically illustrated in fig. 4A by a thick black line 130.

In a further method step, as shown in fig. 4B, a nitride layer 108 (also referred to as pad nitride) is formed on the first oxide layer 107 or the pad oxide 107, for example if a vapor deposition method such as chemical vapor deposition is used.

In a further method step, as in fig. 4C, a trench 101' is formed in the substrate 105. The trench 101 ' is configured as a U-shaped trench 101 ', the U-shaped trench 101 ' having vertical sidewalls 101a ' and a curved bottom 101b '. Arrow 150 marks the deepest point of the trench 101 'or curved bottom 101 b'. The formation of the trenches 101' can be achieved by means of a photolithographic method and an etching method, wherein the nitride layer 108 is used as a hard mask.

By forming the trench 101', a doped source region 106a and a doped drain region 106b with corresponding dopant profiles are simultaneously formed by the doped region 106. The junction between the first source/drain region 106a and the well region 120 is characterized by a thick black line 130a, and the junction between the second source/drain region 106b and the well region 120 is correspondingly characterized by a thick black line 130 b.

By forming the trench 101', two

oxide layers

107a and 107b are furthermore formed from the first oxide layer 107 and two

nitride layers

108a and 108b are formed from the nitride layer 108.

A sacrificial oxide layer (not shown) can be formed on the sidewalls 101a ' and the bottom 101b ' of the trench 101 ' in a further method step. This sacrificial oxide layer is removed again in a subsequent method step.

A second oxide layer 103 'is formed on the sidewalls 101 a' and the bottom 101b 'of the trench 101' and on the nitride sublayers 108a and 108b in a further method step illustrated in fig. 4D. The formation of the second oxide layer 103' is effected, for example, by a growth method or by thermal oxidation. A part of the second oxide layer 103' obviously constitutes a part of the gate oxide which electrically insulates the floating gate region to be structured in the further method step from the well region 120 structured in the substrate 105 and from the first source/drain region 106a and the second source/drain region 106 b. Instead of a single oxide layer 103', it is also possible to form a plurality of (electrically insulating) layers which in addition have different materials.

A spacer layer 104 is formed on the second oxide layer 103' in a further method step illustrated in fig. 4E. The structuring of the spacer layer 104 is for example realized by means of a deposition method, for example a vapor deposition method such as chemical vapor deposition. The spacer layer 104 is preferably of a polysilicon material and is therefore also referred to as a polymer spacer or polymer Liner (Poly-Liner). Alternatively, the spacer layer 104 may also be of other materials such as conductive carbon or titanium nitride (TiN).

In a further method step, which is illustrated in fig. 4F, the spacer layer 104 is anisotropically etched by means of a dry etch process (so-called spacer etch), so that the floating

gate regions

104a and 104b are constructed from polysilicon. In the example shown, a first floating gate region 104a and a second floating gate region 104b are constructed, which first floating gate region 104a and second floating gate region 104b are electrically insulated from the substrate 105 or from a doped well region 120 and a first source/drain region 106a and a second source/drain region 106b constructed in the substrate 105 by a second oxide layer 103'. The polysilicon material of the spacer layer 104 is also etched at the bottom of the trench 101' so as to form two floating gate regions (i.e., a first floating gate region 104a and a second floating gate region 104b) that are separated from each other.

The third oxide layer 103 "is constructed in another method step shown in fig. 4G over the two floating

gate regions

104a and 104b and over the layering of the second oxide layer 103'. The structuring of the third oxide layer 103 ″ can be effected by means of a deposition method (e.g. vapor deposition method, chemical vapor deposition), alternatively for example by thermal oxidation.

The third oxide layer 103 ″ together with the second oxide layer 103' form an electrically insulating region 103 in such a way that floating

gate regions

104a and 104b are formed in this electrically insulating region 103, see fig. 4J. The second oxide layer 103' and the third oxide layer 103 "obviously represent electrically insulating partitions of the electrically insulating region 103.

In a further method step, which is illustrated in fig. 4H, a layer 121 of an electrically conductive material, preferably a polysilicon material, is deposited over the entire area of the device illustrated in fig. 4G, so that the trenches 101' are filled with polysilicon material. In fig. 4H, the second oxide layer 103' and the third oxide layer 103 "are combined into an electrically insulating region 103. A conductive region 102 is formed in the trench 101' by means of an isolating layer 121, which conductive region 102 is at least partially formed between the two floating

gate regions

106a and 106b and is electrically insulated from the two floating

gate regions

106a and 106b by means of an electrical insulating region 103. In other words, the electrically insulating region 103 is configured on the electrically conductive region 102, and the floating

gate regions

106a and 106b configured in the electrically insulating region 103 are electrically insulated from each other and from the electrically conductive region 102 by the electrically insulating region 103.

The conductive region 102, which is comprised of a portion of layer 121, apparently serves as the control gate 102 of the multi-bit memory element 100 constructed as a memory cell transistor.

As can be seen from fig. 4H, the first floating gate region 106a is at least partially structured over the first side 102a of the conductive region or control gate 102, while the second floating gate region 106b is at least partially structured over the second side 102b of the conductive region or control gate 102, wherein the second side 102b is located opposite the first side 102 a.

A hard mask (not shown) is formed on the electrically conductive layer 121 in a further method step, and the electrically conductive layer 121 is structured by applying a photolithography method and an etching method, so that parts of the electrically insulating regions 103 are exposed, as shown in fig. 4I. After structuring the conductive-capable layer 121, a conductive region 110 remains, which conductive region 110 is also referred to as a word line region 110 or word line 110, which word line region 110 serves for electrically contacting a conductive region 102 or control gate 102 of a multi-bit memory element or memory cell transistor 100.

In other method steps, the floating gate polysilicon material in the trenches is separated by reactive ion etching except for the word line 110. The hard mask formed on the word line region 110 is removed and the trenches are filled with an oxide material except for the word line 110, thereby constituting electrically insulating

regions

109a and 109b, see fig. 4J. Furthermore, by removing portions of the

oxide layers

107a and 107b, the

nitride layers

108a and 108b situated thereon, and the regions of the electrically insulating region 103 which are structured thereon (for example by means of etching), a portion of the surface of the first source/drain region 106a and a portion of the surface of the second source/drain region 106b are exposed. A first bit line region 111 is configured on the exposed portion of the surface of the first source/drain region 106a, the first bit line region 111 for electrically contacting the first source/drain region 106a, and a second bit line region 112 is configured on the exposed portion of the surface of the second source/drain region 106b, the second bit line region 112 for electrically contacting the second source/drain region 106 b. The first bit line region 111 is electrically insulated from the word line region 110 by electrically insulating

regions

103, 107a, 108a, and 109a, and the second bit line region 112 is electrically insulated from the word line region 110 by electrically insulating

regions

103, 107b, 108b, and 109 b.

The multi-bit memory cell 100 with the finally constructed trench structure 101 resulting from the above-described method steps is shown in fig. 4J, and this multi-bit memory cell 100 corresponds to the multi-bit memory element 100 shown in fig. 1.

It should be noted at this point that in the above-described method, for reasons of clarity, the specification of parameter ranges for temperature steps such as inert annealing or thermal oxidation is abandoned. A generally customary parameter range can be selected in the respective process technology.

In connection with the method for manufacturing a multi-bit memory element 100 with a trench structure 101 schematically illustrated with reference to fig. 4A to 4J it is noted that under practical process conditions the gate oxide on the region with strongly n-doped (n +) silicon, i.e. the strongly doped region of the first source/drain region 106a or the second source/drain region 106b, is typically constructed almost twice as thick as the gate oxide on the region with a moderate doping. This is advantageous because it is in this region that a high electric field strength occurs (see fig. 2B). In thicker oxide layers, the electric field strength decreases.

It should furthermore be noted that the interface between the gate oxide and the silicon automatically moves in the direction of the source/drain regions when the sacrificial oxide layer is built by thermal oxidation or thermal growth and when the gate oxide is built. This is advantageous because the channel length is thereby enlarged, while the opening of the trench or trench structure, which is related to the feature size, is not enlarged.

In the schematic illustrations of fig. 1 and 4J, electrically insulating edge region 103c has a double thickness near apex 150 of trench structure 101. The reason for this is that, in the embodiment shown, the third oxide layer 103 ″ is structured with the application of a segregation method (see fig. 4G). In contrast, if the third oxide layer 103 "is formed by thermal oxidation, the above-described effect of a" double-thick "oxide layer does not occur.

Fig. 5 shows a multi-bit memory element 500 having a trench structure 501 according to a second embodiment of the present invention. The trench structure 501 has a U-shaped structure with a curved lower section, wherein the deepest point of the trench structure 501 (illustratively, the curved section or "U" vertex of the trench structure 501) is characterized by an arrow 550.

The trench structure 501 has a conductive region 502 and an electrically insulating region 503 configured on the conductive region 502. Furthermore, the trench structure 501 has a first floating gate region 504a, a second floating gate region 504b, a third floating gate region 514a and a fourth floating gate region 514b, which are structured in the electrically insulating region 503 and are electrically insulated from each other and from the electrically conductive region 502 by the electrically insulating region 503.

The four floating

gate regions

504a, 504b, 514a and 514b obviously function as floating gates for storing four bits, while the conductive region 502 obviously functions as a control gate by which the write, erase and read processes in the multi-bit storage element 500 can be controlled.

Similar to fig. 1, the arrow 160 identifies a horizontal axis that is perpendicular to the sidewalls 502a, 502b of the conductive region 502. The vertical axis, indicated by arrow 170, is perpendicular to the horizontal axis and lies in the cross-sectional plane of the trench structure 501 shown in fig. 5.

In the illustrated embodiment, the first floating gate region 504a and the third floating gate region 514a are configured at least partially over the first side 502a of the conductive region 502, while the second floating gate region 504b and the fourth floating gate region 514b are configured at least partially over the second side 502b of the conductive region 502, where the second side 502b is opposite the first side 502 a. Further, with respect to the vertical axis 170 of the trench structure, the first floating gate region 504a is configured above the third floating gate region 514a, and the second floating gate region 504b is configured above the fourth floating gate region 514 b.

The four floating gate regions (floating gates) 504a, 504b, 514a and 514b have polysilicon material. Alternatively, however, these floating gates may also be provided with conductive carbon material or silicon nitride (TiN), for example.

The conductive region (control gate) 502 also has a polysilicon material.

Electrically insulating region 503 is constructed of an oxide material (e.g., silicon dioxide). Thus, the electrically insulating region 503 is also referred to as a gate oxide 503.

The electrically insulating region 503 typically has a dielectric material.

The multi-bit memory element 500 has a substrate 505, the substrate 505 being constructed as a silicon substrate. A first source/drain region 506a and a second source/drain region 506b are constructed in substrate 505. The trench structure 501 is formed in the substrate 505 in such a way that the trench structure 501 is formed at least partially between the first source/drain region 506a and the second source/drain region 506 b. The trench structure 501 is electrically insulated from the substrate 505 or from the first and second source/

drain regions

506a, 506b by an electrically insulating region 503.

First source/drain region 506a and second source/drain region 506b are doped, wherein in both regions the dopant concentration increases towards the substrate surface (illustratively "bottom up"). In other words, first source/drain region 506a or second source/drain region 506b has a variable dopant profile, wherein the doping strength increases from bottom to top.

This is illustrated by the six segments of the first source/drain region 506a or the second source/drain region 506b shown in fig. 5, which are arranged one above the other and each have an approximately constant dopant concentration, wherein the dopant concentration increases from the lowermost segment to the uppermost segment.

If the partitions of first source/drain region 506a or second source/drain region 506b are numbered consecutively from bottom to top with 1 to 6 and

D_{i} = 10^{n_{i}} {cm}^{- 3}

the doping intensity of the i-th zone (1. ltoreq. i. ltoreq.6) is then, for example, applied: n is more than or equal to 17.5₁≤18，18≤n₂≤18.5，18.5≤n₃≤19，19≤n₄≤19.5，19.5≤n₅≤20，20≤n₆≤20.5。

It should be noted at this point that the subdivision of the doped source region 506a or the doped drain region 506b, respectively, into six regions each having an approximately constant doping strength should be understood as merely exemplary. Other dopant profiles can also be constructed in which the exact shape of the dopant profile or the positional dependence of the doping intensity in the first source/drain region 506a or the second source/drain region 506b can be optimized with respect to the functionality of the multi-bit memory element 500.

In addition, multi-bit storage element 500 has a word line region 510, the word line region 510 being at least partially constructed over conductive region 502 or control gate 502. The word line region 502 serves as a word line that electrically contacts or drives the control gate 502. The word line region 510 has polysilicon material.

In addition, multi-bit storage element 500 has a first bit line region 511 and a second bit line region 512, the first bit line region 511 being configured on a portion of first source/drain region 506a, and the second bit line region 512 being configured on a portion of second source/drain region 506 b. First bit line region 511 and second bit line region 512 serve as bit lines that electrically contact or drive first source/drain region 506a or second source/drain region 506 b. The first and second

bit line regions

511 and 512 have a polysilicon material.

The first bit line region 511 is electrically insulated from the word line region 510 by an electrically insulating region 509a, and the second bit line region 512 is electrically insulated from the word line region 510 by an electrically insulating region 509b, wherein the electrically insulating

regions

509a and 509b are of an oxide material. The electrically insulating

regions

509a and 509b are typically of a dielectric material.

In addition, the multi-bit storage element 500 has a third bit line region 513, the third bit line region 513 being configured on a lower partition of the trench structure 501. As shown in fig. 5, the third bit line region 513 is partially constructed under the trench structure 501 and is thus also referred to as a buried bit line region.

The third bitline region 513 is configured on a section of the electrically insulating region 503 such that the third bitline region 513 is electrically insulated from the conductive region 502 and the four floating

gate regions

504a, 504b, 514a and 514b are electrically insulated.

The third bit line region 513 is n-doped, wherein the dopant concentration is 10¹⁷cm^-3And 10²¹cm^-3And the dopant profile is in the third bit line regionRepresented by contour lines: the dopant concentration in the third bitline region 513 decreases from the inside outwards, in other words the region of the third bitline region 513 defined by the surface and the innermost contour of the trench structure has the highest dopant concentration (10)²¹cm^-3) And the dopant concentration in the adjoining partition of the third bit line region 513 is reduced.

The doping of the third bit line region 513 may be realized, for example, by means of an ion implantation method. Alternatively, doping can be achieved by out-diffusion from a material that functions as a source of dopant species.

The partition of the substrate 505 underlying the trench structure 501, the first source/drain region 506a and the second source/drain region 506b is configured as a p-doped well region 520, wherein the doped well region 520 has a dopant concentration of 5 × 10¹⁶cm^-3And 5X 10¹⁷cm^-3In the meantime.

The junction between the first source/drain region 506a and the doped well region 502 of the substrate 505 is represented by a thick line 530a, and the junction between the second source/drain region 506b and the doped well region 502 of the substrate 505 is represented by a thick line 530 b. The

Junction

530a or 530b is also referred to as a bit-line Junction (Bitline-Junction).

The multi-bit storage element 500 shown in fig. 5 is apparently constructed as a non-volatile memory cell (NVM cell) having a trench structure 501 and four polymeric floating

gates

504a, 504b, 514a and 514b (i.e., floating gates made of polysilicon) for storing four bits. The multi-bit memory element 500 or the multi-bit memory cell 500 obviously has two vertical MOS field-corresponding transistors (MOSFETs) with three bit line regions or bit

lines

511, 512 and 513, wherein the third bit line 513 is constructed as a buried bit line.

The trench structure 501 has a maximum elongation d along the horizontal axis 160, for example with a feature size of 60nm₄60nm ± 5 nm. Obviously, d₄Corresponding to the feature size of multi-bit storage element 500.

Furthermore, the trench structure 501 has a maximum elongation along the vertical axis 170 of, for example, 200nm ± 15nm for an F ═ 60 nm.

When a positive voltage is applied to the word line 510, a first conduction channel is formed between the first source/drain region 506a and the third bit line region 513, in the substrate 505 or in a well region 520 formed in the substrate 505, while a second conduction channel is formed between the second source/drain region 506b and the third bit line region 513, in the substrate 505 or in a well region 520 formed in the substrate 505.

It is necessary in the functionality of the multi-bit memory cell 500 to optimize the precise dimensions of the characterizing features of the trench structure 501, such as optimizing the lengths of the first and second conductive channels, the dimensions of the floating

gates

504a, 504b, 514a and 514b, etc., for example, by computer simulation.

It should therefore be noted here that the above-described values for the elongation of the multi-bit memory cell 500 along the horizontal axis 160 or along the vertical axis 170 must be understood as exemplary. For other feature sizes, the elongation may be selected to be correspondingly modified.

The manner in which the multi-bit memory cell 500 shown in fig. 5 functions, more precisely the implementation of the programming process and the reading process, is schematically illustrated in more detail in accordance with fig. 6A to 7D below.

It is apparent that the multi-bit memory cell 500 has two vertical transistors (MOSFETs) with a common control gate 502 and a common bit line (i.e. the buried third bit line 513). Programming of the multi-bit memory cell 500 is achieved by injecting Hot electrons onto the floating gate (Channel Hot electron injection), while erasing is achieved by injecting Hot holes (Hot Hole) onto the floating gate.

The precise voltage conditions for the write/read process or the erase process and the precise dimensions of the multi-bit memory cell 500 can be optimized. For example, quantum mechanical tunneling of electrons through the electrically insulating region 503 (Fowler-Nordheim tunneling) is suppressed.

The basic principle when operating the multi-bit memory cell 500 is that during operation of one of the two vertical transistors on one side of the trench or trench structure 501 (e.g. to perform a programming, erasing or reading process), that transistor is "deactivated" on the other side of the trench structure 501. Deactivation of the transistor is achieved in that the belonging upper bit line (i.e. the first bit line region 511) in case of a "left" transistor, the second bit line region 512 in case of a "right" transistor, and thus the first source/drain region 506a or the drain region 506b are brought to the same potential as the buried bit line 513.

FIG. 6A illustrates a programming process ("programming") in a multi-bit storage element 500 in which the charge state of the first floating gate 504a is changed by injecting hot electrons (characterized by the arrow "hot electron Injection"). Here, a potential of about +5V is applied to the first source/drain region 506a, a potential of about +4V is applied to the control gate 502, and a potential of 0V is applied to the second source/drain region 506b and the third bit line region 513, respectively.

By positive biasing of the first source/drain region 506a with respect to the third bitline region 513, it is apparent that electrons of the "left-adjacent" trench structure are accelerated in the direction of the first source/drain region 506a and are simultaneously accelerated in the direction of the trench structure by positive biasing of the control gate 502. In the vicinity of the first floating gate region 504a, the electrons have sufficient kinetic energy to reach the first floating gate 504a through the electrically insulating region 503 (arrow "hot electron injection"), whereby the charge state of the first floating gate 504a is changed. The kinetic energy of the electrons is not yet sufficient to cause injection of electrons into the third floating gate 514a near the third floating gate 514 a.

Since second source/drain region 506b has the same potential (i.e., 0V) as third bit line region 513, any significant Heating of Electrons located there (characterized by the double arrow "No Heating of Electrons") does not occur in the region of the "right adjacent" trench structure, and thus No electron injection occurs on second floating gate 504b or fourth floating gate 514 b. Obviously, the right vertical transistor of multi-bit memory cell 500 is deactivated.

FIG. 6B shows a programming process ("Program") of a multi-bit memory cell 500 similar to that of FIG. 6A, in which the charge state of the second floating gate 504B is changed. Unlike fig. 6A, in fig. 6B, the potentials of the source region 506A and the drain region 506B are interchanged, so that injection of hot electrons occurs onto the second floating gate 504B, and the left vertical transistor of the multi-bit memory cell 500 is deactivated. Fig. 6C shows another programming process ("Program") for the multi-bit memory cell 500, in which the charge state of the third floating gate 514a is changed by injecting Hot electrons (characterized by the arrow "Hot Electron Injection"). In contrast to the programming process shown in fig. 6A, the potential (0V) of the first source/drain region 506A and the potential (+5V) of the third bitline region 513 are exchanged here, so that it is apparent that electrons of the "left-adjacent" trench structure accelerate in the direction of the third bitline region 513 and have a sufficiently high kinetic energy in the vicinity of the third floating gate 514a in order to reach the third floating gate 514 a. Furthermore, the same potential as that on the third bit line region 513 (i.e., +5V) is applied to the second source/drain region 506b, so that No Heating of Electrons of the "right adjacent" trench structure occurs (characterized by the double arrow "No Heating of Electrons"). Obviously, the right vertical transistor is deactivated.

FIG. 6D shows a programming process ("Program") of the multi-bit memory cell 500 similar to that of FIG. 6C, wherein the charge state of the fourth floating gate 514b is changed. Unlike fig. 6C, in fig. 6D, the potential of the source region 506a and the potential of the drain region 506b are interchanged, so that hot electron injection occurs on the fourth floating gate 514b and the left vertical transistor is deactivated.

Fig. 7A illustrates a reverse read process ("reverse read") in the multi-bit memory cell 500, in which the charge state of the first floating gate 504a is determined (read out). For this purpose, a potential of 0V is applied to the first source/drain region 506a, a potential of +2V is applied to the second source/drain region 506b, a potential of +3V is applied to the control gate 502, and a potential of +2V is applied to the third bit line region 513. Since the second source/drain region 506b has the same potential (i.e., +2V) as the third bit line region 513, the right vertical transistor is deactivated.

Fig. 7B illustrates a reverse read process ("reverse read") in the multi-bit memory cell 500, wherein the charge state of the second floating gate 504B is determined (read) similar to the situation shown in fig. 7A. Thus, unlike the case shown in fig. 7A, here the potential of the source region 506a and the potential of the drain region 506b are interchanged, and the left vertical transistor is deactivated.

Fig. 7C illustrates a reverse read process ("reverse read") in the multi-bit memory cell 500, in which the charge state of the third floating gate 514a is determined (read out). To this end, a potential of +2V is applied to the first source/drain region 506a, a potential of 0V is applied to the second source/drain region 506b, a potential of +3V is applied to the control gate 502, and a potential of 0V is applied to the third bit line region. Since the second source/drain region 506b has the same potential (i.e., +2V) as the third bit line region 513, the right vertical transistor is deactivated.

Fig. 7D illustrates a reverse read process ("reverse read") in the multi-bit memory cell 500, in which the charge state of the fourth floating gate 514b is determined (read out) similar to the situation illustrated in fig. 7C. Thus, unlike the case shown in fig. 7C, here the potentials of the source region 506a and the drain region 506b are interchanged, and the left vertical transistor is deactivated.

It should be noted in connection with the description of fig. 7A to 7D that only the Reverse Read process ("Reverse Read") is illustrated in the figures, since only this Reverse Read process is sensitive to the injected charge.

As already described in connection with multi-bit storage element 100 having two floating gates, it generally applies that in identifying "forward read" and "reverse read," the directions relate to the programming directions (see the description for FIG. 3B).

A method for manufacturing the multi-bit memory element 500 or the memory cell transistor 500 shown in fig. 5 according to an embodiment of the present invention is described below with reference to fig. 8A to 8P.

To fabricate the multi-bit memory element 500, a substrate 505 is raised, as shown in FIG. 8A, the substrate 505 being configured as a silicon substrate. For example, if a separation method is used, a first oxide layer 507 (also referred to as pad oxide) is formed on the substrate 505.

As the separation method, a vapor phase separation method such as a chemical vapor deposition method (CVD) can be applied.

Alternatively, the first oxide layer 507 or the pad oxide 507 can also be formed by thermal oxidation.

Furthermore, a p-doped well region 520 is formed in the substrate 505 by introducing doping atoms. The doping is carried out by means of ion implantation (so-called well implantation) and the concentration of the dopant in the doped well region 520 is 5 × 10¹⁶cm^-3And 5X 10¹⁷cm^-3In the meantime.

Furthermore, an n-doped region 506 is formed in the substrate 505 by introducing doping atoms, from which doped region 506 source/

drain regions

506a and 506b are formed in a method step described below (see fig. 5). In the embodiment shown in fig. 8A, the configuration of the doped region 506 is implemented such that the dopant concentration in the doped region 506 rises toward the substrate surface (i.e., from "down to up"). In other words, the doped region 506 has a variable dopant profile, wherein the doping intensity increases from bottom to top.

In fig. 8A, six partial regions are illustrated by way of example in the n-doped region 506, each having an approximately constant doping intensity. If the zones are numbered consecutively from bottom to top with 1 to 6 and are used

D_{i} = 10^{n_{i}} {cm}^{- 3}

It should be noted at this point that the subdivision of the doped region 506a into six partitions each having an approximately constant doping intensity should be understood to be merely exemplary. Other dopant profiles may also be constructed in which the exact shape of the dopant profile or the positional dependence of the doping intensity is optimized with respect to the functionality of the multi-bit memory element 500.

After the formation of the doped region 506 in the substrate 505, an annealing or so-called annealing is carried out, i.e. a heating of the doped region 506 is effected. In this case, the implanted dopant species is electrically activated.

The junction between the doped region 506 and the doped well region 520 is schematically illustrated in fig. 8A by a thick black line 530.

In a further method step, as shown in fig. 8B, a nitride layer 508 (also referred to as pad nitride) is formed on the first oxide layer 507 or the pad oxide 507, for example in the case of application of a vapor deposition method such as a chemical vapor deposition method (CVD).

In a further method step, as shown in fig. 8C, a trench 501' is formed in the substrate 505. The trench 501 ' is configured as a U-shaped trench 501 ', the U-shaped trench 501 ' having vertical sidewalls 501a ' and a curved bottom 501b '. Arrow 550 marks the deepest point of the trench 501 'or curved bottom 501 b'. The formation of the trench 501' can be achieved by means of a photolithography method and an etching method, wherein the nitride layer 508 serves as a hard mask.

By forming the trench 501', a doped source region 506a and a doped drain region 506b with corresponding dopant profiles are simultaneously formed by the doped region 506. The junction between first source/drain region 506a and well region 520 is characterized by thick line 530a, and the junction between second source/drain region 506b and well region 520 is correspondingly characterized by thick line 530 b.

Furthermore, by structuring the trench 501', two

oxide sublayers

507a and 507b are formed by the first oxide layer 507, and two nitride sublayers 508a and 508b are formed by the nitride layer 508 or the hard mask 508.

A sacrificial oxide layer (not shown) is formed in a further method step on the sidewalls 501a ' and the bottom 501b ' of the trench 501 '.

The third bit line region 513 is constructed with another method step shown in fig. 8D. The third bitline region 513 is configured on a lower subsection of the trench 501 'and partially below the trench 501'. Thus, the third bit line region 513 is apparently configured as a buried bit line region.

The third bit line region 513 is n-doped with a dopant concentration of 10¹⁷cm^-3And 10²¹cm^-3And the dopant profile in the third bitline region 513 is represented by the contour lines: the dopant concentration in the third bitline region 513 decreases from the inside to the outside, in other words the region of the third bitline region 513 defined by the surface and the innermost contour of the trench has the highest dopant concentration (10)²¹cm^-3) And the dopant concentration in the adjacent partition of the third bitline region 513 decreases.

The doping of the third bit line region 513 is achieved by means of an ion implantation method. Alternatively, the doping is achieved by out-diffusion from a material acting as a source of dopant species.

After the formation of the doped bit line regions 513 in the substrate 505, a tempering or so-called annealing is effected, i.e. a heating of the doped bit line regions 513 is effected. In this case, the implanted dopant species is electrically activated.

The sacrificial oxide layer is removed after the bit line anneal.

A second oxide layer 503 'is formed in a further method step on the sidewalls 501 a' and the bottom 501b 'of the trench 501' and on the

nitride sub-layers

508a and 508 b. The formation of the second oxide layer 503' is preferably effected by a growth method or by thermal oxidation. A portion of the second oxide layer 503' obviously constitutes a portion of the gate oxide that electrically insulates the floating gate region to be constructed in further method steps from the well region 520, the first source/drain region 506a, the second source/drain region 506b and the third bitline region 513 constructed in the substrate 505. Instead of a single oxide layer 503', it is also possible to form a plurality of (electrically insulating) layers, which, in addition, have different materials.

A first conductive layer 514 made of a polysilicon material is formed in a further method step on the second oxide layer 503 'in such a way that the trenches 501' are filled with the first polysilicon layer 514. The construction of the first polysilicon layer 514 is preferably accomplished by a segregation method, for example a vapor segregation method such as chemical vapor deposition. The third and fourth floating

gate regions

514a, 514b are formed from the first polysilicon layer 514 in further method steps (see fig. 5). Alternatively, the first conductive layer 514 may also be of another conductive material such as conductive carbon or titanium nitride (TiN).

After first polysilicon layer 514 is constructed in trench 501 ', a portion of first polysilicon layer 514 is removed by a return etch (zurueckaetzen) so that the polysilicon material of layer 514 remains only in the lower region of trench 501', as shown in fig. 8E.

I.e. the formation of recesses (processes) is obviously carried out, wherein the formation of the recesses is carried out by means of methods known from DRAM Deep Trench technology (DRAM-Deep-Trench-technology).

In a further method step shown in fig. 8F, third oxide layer 503 ″ is deposited over first polysilicon layer 514 and over second oxide layer 503 'so that trench 501' is refilled with oxide material.

In a further method step shown in fig. 8G, parts of the oxide material of the third oxide layer 503 ″ and of the second oxide layer 503 'are removed by etching, so that a Recess (process) is formed again, wherein, however, the oxide material of the second oxide layer 503' and of the third oxide layer 503 ″ is now formed on the first polysilicon layer 514. When the oxide material is removed by etch back, portions of the nitride sublayers 508a, 508b and sidewalls 501a ', 501b ' of the trench 501 ' are also exposed.

In a further method step, fourth oxide layer 503 * or pad layer 503 * is formed on the exposed

nitride sublayers

508a and 508b and on the exposed parts of the side walls 501a ', 501b ' of the trench 501 ' by applying a deposition method (for example chemical vapor deposition), so that the device shown in fig. 8H results.

A second conductive layer 504 made of a polysilicon material is formed in a further method step on the third oxide layer 503 ″ and the liner layer 503 * in such a way that the trench 501' is filled with the second polysilicon layer 504. The construction of the second polysilicon layer 504 is again preferably accomplished by a segregation method (e.g., a vapor segregation method such as chemical vapor deposition). The first floating gate region 504a and the second floating gate region 504b are formed from the second polysilicon layer 504 in further method steps (see fig. 5). Alternatively, the second electrically conductive layer 504 may also be of another electrically conductive material, such as electrically conductive carbon or titanium nitride (TiN). After the second polysilicon layer 504 is formed in the trench 501 ', a portion of the second polysilicon layer 504 is removed by a etch back so that the trench 501' is filled with material only up to about a bit below the substrate surface, as shown in fig. 8I.

In another method step shown in fig. 8J, the exposed areas of the pad layer 503 * are removed by applying an etching method.

The trenches 501' are filled by isolating a layer made of a nitride material and spacers 515 are constructed from the nitride layer by means of an etching method, see fig. 8K.

In a further method step shown in fig. 8L, spacers 515 are anisotropically etched parallel to the side walls, thereby removing the material of second polysilicon layer 504, third oxide layer 503 ″ and first polysilicon layer 514 and exposing sections of second oxide layer 503'. The etching is preferably effected by a dry etching method.

In addition, the first, second, third and fourth floating

gate regions

504a, 504b, 514a and 514b are constructed by this etching. The first and second floating

gate regions

504a, 504b are apparently comprised of the material of the second polysilicon layer 504 that remains after the etch, while the third and fourth floating

gate regions

514a, 514b are comprised of the material of the first polysilicon layer 514 that remains after the etch.

The remaining hard mask, i.e., the two

nitride layers

508a and 508b and the nitride spacer 515, are removed in another method step shown in fig. 8M so as to expose the two

oxide layers

507a, 507b, the portion of the side of the first or second source/

drain region

506a, 506b aligned toward the trench 501', and the upper surfaces of the first, second and fourth oxide layers 503 * (spacer layer 503 *).

A fifth oxide layer 503 "", which is formed on the inner side surfaces of floating

gate regions

504a, 504b, 514a and 514b, on the exposed regions of second oxide layer 503 ', and on the regions exposed in the above-described method steps (see the above description for fig. 8M), is formed in trench 501' in another method step shown in fig. 8N. The structuring of the fifth oxide layer 503 "" is realized by means of a segregation method, such as chemical vapor deposition, alternatively by thermal oxidation.

By structuring the fifth oxide layer 503' it is apparent that electrically insulating regions 503 are formed, which electrically insulating regions 503 surround the floating

gate regions

504a, 504b, 514a and 514b, see FIG. 8O. The electrically insulating region 503 is comprised of the second oxide layer 503', the third oxide layer 503 ", the fourth oxide layer 503 * (the pad layer 503 *), and the fifth oxide layer 503". The floating

gate regions

504a, 504b, 514a, and 514b are electrically isolated from each other and from the first source/drain region 506a, the second source/drain region 506b, the buried third bitline region 513, and the well region 520 by electrically insulating regions 503.

A third conductive layer 521 made of polysilicon is formed on the fifth oxide layer 503 "", in a further method step shown in fig. 8O, in such a way that the trenches 501' are filled. The conductive region 502 or control gate 502 and word line region 510 of the trench structure 501 are apparently formed by the third polysilicon layer 521, see fig. 5.

Furthermore, electrically insulating regions 503 are shown in fig. 8O, which electrically insulating regions 503 also electrically insulate the floating

gate regions

504a, 504b, 514a and 514b from the third polysilicon layer 521.

The third polysilicon layer 521 is structured in a further method step and portions of the polysilicon layer 521 are removed by etching so that underlying portions of the electrically insulating layer 503 are exposed, see fig. 8P. In addition, the conductive regions 502 or control gates 502 and word line regions 510 of the multi-bit memory cell 500 are shown in FIG. 8P. The finally constructed trench structure is also indicated by the dashed line 501. Furthermore, a first side 502a of the conductive area 502 and a second side 502b located opposite the first side 502a are shown. The arrow 160 represents a horizontal axis that is perpendicular to the sides 502a, 502b of the conductive region 502. Arrow 170 represents a vertical axis that is perpendicular to horizontal axis 160 and lies in the cross-sectional plane of trench structure 501 shown in fig. 8P.

Other method steps remove the exposed portions of the electrically insulating regions 503 (see fig. 8P) and construct first bit line regions 511 on the first source/drain regions 506a and second bit line regions 512 on the second source/drain regions 506 b. Further, an electrically insulating region 509a made of an oxide material is configured between the first bit line region 511 and the word line region 510, and an electrically insulating region 509b made of an oxide material is configured between the second bit line region 512 and the word line region 510.

In total, the multi-bit memory cell 500 with the trench structure 501 shown in fig. 5 results.

Claims

1. A multi-bit memory element having a trench structure with

A conductive region;

an electrically insulating region configured on the electrically conductive region;

a first floating gate region configured in the electrically insulating region, the first floating gate region being configured at least partially over the first side of the electrically conductive region;

a second floating gate region formed in the electrically insulating region, which second floating gate region is at least partially formed over a second side of the electrically conductive region, which second side is located opposite the first side;

a third floating gate region configured in the electrically insulating region, the third floating gate region being configured at least partially over the first side of the electrically conductive region;

a fourth floating gate region configured in the electrically insulating region, the fourth floating gate region being configured at least partially over the second side of the electrically conductive region,

wherein, with respect to the vertical axis of the trench structure:

the first floating gate region is configured above the third floating gate region;

the second floating gate region is configured above the fourth floating gate region; and

wherein,

the floating gate regions are electrically insulated from each other and from the conductive region by the electrically insulating region.

2. The multi-bit storage element of claim 1,

the channel structure has a U-shaped configuration with a curved lower section.

3. The multi-bit storage element of claim 1,

the electrically insulating region has a plurality of electrically insulating subsections.

4. The multi-bit storage element of claim 3,

at least one of the plurality of electrically insulating segments has a maximum elongation of 6nm ± 1nm along a horizontal axis perpendicular to the first and second sides of the conductive region.

5. The multi-bit storage element of claim 3,

the electrically insulating region has an electrically insulating edge region having a thickness of 6nm ± 1 nm.

6. The multi-bit storage element of claim 1,

the trench structure has a maximum elongation along the vertical axis of 200nm ± 15 nm.

7. The multi-bit storage element of claim 1,

the trench structure has a maximum elongation of 60nm ± 5nm along a horizontal axis that is perpendicular to the first and second sides of the conductive region.

8. The multi-bit storage element of claim 1, having a substrate, wherein,

the trench structure is at least partially structured in the substrate;

the conductive region and the floating gate region are electrically insulated from the substrate by an electrically insulating region.

9. The multi-bit storage element of claim 8, configured as a memory cell transistor, wherein,

constructing a first source/drain region and a second source/drain region in the substrate;

a trench structure is at least partially constructed between the first source/drain region and the second source/drain region;

the first source/drain region and the second source/drain region are electrically insulated from the floating gate region.

10. The multi-bit storage element of claim 9 having,

a first bit line region at least partially formed on the first source/drain region;

a second bit line region at least partially configured on the second source/drain region.

11. The multi-bit storage element of claim 9,

having a word line region at least partially configured over a conductive region.

12. The multi-bit storage element of claim 9,

the first source/drain region and/or the second source/drain region is doped.

13. The multi-bit storage element of claim 12,

in the first source/drain region and/or in the second source/drain region, the dopant concentration increases towards the substrate surface.

14. The multi-bit storage element of claim 13,

the concentration of the doping substance is 10¹⁶cm^-3And 10²¹cm^-3In the meantime.

15. The multi-bit storage element of claim 10,

having a third bitline region configured at least over a section of the trench structure.

16. The multi-bit storage element of claim 15,

the third bitline region is configured on the electrically insulating region such that the third bitline region is electrically insulated from the conductive region and the floating gate region.

17. The multi-bit storage element of claim 15,

the third bit line region is doped.

18. The multi-bit storage element of claim 17,

in the third bit line region, the dopant concentration increases toward the substrate surface.

19. The multi-bit storage element of claim 18,

20. The multi-bit storage element of claim 8,

in the substrate, a doped well region is constructed at least below the trench structure.

21. The multi-bit storage element of claim 20,

22. The multi-bit storage element of claim 1,

the floating gate region has a polysilicon material and/or a conductive carbon material and/or titanium nitride.

23. The multi-bit storage element of claim 1,

the conductive region has a polysilicon material.

24. The multi-bit storage element of claim 3,

at least one electrically insulating partition has an oxide material and/or a nitride material.

25. The multi-bit storage element of claim 8,

the substrate has one of the following materials:

silicon;

germanium;

·SiGe；

gallium arsenide;

indium phosphide;

IV-IV-semiconductor materials;

III-V-semiconductor materials;

II-VI-semiconductor materials.

26. A method for fabricating a multi-bit memory element having a trench structure, wherein,

forming a trench in the substrate;

constructing a conductive region in the trench;

constructing electrically insulating regions on the electrically conductive regions;

forming a first floating gate region at least partially over the first side of the conductive region;

forming a second floating gate region, which is at least partially formed over the second side of the conductive region;

-forming a third floating gate region, which third floating gate region is at least partly formed over the first side of the conductive region;

-forming a fourth floating gate region, which fourth floating gate region is at least partly formed over the second side of the conductive region;

wherein, with respect to the vertical axis of the trench structure:

wherein the floating gate regions are configured such that the floating gate regions are electrically insulated from each other and from the conductive region by the electrically insulating region.

27. The method of claim 26, wherein,

28. The method of claim 26, wherein,

the structuring of the trenches is achieved by means of a photolithographic method and/or an etching method.

29. The method of claim 26, wherein,

the floating gate region is constructed by constructing at least one spacer layer, wherein the at least one spacer layer is constructed at least over a section of the sidewall of the trench structure.

30. The method of claim 29, wherein,

the structuring of the at least one spacer layer is effected by means of a segregation method.

31. The method of claim 29, wherein,

the at least one spacer layer has a polysilicon material.

32. The method of claim 26, wherein,

the first source/drain region and the second source/drain region are configured in the substrate.

33. The method of claim 32, wherein,

the first source/drain region and/or the second source/drain region is doped.

34. The method of claim 33, wherein,

the doping is effected by means of an ion implantation method.

35. The method of claim 26, wherein,

in the substrate, a doped well region is configured at least below the trench structure.

36. The method of claim 35, wherein,

the formation of the doped well region is carried out by means of an ion implantation method.

37. The method of claim 27, wherein,

the at least one electrically insulating partition is configured as an oxide layer.

38. The method of claim 27, wherein,

at least one electrically insulating section is formed by means of an isolation method and/or a growth method and/or an oxidation method.

39. The method of claim 26, wherein,

after the trenches are constructed and before the electrically insulating regions are constructed, a sacrificial oxide layer is constructed at least over the partitions of the sidewalls and/or bottom of the trenches.