DE102005002198B3 - Power semiconductor component, has surface electrodes connected to one semiconductor layer in such a manner that lateral running series circuit of MOS diodes is formed, where electrodes lie partially directly on layer - Google Patents

Abstract

The component has a semiconductor body, in which a peripheral area (4) exhibits semiconductor layers (5, 6). Trenches (7) pierce through the layer (6), where trench electrodes are electrically isolated against the body by insulation layers (9). Surface electrodes (10) are connected to the layer (6) in such a manner that a lateral running series circuit of MOS diodes is formed. The electrodes lie partially directly on the layer (6). An independent claim is also included for a method for manufacturing a semiconductor component.

Description

The The invention relates to a semiconductor device with edge region and its Adjustment process.

Semiconductor components (in particular power semiconductor components) should have the lowest possible specific forward resistance R _on A (R _on = _on- resistance, A = chip area of the active region of the semiconductor component). Furthermore, the semiconductor devices should have good breakdown properties ("avalanche resistance").

The Breakthrough properties of a semiconductor device are very strong the embodiment of the edge construction of the semiconductor device dependent. edge designs have therefore been the subject of intensive research in the past. The edge construction of a semiconductor device serves primarily in addition, electric field strengths in a zone of the semiconductor device that is between the active area (Cell field) and the saw edge of the semiconductor device is set to desired values. To a premature one To avoid breakthrough in the off-state of the semiconductor device allowed to the electric field strengths within the boundary structure those in the active area predominant Do not exceed field strength maximum values. To achieve this, it is attempted to make equipotential lines such as Inside of the semiconductor device or from the interior of the edge construction the surface lead the semiconductor device that excessively strong Potential gradients are avoided. The defined outward guidance of equipotential lines is referred to as "equipotential line management". The equipotential lines should be so led be that overly strong curvatures and high equipotential line densities be avoided.

Ideally a semiconductor device should be designed so that its edge construction (hereinafter also referred to as edge area) requires little chip area, the Semiconductor device at the same time, however, the best possible blocking capability having. In addition, the edge construction should be as insensitive as possible to surface charges be. Such a semiconductor device is for example in the document WO 2004/107448 A1.

The The object underlying the invention is another semiconductor device indicate that the above mentioned Requirements are sufficient.

To solve this problem, the invention provides a semiconductor device according to claim 1 ready. Furthermore, the invention provides methods for producing such a semiconductor device according to the patent claims 8th and 9 ready. Advantageous embodiments and developments of the inventive concept can be found in the subclaims.

• – eine erste Halbleiterschicht des einen Dotiertyps,
• – eine zweite Halbleiterschicht des anderen Dotiertyps, die auf der ersten Halbleiterschicht angeordnet ist,
• – Trenches, die die zweite Halbleiterschicht durchstoßen und in die erste Halbleiterschicht hineinragen, wobei in den Trenches Trench-Elektroden vorgesehen sind, die mittels entsprechender Isolationsschichten gegenüber dem Halbleiterkörper elektrisch isoliert sind, und
• – Oberflächen-Elektroden, die oberhalb der zweiten Halbleiterschicht vorgesehen sind und mit der zweiten Halbleiterschicht und jeweils einer Trench-Elektrode elektrisch verbunden sind, derart, dass eine lateral verlaufende Serienschaltung von MOS-Dioden des anderen Kanaltyps gebildet wird, wobei jede MOS-Diode aus einem Trench, der in dem Trench vorgesehenen Isolationsschicht und Trench-Elektrode, den an den Trench angrenzenden Bereichen der ersten und zweiten Halbleiterschicht sowie der mit der Trench-Elektrode elektrisch verbundenen Oberflächen-Elektrode besteht. Die Oberflächen-Elektroden liegen zumindest teilweise direkt auf der zweiten Halbleiterschicht auf, d.h. sind direkt auf der zweiten Halbleiterschicht angeordnet.

The semiconductor component according to the invention has a semiconductor body in which an active region and an edge region adjoining the active region are provided. The border area points to:

• A first semiconductor layer of the one doping type,
• A second semiconductor layer of the other doping type, which is arranged on the first semiconductor layer,
• Trenches that pierce the second semiconductor layer and protrude into the first semiconductor layer, wherein in the trenches trench electrodes are provided, which are electrically insulated by means of corresponding insulating layers with respect to the semiconductor body, and
• - Surface electrodes which are provided above the second semiconductor layer and are electrically connected to the second semiconductor layer and each of a trench electrode, such that a laterally extending series connection of MOS diodes of the other channel type is formed, each MOS diode of a trench comprising the insulating layer and trench electrode provided in the trench, the regions of the first and second semiconductor layers adjoining the trench, and the surface electrode electrically connected to the trench electrode. The surface electrodes are at least partially directly on the second semiconductor layer, ie are arranged directly on the second semiconductor layer.

In an embodiment is every surface electrode only connected to the region of the second semiconductor layer, the in terms of of the corresponding trench to which the surface electrode is "assigned" to the active region of the semiconductor device is facing.

In a preferred embodiment is every surface electrode with the corresponding "associated" trench electrode merged into a common electrode. This embodiment has the advantage that, as later explained in more detail will be, it is particularly easy to manufacture.

The surface electrodes and the trench electrodes are preferably made of doped polysilicon of one or the other doping type. For a good shielding of external electric fields or an effective suction of upper To allow surface charges, the surface electrodes should be designed annular and the active area (at least partially) enclose.

In a preferred embodiment For example, one doping type is n-type and the other doping type is p-type. Of course can in all embodiments the doping types are interchanged, that is, n-regions can through p-ranges be replaced and vice versa. The semiconductor device can both have a lateral as well as a vertical structure.

• – Ausbilden der zweiten Halbleiterschicht auf oder in der ersten Halbleiterschicht,
• – Ausbilden der Trenches,
• – Auskleiden der Innenwände der Trenches mit Isolationsschichten,
• – Abscheiden einer Schicht aus leitendem Material auf der Oberfläche der so entstandenen Struktur, derart, dass die Trenches wenigstens teilweise mit dem leitenden Material aufgefüllt werden,
• – Strukturieren der aus leitendem Material bestehenden Schicht.

The invention further provides a method for producing the semiconductor device according to the invention, comprising the following steps:

• Forming the second semiconductor layer on or in the first semiconductor layer,
• - forming the trenches,
• Lining the inner walls of the trenches with insulating layers,
• Depositing a layer of conductive material on the surface of the resulting structure such that the trenches are at least partially filled with the conductive material,
• - Structuring the existing layer of conductive material.

The Layer of conductive material is preferably made of (highly) doped Semiconductor material, but may also consist of a metal.

• – Ausbilden der Trenches in der ersten Halbleiterschicht,
• – Auskleiden der Innenwände der Trenches mit Isolationsschichten,
• – Abscheiden einer Schicht aus dotiertem halbleitenden Material auf der Oberfläche der so entstandenen Struktur, derart, dass die Trenches wenigstens teilweise mit dem halbleitenden Material aufgefüllt werden,
• – Ausbilden der zweiten Halbleiterschicht, indem Dotierstoffe mittels eines Temperprozesses in den oberen Teil der zwischen den Trenches befindlichen Bereiche der ersten Halbleiterschicht eingebracht werden (die Dotierstoffe treten aus der aus dotiertem halbleitenden Material bestehenden Schicht in den Halbleiterkörper ein), und
• – Strukturieren der aus dotiertem halbleitenden Material bestehenden Schicht.

Alternatively, the semiconductor device according to the invention can also be produced as follows:

• Forming the trenches in the first semiconductor layer,
• Lining the inner walls of the trenches with insulating layers,
• Depositing a layer of doped semiconductive material on the surface of the resulting structure such that the trenches are at least partially filled with the semiconducting material,
• Forming the second semiconductor layer by introducing dopants into the upper part of the regions between the trenches of the first semiconductor layer by means of an annealing process (the dopants enter the semiconductor body from the layer consisting of doped semiconducting material), and
• - Structuring of the layer consisting of doped semiconducting material.

Both Manufacturing processes have the advantage that the surface electrodes and the trench electrodes as common, fused together Electrodes can be produced in one process step.

The Invention leaves particularly beneficial in the field of power semiconductor devices deploy.

The Invention will be described below with reference to the figures exemplary embodiment explained in more detail. It demonstrate:

1 a cross-sectional view of a preferred embodiment of a semiconductor device according to the invention,

2 a schematic diagram to illustrate a preferred embodiment of the manufacturing method according to the invention.

In the figures are identical or corresponding areas, Components and component groups are marked with the same reference numbers.

A semiconductor device 1 has a semiconductor body 2 in which an active area 3 as well as to the active area 3 adjacent border area 4 are provided. The border area 4 includes: a first semiconductor layer 5 of the one (n-) doping type, a second semiconductor layer 6 of the other (p-) doping type deposited on the first semiconductor layer 5 is provided, as well as trenches 7 that the second semiconductor layer 6 pierced and in the first semiconductor layer 5 protrude, being in the trenches 7 Trench electrodes 8th are provided, which by means of appropriate insulation layers 9 opposite to the semiconductor body 2 are electrically isolated. The design of the insulation layers 9 is in principle arbitrary; For example, at the bottom of the trenches 7 the insulation layer 9 be thickened designed. The semiconductor device 1 also has surface electrodes 10 on, above the second semiconductor layer 6 are provided and with this and in each case a trench electrode 8th are electrically connected, so that a laterally extending series connection of MOS diodes 11 of the other channel type is formed. Each MOS diode 11 consists of a trench 7 , the insulation layer provided in the trench 9 and the trench electrode surrounded by this insulating layer 8th , the regions of the first and second semiconductor layers adjoining the corresponding trench 5 . 6 as well as with the trench electrode 8th electrically connected surface electrode 10 , Below the first semiconductor layer 5 is a third (heavily doped) semiconductor layer 12 of a doping type provided. In the area of the saw edge 15 is an electrical connection 16 provided, which is the first semiconductor layer 5 with the second semiconductor layer 6 connects electrically. A p ⁺ -doped region 17 to a (not to be seen) cell field in the active area 3 adjacent, is at ground potential.

The material of the trench electrodes 8th as well as the surface electrodes 10 is preferably made of doped polysilicon, since in this case the MOS diodes 11 can be made very easily.

In 1 is still the equivalent circuit of one of the MOS diodes 11 wherein "S" denotes source and "D" denotes drain.

In 1 a semiconductor device with a vertical structure is shown. However, the invention can be applied analogously to semiconductor devices with a lateral structure. The active area 3 may be, for example, a transistor cell array or a diode cell array. Advantageous to the in 1 shown semiconductor device is that no passivation of the semiconductor device is required. The surface electrodes 10 are preferably designed as rings, each ring the active area 3 at least partially (preferably completely) encloses. Through the surface electrodes 10 can be both a suction of surface charges that are on a surface 13 of the semiconductor device, as well as the shielding of electromagnetic fields from the outside, causing a distortion of the potential profile within the edge region 4 can be realized.

The production of in 1 The semiconductor device shown can be made as follows: first, the trenches 7 formed, the inner walls with the insulation layers 9 be lined. Then it is applied to the surface of the semiconductor device 1 deposited a layer of polysilicon, the remaining free spaces within the trenches 7 fills as well as the surface 13 of the semiconductor body 2 covered. Now a structuring process takes place in which the on the surface 13 arranged layer of polysilicon in the individual surface electrodes 10 "isolated" is.

The manufacturing process described above was prior to forming the trenches 7 the second semiconductor layer 6 be already trained. However, this is not necessarily the case, as in 2 indicated manufacturing process shows:
First, the second semiconductor layer 6 unavailable. In the first semiconductor layer 5 become the trenches 7 introduced, the inner walls with insulation layers 9 covered and then onto the surface 13 , that of the surface of the first semiconductor layer 5 corresponds, a layer of polysilicon of the other doping type (p-type doping) applied, the remaining free spaces within the trenches 7 fill up. This is followed by an annealing process, which causes dopants from the polysilicon layer 14 in the first semiconductor layer 5 enter and in this way the second semiconductor layer 6 form. Subsequently, the polysilicon layer 14 be structured, that is in the individual surface electrodes 10 to be isolated.

Accordingly, according to the invention a semiconductor device specified in the edge region Feldringstrukturen and / or field plates are used. In the edge area of the power semiconductor be through masked etching processes Trenches generated, which are the near-surface Pierce p-doped zone. Subsequently These trenches are provided with an insulator and finally with Filled in polysilicon, wherein the polysilicon contacts the p-doped region. The structure allows a high blocking capacity as well as a high insensitivity to surface charges.

The Invention leaves to apply to any semiconductor devices, for example on MOSFETs (MOS Field Effect Transistor), IGBTs (Insulated Gate Bipolar Transistor), Diodes, etc.

1

Semiconductor device

2

Semiconductor body

3

active Area

4

border area

5

first Semiconductor layer

6

second Semiconductor layer

7

trench

8th

Trench electrode

9

insulation layer

10

Surface electrode

11

MOS-electrode

12

third Semiconductor layer

13

surface

14

polysilicon layer

15

sawing edge

16

electrical connection

17

Semiconductor region

Claims (9)

Semiconductor device ( 1 ), with a semiconductor body ( 2 ), in which: - an active area ( 3 ), and - on to the active area ( 3 ) adjacent border area ( 4 ) are provided, wherein the edge region ( 4 ): - a first semiconductor layer ( 5 ) of a doping type (n), - a second semiconductor layer ( 6 ) of the other doping type (p), which on the first semiconductor layer ( 5 ), - Trenches ( 7 ), which the second semiconductor layer ( 6 ) and into the first semiconductor layer ( 5 protrude), where in the trenches ( 7 ) Trench electrodes ( 8th ) provided by means of corresponding insulation layers ( 9 ) with respect to the Halbleiterkör by ( 2 ) are electrically isolated, and - surface electrodes ( 10 ), which above the second semiconductor layer ( 6 ) are provided and with the second semiconductor layer ( 6 ) and one trench electrode each ( 8th ) are electrically connected, such that a laterally extending series connection of MOS diodes ( 11 ) of the other channel type (p) is formed, each MOS diode ( 11 ) from a trench ( 7 ), the insulation layer provided in the trench ( 9 ) and trench electrode ( 8th ), the regions of the first and second semiconductor layers adjoining the trench ( 5 . 6 ) as well as with the trench electrode ( 8th ) electrically connected surface electrode ( 10 ), characterized in that the surface electrodes ( 10 ) at least partially directly on the second semiconductor layer ( 6 ) rest. Semiconductor device ( 1 ) according to claim 1, characterized in that each surface electrode ( 10 ) only with the region of the second semiconductor layer ( 6 ) associated with the corresponding trench ( 7 ) the active area ( 3 ) of the semiconductor device ( 1 ) is facing. Semiconductor device ( 1 ) according to one of claims 1 to 2, characterized in that each surface electrode ( 10 ) with the appropriate trench electrode ( 8th ) are fused to a common electrode. Semiconductor device ( 1 ) according to one of claims 1 to 3, characterized in that the surface electrodes ( 10 ) and the trench electrodes ( 8th ) consist of doped polysilicon of the other doping type. Semiconductor device ( 1 ) according to one of claims 1 to 4, characterized in that the surface electrodes ( 10 ) are annular and the active area ( 3 ) enclose. Semiconductor device ( 1 ) according to any one of claims 1 to 5, characterized in that one doping type is n-type and the other doping type is p-type. Semiconductor device ( 1 ) according to one of claims 1 to 6, characterized by a vertical structure. Method for producing the semiconductor device ( 1 ) according to one of the preceding claims, comprising the following steps: - forming the second semiconductor layer ( 6 ) on or in the first semiconductor layer, - forming the trenches ( 7 ), - lining the inner walls of the trenches ( 7 ) with insulation layers ( 9 ), - depositing a layer ( 14 ) of conductive material on the surface ( 13 ) of the resulting structure, such that the trenches ( 7 ) are at least partially filled with the conductive material, - structuring the layer ( 14 ) of conductive material. Method for producing the semiconductor device ( 1 ) according to any one of claims 1 to 7, comprising the following steps: - forming the trenches ( 7 ) in the first semiconductor layer ( 5 ), - lining the inner walls of the trenches ( 7 ) with insulation layers ( 9 ), - depositing a layer ( 14 ) of doped semiconductive material on the surface ( 13 ) of the resulting structure, such that the trenches ( 7 ) are at least partially filled with the semiconducting material, - forming the second semiconductor layer ( 6 ) by dopants by means of an annealing process in the upper part of the inter-trench areas of the first semiconductor layer ( 5 ), - structuring of the layer ( 14 ) of doped semiconducting material.