DE102004053646A1 - Locally defined production of Si nanocrystals on an Si substrate with insulating layer useful in electronic switching technology with gas phase Ga deposition in holes in the insulated layer at which nanocrystals grow out from Ga-Si eutectic - Google Patents

Locally defined production of Si nanocrystals on an Si substrate with insulating layer useful in electronic switching technology with gas phase Ga deposition in holes in the insulated layer at which nanocrystals grow out from Ga-Si eutectic Download PDF

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DE102004053646A1
DE102004053646A1 DE200410053646 DE102004053646A DE102004053646A1 DE 102004053646 A1 DE102004053646 A1 DE 102004053646A1 DE 200410053646 DE200410053646 DE 200410053646 DE 102004053646 A DE102004053646 A DE 102004053646A DE 102004053646 A1 DE102004053646 A1 DE 102004053646A1
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silicon
insulating layer
nanocrystals
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gallium
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Edmund Prof. Dr.-Ing. Burte
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Otto Von Guericke Universitaet Magdeburg
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02601—Nanoparticles
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639—Preparation of substrate for selective deposition
    • H01L21/02645—Seed materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate

Abstract

Locally defined production of Si nanocrystals on an Si substrate (a) with insulating layer (b) where this layer is removed photolithographically and by etching at sites of lateral dimensions about 10 nm, where the crystals are required to grow. At holes produced in the insulated layer Ga (e) is deposited on the Si substrate from the gas phase and The Si nanocrystals grow out from the local Ga-Si eutectic at the holes on addition of the Si-containing gas.

Description

Die Erfindung betrifft ein Verfahren zur örtlich definierten Erzeugung von Silizium-Nanokristallen, insbesondere in Form von Silizium-Nadeln oder Silizium-Nanodrähten, auf einem z. B. scheibenförmigen Siliziumsubstrat. Unter "örtlich definierter Erzeugung" soll im Folgenden die Erzeugung von Silizium-Nanokristallen an vorgebbaren Orten der Substratoberfläche verstanden werden; insbesondere sollen die Silizium-Nanokristalle entsprechend eines vorgebbaren geometrischen Musters angeordnet sein.The The invention relates to a method for locally defined generation of silicon nanocrystals, in particular in the form of silicon needles or silicon nanowires, on a z. B. disc-shaped silicon substrate. Under "locally defined Generation "should in the following, the generation of silicon nanocrystals to predeterminable Locate the substrate surface be understood; in particular, the silicon nanocrystals should be arranged according to a predetermined geometric pattern.

Um unter Verwendung von Silizium-Nanokristallen elektronische Schaltungen herstellen zu können, wobei die Silizium-Nanokristalle das Volumen bzw. das Substrat der Transistorstrukturen bilden, müssen die Silizium-Nanokristalle örtlich wohl definiert erzeugt werden, um auch leitende Verbindungen zu den dem Siliziumsubstrat nahen Elektroden der Transistorstrukturen realisieren zu können. Für den genannten Zweck ist es auch bekannt, von einem Siliziumsubstrat auszugehen, das mit einer isolierenden Schicht aus Siliziumoxid und/oder Siliziumnitrid versehen ist.Around using silicon nanocrystals electronic circuits to be able to produce wherein the silicon nanocrystals the volume and the substrate of the Transistor structures form, must the silicon nanocrystals locally well defined to be able to also make conductive connections the electrodes of the transistor structures close to the silicon substrate to be able to realize. For the mentioned Purpose, it is also known to start from a silicon substrate, that with an insulating layer of silicon oxide and / or silicon nitride is provided.

Aus der Literatur/1, 2, 3/ ist bekannt, dass z. B. unter Verwendung von Gold- oder Gallium-Nano-templaten und bei Zuführung eines Silizium-haltigen Gases unter geeigneten experimentellen Randbedingungen auf der Oberfläche einer Siliziumscheibe einkristalline, aus Silizium bestehende Nadeln gezüchtet werden können, die genau an den Stellen wachsen, an denen die Template erzeugt wurden.Out the literature / 1, 2, 3 / is known that z. B. using of gold or gallium nanotemplates and at feeder a silicon-containing gas under suitable experimental conditions on the surface a silicon wafer monocrystalline, consisting of silicon needles cultured can be which grow exactly where the template creates were.

Aus dem in der DE 101 13 549 C2 genannten Stand der Technik ist es bekannt, ein katalytisch aktives Metall auf einem bereits mit Fotolack strukturiertem Substrat aufzubringen. Anschließend wird ein Liftoff-Verfahren verwendet, um den strukturierten Fotolack und das darauf befindliche Metall zu entfernen. Das zurückbleibende katalytisch aktive Metall wird sodann zum Aufwachsen von Nanoröhren verwendet, wobei der Ort des Aufwachsens sich nach dem Ort des aufgebrachten katalytisch aktiven Metalls bestimmt. Die Verwendung von Gallium als katalytisch aktives Metall würde bei diesem Verfahren bei der nachträglichen Entfernung des Fotolacks im Lift-Off-Verfahren zu einer sauerstoffbedingten Verunreinigung der Galliumoberfläche führen.From the in the DE 101 13 549 C2 It is known in the cited prior art to apply a catalytically active metal to a substrate already structured with photoresist. Subsequently, a liftoff process is used to remove the patterned photoresist and the metal thereon. The remaining catalytically active metal is then used to grow nanotubes, with the location of growth determined by the location of the deposited catalytically active metal. The use of gallium as a catalytically active metal would result in this process in the subsequent removal of the resist in the lift-off process to an oxygen-related contamination of the gallium surface.

Aus der DE 101 13 549 C2 ist ein Verfahren zum Wachsen einer Nanoröhre bekannt, bei dem ein Substrat, welches einen mit Fotolack bedeckten Bereich und einen freien Bereich aufweist, mit einer Verbindung eines katalytisch aktiven Metalls in Kontakt gebracht wird. Hierdurch wird eine Schicht, die die Verbindung des katalytisch aktiven Metalls aufweist, auf dem Substrat gebildet. Das so behandelte Substrat wird sodann mit einer basischen Lösung in Kontakt gebracht, wodurch die Verbindung des katalytisch wirksamen Metalls in das entsprechende Hydroxid überführt wird. Der Fotolack wird dann mittels eines Liftoff-Verfahrens entfernt, sodass das Hydroxid des katalytisch aktiven Metalls auf dem freien Bereich des Substrats verbleibt. Das Hydroxid wird anschließend zum entsprechenden katalytisch aktiven Metall reduziert und im Anschluss daran wird auf dem katalytisch aktiven Metall die Nanoröhre aufgewachsen. Dieses Verfahren ist durch den Einschluss nasschemischer Verfahrensschritte relativ aufwendig.From the DE 101 13 549 C2 For example, a method for growing a nanotube is known in which a substrate having a photoresist-covered region and a free region is brought into contact with a compound of a catalytically active metal. As a result, a layer comprising the compound of the catalytically active metal is formed on the substrate. The thus-treated substrate is then contacted with a basic solution, whereby the compound of the catalytically active metal is converted into the corresponding hydroxide. The photoresist is then removed by a liftoff process so that the hydroxide of the catalytically active metal remains on the free area of the substrate. The hydroxide is subsequently reduced to the corresponding catalytically active metal and, subsequently, the nanotube is grown on the catalytically active metal. This process is relatively complicated by the inclusion of wet-chemical process steps.

Der Erfindung liegt die Aufgabe zugrunde, ausgehend von einer mit einer isolierenden Schicht versehenen Siliziumsubstratscheibe örtlich definiert Silizium-Nanokristalle zu erzeugen.Of the Invention is based on the object, starting from one with a Insulating layer provided silicon substrate disk locally defines silicon nanocrystals to create.

Erfindungsgemäß wird diese Aufgabe durch die Merkmale des Anspruchs 1 gelöst. Vorteilhafte Ausgestaltungen und Weiterbildungen des erfindungsgemäßen Verfahrens ergeben sich aus den Ansprüchen.According to the invention this Problem solved by the features of claim 1. Advantageous embodiments and further developments of the method according to the invention arise from the claims.

So ist es für die Abscheidung des Galliums an den in der isolierenden Schicht erzeugten Lochstellen besonders vorteilhaft, eine in der Gasphase vorliegende metallorganische Galliumverbindung, z. B. Trimethylgallium, bei einem Druck im Bereich von ca. 50 mTorr bis 10 Torr und einer Temperatur im Bereich von ca. 250 bis 750 °C einzusetzen.So is it for the deposition of gallium at the in the insulating layer holes produced particularly advantageous, one present in the gas phase organometallic gallium compound, e.g. B. trimethylgallium, at a pressure in the range of about 50 mTorr to 10 Torr and a temperature in the range of approx. 250 to 750 ° C use.

Eine andere besonders vorteilhafte Ausgestaltung des erfindungsgemäßen Verfahrens ermöglicht es, die laterale Abmessung der in der isolierenden Schicht erzeugten Lochstellen vor der Galliumabscheidung zu reduzieren. Erreicht wird dies durch ein- oder mehrfache Anwendung folgender Prozessschritte:

  • • Abscheiden einer CVD-Schicht aus Polysilizium oder Siliziumoxid mindestens im Bereich der Lochstellen der isolierenden Schicht mit konformer Kantenbedeckung und – bei Abscheidung einer Polysiliziumschicht – thermische Oxidierung der Polysiliziumschicht,
  • • Ausführen eines Trockenätzschrittes mindestens im Bereich der Lochstellen, bei dem das Siliziumoxid um die Schichtdicke des Oxides am Boden der Lochstelle ganzflächig zurückgeätzt wird, bis am Boden der Lochstelle wieder Silizium frei gelegt wird.
Another particularly advantageous embodiment of the method according to the invention makes it possible to reduce the lateral dimension of the holes produced in the insulating layer before the gallium deposition. This is achieved by single or multiple application of the following process steps:
  • Deposition of a CVD layer of polysilicon or silicon oxide at least in the region of the perforations of the insulating layer with conformal edge coverage and, in the case of deposition of a polysilicon layer, thermal oxidation of the polysilicon layer,
  • • Carrying out a dry etching step at least in the region of the hole locations, in which the silicon oxide is etched back over the entire surface area by the layer thickness of the oxide at the bottom of the hole location, until silicon is exposed again at the bottom of the hole location.

Auf diese Weise lassen sich die Anforderungen an den photolithographischen und den Ätzprozess zur Herstellung der Lochstellen wesentlich reduzieren.On this way, the requirements for the photolithographic and the etching process significantly reduce for the production of the holes.

Im Folgenden ist die Erfindung anhand eines Ausführungsbeispiels näher erläutert, wobei jedoch auf die explizite Nennung an sich bekannter und üblicherweise verwendeter Prozessschritte einer Halbleiterbauelementprozessierung, wie Reinigung der Silizium-Oberflächen von organischen und anorganischen Spuren, Schritte zum Entlacken, u.s.w., verzichtet wird. In dem Ausführungsbeispiel wird Bezug genommen auf die beigefügte Zeichnung, die in schematischer Darstellung das Ergebnis der im erfindungsgemäßen Verfahren durchzuführenden Prozessschritte veranschaulicht.in the Below, the invention is explained in more detail with reference to an embodiment, wherein however, to the explicit mention of known per se and usually used process steps of semiconductor device processing, like cleaning the silicon surfaces of organic and inorganic traces, stripping, etc. is waived. In the embodiment Reference is made to the accompanying drawings, which in schematic Representation of the result to be carried out in the process according to the invention Process steps illustrated.

1a: Nach Belichtung und Entwicklung des Photolacks einer mit Siliziumoxid versehenen Substratscheibe 1a After exposure and development of the photoresist of a substrate plate provided with silicon oxide

1b: Nach Trockenätzen des Siliziumoxids und Entfernen des Photolacks 1b After dry etching the silica and removing the photoresist

1c: Nach konformer Abscheidung einer Schicht mittels CVD, z.B. Siliziumoxid 1c : After conformal deposition of a layer by means of CVD, eg silicon oxide

1d: Nach ganzflächigem Rückätzen der Oberfläche 1d After full-surface re-etching of the surface

1e: Nach selektivem Abscheiden von Gallium an den Lochstellen 1e : After selective deposition of gallium at the holes

1a zeigt in einer Schnittdarstellung ein Siliziumsubstrat a, auf das eine isolierende Schicht b aus Siliziumoxid aufgebracht ist sowie eine Schicht Photolack c. Der Photolack c ist bereits mittels photolithographischer Methoden unter Verwendung eines Elektronenstrahldirektschreibers oder eines im extremen UV-Bereich arbeitenden Steppers nanoskalig strukturiert, d.h. der Photolack ist an den Stellen, an denen Silizium-Nanokristalle auf dem Siliziumsubstrat wachsen sollen, in Bereichen mit einer Abmessung von einigen 10 nm entfernt. Diese Stellen ohne Photolack bilden ein geometrisches Muster, das zugleich der örtlichen Verteilung der zu erzeugenden Silizium-Nanokristalle entspricht. 1a shows a sectional view of a silicon substrate a, on which an insulating layer b of silicon oxide is applied and a layer of photoresist c. The photoresist c is already nanoscale structured by means of photolithographic methods using an electron beam writer or a stepper working in the extreme UV range, ie the photoresist is in areas with a dimension of a few at the locations where silicon nanocrystals are to grow on the silicon substrate 10 nm away. These areas without photoresist form a geometric pattern, which also corresponds to the local distribution of the silicon nanocrystals to be produced.

Die isolierende Schicht b wird schließlich in einem üblichen Trockenätzschritt entsprechend dem im Photolack c erzeugten geometrischen Muster strukturiert (1b), sodass in der isolierenden Schicht b Lochstellen in einer örtlich definierten Verteilung erzeugt werden. Anschließend wird auch der verbliebene Photolack entfernt.The insulating layer b is finally patterned in a conventional dry etching step according to the geometric pattern generated in the photoresist c ( 1b ), so that in the insulating layer b holes are generated in a locally defined distribution. Subsequently, the remaining photoresist is removed.

In den folgenden Schritten wird die laterale Abmessung der Lochstellen verringert durch ein- oder mehrfache Anwendung folgender Prozessschritte:

  • • Abscheiden von Polysilizium oder Siliziumoxid als CVD-Schicht d (1c) mit konformer Kantenbedeckung mindestens im Bereich der Lochstellen und – bei Abscheidung einer Polysiliziumschicht – thermische Oxidierung der Polysiliziumschicht,
  • • Ausführen eines Trockenätzschrittes mindestens im Bereich der Lochstelle, bei dem das Siliziumoxid um die Schichtdicke des Oxides am Boden der Lochstelle ganzflächig zurückgeätzt wird, bis am Boden der Lochstelle wieder Silizium frei gelegt wird (1d).
In the following steps, the lateral dimension of the holes is reduced by using one or more of the following process steps:
  • Deposition of polysilicon or silicon oxide as CVD layer d ( 1c ) with conformal edge coverage at least in the region of the perforations and - in the case of deposition of a polysilicon layer - thermal oxidation of the polysilicon layer,
  • Executing a dry etching step at least in the region of the hole, in which the silicon oxide is etched back over the entire surface by the layer thickness of the oxide at the bottom of the hole until silicon is released again at the bottom of the hole 1d ).

Anschließend wird aus der Gasphase z.B. unter Verwendung von Trimethylgallium unter geeigneten Prozessbedingungen, z.B. bei einem Druck von ca. 50 mTorr bis 10 Torr und Temperaturen im Bereich von 250 bis 750 °C Gallium e an den freien, d.h. nicht mit der isolierenden Schicht versehenen Stellen des Siliziumsubstrats a niedergeschlagen. Die Adsorbtion und Reaktion z.B. des Trimethylgalliums auf Silizium läuft örtlich selektiv ab.Subsequently, will from the gas phase, e.g. using trimethylgallium below suitable process conditions, e.g. at a pressure of about 50 mTorr to 10 Torr and temperatures in the range of 250 to 750 ° C gallium e to the free, i. not provided with the insulating layer sites of the silicon substrate a. The adsorption and reaction e.g. of the trimethylgallium on silicon is locally selective.

Die auf diese Weise mit einem definierten geometrischen Muster erzeugten metallischen Template werden für das Wachsen der Silizium-Nanodrähte an genau diesen Stellen herangezogen, indem unter Zuführung Silizium-haltiger Gase, wie aus der Literatur bekannt, aus dem lokal vorliegenden Gallium-Silizium Eutektikum die Nanokristalle herausgewachsen werden.The created in this way with a defined geometric pattern metallic template will be for the growth of silicon nanowires used in exactly these places, by feeding silicon-containing Gases, as known from the literature, from the locally available Gallium-silicon eutectic the nanocrystals are outgrown.

Referenzen:References:

  • /1/ L. J. Lauhon, M. S. Gudiksen, D. Wamg, C. M. Lieber, Nature 420 (2002) 57, Y. Cui, C. M. Lieber, Science 291 (2001) 851/ 1 / L.J. Lauhon, M.S. Gudiksen, D. Wamg, C.M. Lieber, Nature 420 (2002) 57, Y. Cui, C.M. Lieber, Science 291 (2001) 851
  • /2/ Z. L. Wang, Z. R. Dai, R. P. Gao, Z. J. Bai, J. L. Gole, Appl. Phys. Lett. 77 (2000) 3349/ 2 / Z.L. Wang, Z.R. Dai, R.P. Gao, Z.J. Bai, J.L. Gole, Appl. Phys. Lett. 77 (2000) 3349
  • /3/ A. M. Morales, C. M. Lieber, Science 279 (1998) 208/ 3 / A.M. Morales, C.M. Lieber, Science 279 (1998) 208

Claims (5)

Verfahren zur örtlich definierten Erzeugung von Silizium-Nanokristallen auf einem Siliziumsubstrat (a), das mindestens abschnittsweise eine isolierende Schicht (b) aufweist, wobei • die isolierende Schicht (b) an den Stellen, an denen die Silizium-Nanokristalle auf dem Siliziumsubstrat (a) wachsen sollen, mittels eines photolithographischen und eines Ätzprozesses entfernt wird, indem an diesen Stellen, deren laterale Abmessung jeweils einige 10 nm beträgt, zuerst der Photolack (c) und nachfolgend in einem üblichen Trockenätzschritt auch die isolierende Schicht (b) entfernt wird, • an den in der isolierenden Schicht (b) erzeugten Lochstellen Gallium (e) aus der Gasphase auf dem Siliziumsubstrat (a) niedergeschlagen wird und • aus dem an den Lochstellen lokal vorliegenden Gallium-Silizium Eutektikum unter Zuführung Silizium-haltiger Gase die Silizium-Nanokristalle herausgewachsen werden.Method for the locally defined production of silicon nanocrystals on a silicon substrate (a), which has at least sections an insulating layer (b), wherein • the insulating layer (b) at the locations where the silicon nanocrystals on the silicon substrate (a ) is removed by means of a photolithographic and an etching process by first removing the photoresist (c) at these points whose lateral dimension is in each case a few 10 nm, and subsequently also the insulating layer (b) in a conventional dry etching step, gallium (e) is precipitated from the gas phase on the silicon substrate (a) at the perforation points generated in the insulating layer (b), and the silicon nanocrystals are ejected from the gallium-silicon eutectic present locally at the hole locations while supplying silicon-containing gases to be grown. Verfahren nach Anspruch 1, dadurch gekennzeichnet, dass als isolierende Schicht (b) Siliziumoxid und/oder Siliziumnitrid verwendet wird.Method according to claim 1, characterized in that in that as insulating layer (b) silicon oxide and / or silicon nitride is used. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass für die photolithographische Strukturierung der isolierenden Schicht (b) ein Elektronenstrahldirektschreiber oder ein im extremen UV-Bereich arbeitender Stepper verwendet wird.Method according to claim 1 or 2, characterized that for the photolithographic structuring of the insulating layer (b) an electron beam direct or extreme UV working stepper is used. Verfahren nach Anspruch 1 oder 3, dadurch gekennzeichnet, dass das Gallium aus einer in der Gasphase vorliegenden metallorganischen Galliumverbindung, z. B. Trimethylgallium, bei einem Druck im Bereich von ca. 50 mTorr bis 10 Torr und einer Temperatur im Bereich von ca. 250 bis 750 °C abgeschieden wird.Method according to claim 1 or 3, characterized that the gallium consists of a organometallic gas phase Gallium compound, e.g. B. trimethylgallium, at a pressure in the range from about 50 mTorr to 10 Torr and a temperature in the range of about 250 to 750 ° C is deposited. Verfahren nach einem der vorhergehenden Ansprüche, dadurch gekennzeichnet, dass vor der Galliumabscheidung die laterale Abmessung der Lochstellen in der isolierenden Schicht (b) verringert wird durch ein- oder mehrfache Anwendung folgender Prozessschritte: • Abscheiden einer CVD-Schicht (d) aus Polysilizium oder Siliziumoxid mindestens im Bereich der Lochstellen der isolierenden Schicht (b) mit konformer Kantenbedeckung und – bei Abscheidung einer Polysiliziumschicht – thermische Oxidierung der Polysiliziumschicht, • Ausführen eines Trockenätzschrittes mindestens im Bereich der Lochstellen, bei dem das Siliziumoxid (d) um die Schichtdicke des Oxides am Boden der Lochstelle ganzflächig zurückgeätzt wird, bis am Boden der Lochstelle wieder Silizium frei gelegt wird.Method according to one of the preceding claims, characterized characterized in that before the gallium deposition the lateral dimension the holes in the insulating layer (b) is reduced by single or multiple application of the following process steps: • Separate a CVD layer (d) of polysilicon or silicon oxide at least in the area of the perforations of the insulating layer (b) with conformal edge coverage and - at Deposition of a polysilicon layer - thermal oxidation of the Polysilicon layer, • Execute a dry etching at least in the area of the holes, where the silicon oxide (d) is etched back over the entire surface of the layer thickness of the oxide at the bottom of the hole, until silicon is released again at the bottom of the hole.
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EP2036117A1 (en) * 2006-06-15 2009-03-18 Electronics and Telecommunications Research Institute Method of manufacturing silicon nanowires using silicon nanodot thin film
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