DE102004053646A1 - Locally defined production of Si nanocrystals on an Si substrate with insulating layer useful in electronic switching technology with gas phase Ga deposition in holes in the insulated layer at which nanocrystals grow out from Ga-Si eutectic - Google Patents

Locally defined production of Si nanocrystals on an Si substrate with insulating layer useful in electronic switching technology with gas phase Ga deposition in holes in the insulated layer at which nanocrystals grow out from Ga-Si eutectic

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Publication number
DE102004053646A1
DE102004053646A1 DE200410053646 DE102004053646A DE102004053646A1 DE 102004053646 A1 DE102004053646 A1 DE 102004053646A1 DE 200410053646 DE200410053646 DE 200410053646 DE 102004053646 A DE102004053646 A DE 102004053646A DE 102004053646 A1 DE102004053646 A1 DE 102004053646A1
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Germany
Prior art keywords
silicon
insulating layer
si
nanocrystals
layer
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Ceased
Application number
DE200410053646
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German (de)
Inventor
Edmund Prof. Dr.-Ing. Burte
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Otto Von Guericke Universitaet Magdeburg
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Otto Von Guericke Universitaet Magdeburg
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Priority to DE200410053646 priority Critical patent/DE102004053646A1/en
Publication of DE102004053646A1 publication Critical patent/DE102004053646A1/en
Application status is Ceased legal-status Critical

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02491Conductive materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • H01L21/02601Nanoparticles
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02636Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02639Preparation of substrate for selective deposition
    • H01L21/02645Seed materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669Nanowires or nanotubes
    • H01L29/0673Nanowires or nanotubes oriented parallel to a substrate

Abstract

Locally defined production of Si nanocrystals on an Si substrate (a) with insulating layer (b) where this layer is removed photolithographically and by etching at sites of lateral dimensions about 10 nm, where the crystals are required to grow. At holes produced in the insulated layer Ga (e) is deposited on the Si substrate from the gas phase and The Si nanocrystals grow out from the local Ga-Si eutectic at the holes on addition of the Si-containing gas.

Description

  • The The invention relates to a method for locally defined generation of silicon nanocrystals, in particular in the form of silicon needles or silicon nanowires, on a z. B. disc-shaped silicon substrate. Under "locally defined Generation "should in the following, the generation of silicon nanocrystals to predeterminable Locate the substrate surface be understood; in particular, the silicon nanocrystals should be arranged according to a predetermined geometric pattern.
  • Around using silicon nanocrystals electronic circuits to be able to produce wherein the silicon nanocrystals the volume and the substrate of the Transistor structures form, must the silicon nanocrystals locally well defined to be able to also make conductive connections the electrodes of the transistor structures close to the silicon substrate to be able to realize. For the mentioned Purpose, it is also known to start from a silicon substrate, that with an insulating layer of silicon oxide and / or silicon nitride is provided.
  • Out the literature / 1, 2, 3 / is known that z. B. using of gold or gallium nanotemplates and at feeder a silicon-containing gas under suitable experimental conditions on the surface a silicon wafer monocrystalline, consisting of silicon needles cultured can be which grow exactly where the template creates were.
  • From the in the DE 101 13 549 C2 It is known in the cited prior art to apply a catalytically active metal to a substrate already structured with photoresist. Subsequently, a liftoff process is used to remove the patterned photoresist and the metal thereon. The remaining catalytically active metal is then used to grow nanotubes, with the location of growth determined by the location of the deposited catalytically active metal. The use of gallium as a catalytically active metal would result in this process in the subsequent removal of the resist in the lift-off process to an oxygen-related contamination of the gallium surface.
  • From the DE 101 13 549 C2 For example, a method for growing a nanotube is known in which a substrate having a photoresist-covered region and a free region is brought into contact with a compound of a catalytically active metal. As a result, a layer comprising the compound of the catalytically active metal is formed on the substrate. The thus-treated substrate is then contacted with a basic solution, whereby the compound of the catalytically active metal is converted into the corresponding hydroxide. The photoresist is then removed by a liftoff process so that the hydroxide of the catalytically active metal remains on the free area of the substrate. The hydroxide is subsequently reduced to the corresponding catalytically active metal and, subsequently, the nanotube is grown on the catalytically active metal. This process is relatively complicated by the inclusion of wet-chemical process steps.
  • Of the Invention is based on the object, starting from one with a Insulating layer provided silicon substrate disk locally defines silicon nanocrystals to create.
  • According to the invention this Problem solved by the features of claim 1. Advantageous embodiments and further developments of the method according to the invention arise from the claims.
  • So is it for the deposition of gallium at the in the insulating layer holes produced particularly advantageous, one present in the gas phase organometallic gallium compound, e.g. B. trimethylgallium, at a pressure in the range of about 50 mTorr to 10 Torr and a temperature in the range of approx. 250 to 750 ° C use.
  • Another particularly advantageous embodiment of the method according to the invention makes it possible to reduce the lateral dimension of the holes produced in the insulating layer before the gallium deposition. This is achieved by single or multiple application of the following process steps:
    • Deposition of a CVD layer of polysilicon or silicon oxide at least in the region of the perforations of the insulating layer with conformal edge coverage and, in the case of deposition of a polysilicon layer, thermal oxidation of the polysilicon layer,
    • • Carrying out a dry etching step at least in the region of the hole locations, in which the silicon oxide is etched back over the entire surface area by the layer thickness of the oxide at the bottom of the hole location, until silicon is exposed again at the bottom of the hole location.
  • On this way, the requirements for the photolithographic and the etching process significantly reduce for the production of the holes.
  • in the Below, the invention is explained in more detail with reference to an embodiment, wherein however, to the explicit mention of known per se and usually used process steps of semiconductor device processing, like cleaning the silicon surfaces of organic and inorganic traces, stripping, etc. is waived. In the embodiment Reference is made to the accompanying drawings, which in schematic Representation of the result to be carried out in the process according to the invention Process steps illustrated.
  • 1a After exposure and development of the photoresist of a substrate plate provided with silicon oxide
  • 1b After dry etching the silica and removing the photoresist
  • 1c : After conformal deposition of a layer by means of CVD, eg silicon oxide
  • 1d After full-surface re-etching of the surface
  • 1e : After selective deposition of gallium at the holes
  • 1a shows a sectional view of a silicon substrate a, on which an insulating layer b of silicon oxide is applied and a layer of photoresist c. The photoresist c is already nanoscale structured by means of photolithographic methods using an electron beam writer or a stepper working in the extreme UV range, ie the photoresist is in areas with a dimension of a few at the locations where silicon nanocrystals are to grow on the silicon substrate 10 nm away. These areas without photoresist form a geometric pattern, which also corresponds to the local distribution of the silicon nanocrystals to be produced.
  • The insulating layer b is finally patterned in a conventional dry etching step according to the geometric pattern generated in the photoresist c ( 1b ), so that in the insulating layer b holes are generated in a locally defined distribution. Subsequently, the remaining photoresist is removed.
  • In the following steps, the lateral dimension of the holes is reduced by using one or more of the following process steps:
    • Deposition of polysilicon or silicon oxide as CVD layer d ( 1c ) with conformal edge coverage at least in the region of the perforations and - in the case of deposition of a polysilicon layer - thermal oxidation of the polysilicon layer,
    • Executing a dry etching step at least in the region of the hole, in which the silicon oxide is etched back over the entire surface by the layer thickness of the oxide at the bottom of the hole until silicon is released again at the bottom of the hole 1d ).
  • Subsequently, will from the gas phase, e.g. using trimethylgallium below suitable process conditions, e.g. at a pressure of about 50 mTorr to 10 Torr and temperatures in the range of 250 to 750 ° C gallium e to the free, i. not provided with the insulating layer sites of the silicon substrate a. The adsorption and reaction e.g. of the trimethylgallium on silicon is locally selective.
  • The created in this way with a defined geometric pattern metallic template will be for the growth of silicon nanowires used in exactly these places, by feeding silicon-containing Gases, as known from the literature, from the locally available Gallium-silicon eutectic the nanocrystals are outgrown.
  • References:
    • / 1 / L.J. Lauhon, M.S. Gudiksen, D. Wamg, C.M. Lieber, Nature 420 (2002) 57, Y. Cui, C.M. Lieber, Science 291 (2001) 851
    • / 2 / Z.L. Wang, Z.R. Dai, R.P. Gao, Z.J. Bai, J.L. Gole, Appl. Phys. Lett. 77 (2000) 3349
    • / 3 / A.M. Morales, C.M. Lieber, Science 279 (1998) 208

Claims (5)

  1. Method for the locally defined production of silicon nanocrystals on a silicon substrate (a), which has at least sections an insulating layer (b), wherein • the insulating layer (b) at the locations where the silicon nanocrystals on the silicon substrate (a ) is removed by means of a photolithographic and an etching process by first removing the photoresist (c) at these points whose lateral dimension is in each case a few 10 nm, and subsequently also the insulating layer (b) in a conventional dry etching step, gallium (e) is precipitated from the gas phase on the silicon substrate (a) at the perforation points generated in the insulating layer (b), and the silicon nanocrystals are ejected from the gallium-silicon eutectic present locally at the hole locations while supplying silicon-containing gases to be grown.
  2. Method according to claim 1, characterized in that in that as insulating layer (b) silicon oxide and / or silicon nitride is used.
  3. Method according to claim 1 or 2, characterized that for the photolithographic structuring of the insulating layer (b) an electron beam direct or extreme UV working stepper is used.
  4. Method according to claim 1 or 3, characterized that the gallium consists of a organometallic gas phase Gallium compound, e.g. B. trimethylgallium, at a pressure in the range from about 50 mTorr to 10 Torr and a temperature in the range of about 250 to 750 ° C is deposited.
  5. Method according to one of the preceding claims, characterized characterized in that before the gallium deposition the lateral dimension the holes in the insulating layer (b) is reduced by single or multiple application of the following process steps: • Separate a CVD layer (d) of polysilicon or silicon oxide at least in the area of the perforations of the insulating layer (b) with conformal edge coverage and - at Deposition of a polysilicon layer - thermal oxidation of the Polysilicon layer, • Execute a dry etching at least in the area of the holes, where the silicon oxide (d) is etched back over the entire surface of the layer thickness of the oxide at the bottom of the hole, until silicon is released again at the bottom of the hole.
DE200410053646 2004-11-03 2004-11-03 Locally defined production of Si nanocrystals on an Si substrate with insulating layer useful in electronic switching technology with gas phase Ga deposition in holes in the insulated layer at which nanocrystals grow out from Ga-Si eutectic Ceased DE102004053646A1 (en)

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DE200410053646 DE102004053646A1 (en) 2004-11-03 2004-11-03 Locally defined production of Si nanocrystals on an Si substrate with insulating layer useful in electronic switching technology with gas phase Ga deposition in holes in the insulated layer at which nanocrystals grow out from Ga-Si eutectic

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2036117A1 (en) * 2006-06-15 2009-03-18 Electronics and Telecommunications Research Institute Method of manufacturing silicon nanowires using silicon nanodot thin film
WO2017177554A1 (en) * 2016-04-11 2017-10-19 西安隆基硅材料股份有限公司 Crystalline silicon and preparation method therefor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0010596A1 (en) * 1978-11-03 1980-05-14 International Business Machines Corporation Method of forming openings in masks for the production of semiconductor devices
EP1369506A1 (en) * 2002-05-28 2003-12-10 Japan Aviation Electronics Industry, Limited Method of making photonic crystal
US20040075464A1 (en) * 2002-07-08 2004-04-22 Btg International Limited Nanostructures and methods for manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0010596A1 (en) * 1978-11-03 1980-05-14 International Business Machines Corporation Method of forming openings in masks for the production of semiconductor devices
EP1369506A1 (en) * 2002-05-28 2003-12-10 Japan Aviation Electronics Industry, Limited Method of making photonic crystal
US20040075464A1 (en) * 2002-07-08 2004-04-22 Btg International Limited Nanostructures and methods for manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Bronikowski et al.:"The chemistry of qallium de- position Si(001) from thrimethylgallium: an atom- ically resolved STM study" in Surface Science, 1996, Nr. 3, S. 311-324 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2036117A1 (en) * 2006-06-15 2009-03-18 Electronics and Telecommunications Research Institute Method of manufacturing silicon nanowires using silicon nanodot thin film
EP2036117A4 (en) * 2006-06-15 2012-09-19 Korea Electronics Telecomm Method of manufacturing silicon nanowires using silicon nanodot thin film
WO2017177554A1 (en) * 2016-04-11 2017-10-19 西安隆基硅材料股份有限公司 Crystalline silicon and preparation method therefor

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