DE102004021054A1 - Semiconductor component for a flip-chip structure has contact layers between a semiconductor chip and a chip carrier - Google Patents

Semiconductor component for a flip-chip structure has contact layers between a semiconductor chip and a chip carrier Download PDF

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Publication number
DE102004021054A1
DE102004021054A1 DE102004021054A DE102004021054A DE102004021054A1 DE 102004021054 A1 DE102004021054 A1 DE 102004021054A1 DE 102004021054 A DE102004021054 A DE 102004021054A DE 102004021054 A DE102004021054 A DE 102004021054A DE 102004021054 A1 DE102004021054 A1 DE 102004021054A1
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chip
chip carrier
semiconductor
carrier part
component according
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DE102004021054A
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DE102004021054B4 (en
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Ralf Otremba
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

Between a semiconductor chip (1) and a chip carrier (2) there are first (6a) and second (6b) contact layers with their thicknesses (d1,d2) selected in a vertical direction so that there is no short-fall in a minimum required clearance for insulation stability between the semiconductor chip and the chip carrier.

Description

Die Erfindung betrifft ein Halbleiterbauelement mit einem Halbleiterchip und einem Chipträger, wobei der Halbleiterchip auf seiner dem Chipträger zugewandten Vorderseite einen ersten und einen zweiten Anschlusskontakt aufweist und mit dem Chipträger verbunden ist. Diese Art der Anordnung wird auch als "Flipchip-Anordnung" bezeichnet. Auf seiner der Vorderseite gegenüber liegenden Rückseite weist ein derartiger Halbleiterchip, der bevorzugt als Leistungshalbleiterchip ausgebildet ist, üblicherweise eine dritten Anschlusskontakt auf.The The invention relates to a semiconductor device with a semiconductor chip and a chip carrier, wherein the semiconductor chip on its front side facing the chip carrier having a first and a second terminal contact and with the chip carrier connected is. This type of arrangement is also referred to as a "flip-chip arrangement". On his opposite the front lying back has such a semiconductor chip, preferably as a power semiconductor chip is formed, usually a third connection contact on.

Bei dem ersten bzw. dritten Anschlusskontakt handelt es sich beispielsweise um einen ersten und einen zweiten Lastanschluss eines in den Halbleiterchip integrierten Bauelements, beispielsweise um den Source-Anschluss bzw. den Drain-Anschluss eines n-Kanal MOSFETs oder IGBTs. Der zweite Anschlusskontakt bildet einen Steueranschluss des Bauelements, d. h. den Gate-Anschlussbein einem in den Chip integrierten MOSFET.at the first or third terminal contact is for example around a first and a second load terminal of a in the semiconductor chip integrated device, for example, to the source terminal or the drain terminal of an n-channel MOSFET or IGBT. The second Terminal contact forms a control terminal of the device, d. H. the gate terminal leg of a chip-integrated MOSFET.

Die Flipchip-Anordnung wird beispielsweise gewählt, um anstelle des an der Rückseite angeordneten, bei vielen Anwendungen auf hohem elektrischen Potential liegenden dritten Anschlusskontaktes den an der Vorderseite angeordneten ersten Anschlusskontakt, der üblicherweise auf einem niedrigeren elektrischen Potential liegt, mit dem Chipträger elektrisch und mechanisch zu verbinden. Durch diese Maßnahme werden Schaltungsverluste sowie elektromagnetische Störstrahlungen reduziert, die anderenfalls, nämlich beim Anschließen des Chipträgers an das hohe Potential des dritten Anschlusskontaktes, aus der verhältnismäßig hohen Kapazität sowie den großen Abmessungen des Chipträgers resultieren.The Flip-chip arrangement is chosen, for example, instead of at the back arranged, in many applications at high electrical potential lying third terminal contact arranged at the front first connection contact, usually is at a lower electrical potential with the chip carrier electrically and mechanically connect. By this measure, circuit losses as well as electromagnetic interference radiation reduced, the other way, namely when connecting of the chip carrier to the high potential of the third terminal contact, from the relatively high capacity as well as the big one Dimensions of the chip carrier result.

Bei derartigen Anordnungen liegt der auf der Rückseite des Halbleiterchips angeordnete dritte Anschlusskontakt auf einem hohen elektrischen Potential gegenüber dem Chipträger. Dieses hohe elektrische Potential erstreckt sich infolge einer beim Sägen des Halbleiterchips auftretenden Oberflächenveränderung an dessen in vertikaler Richtung verlaufenden Seiten bis an die dem Chipträger zugewandten Kanten des Halbleiterchips.at Such arrangements is on the back of the semiconductor chip arranged third terminal contact on a high electrical Potential opposite the chip carrier. This high electrical potential extends as a result of a Sawing the Semiconductor chips occurring surface change at the in vertical Direction extending sides to the chip carrier facing Edges of the semiconductor chip.

Um eine ausreichende Spannungsfestigkeit des Halbleiterbauelements zu erreichen ist es erforderlich, einen ausreichend großen Abstand zwischen der Vorderseite des Halbleiterchips und dem Chipträger vorzusehen. Andererseits ist es vorteilhaft, diesen Abstand nicht zu groß zu wählen, da sich hierdurch insbesondere die Wärmeableitung vom Halbleiterchip über zur Kontaktierung verwendete Lotkugel zum Chipträger unnötig verschlechtert.Around a sufficient dielectric strength of the semiconductor device It is necessary to reach a sufficiently large distance provide between the front of the semiconductor chip and the chip carrier. On the other hand, it is advantageous not to choose this distance too large because This in particular the heat dissipation from the semiconductor chip to the Contacting used solder ball to the chip carrier unnecessarily deteriorated.

Üblicherweise wird eine Flipchip-Anordnung mittels an den Anschlusskontakten angeordneten Lotkugeln die auch als "Solder Balls" bezeichnet werden, aus einem niedrigschmelzenden Metall bzw. einer niedrigschmelzenden Legierung realisiert. Bei der Montage wird der Halbleiterchip mit den Lotkugeln auf den aufgeheizten Chipträger gesetzt, wobei die Lotkugeln schmelzen und so den Halbleiterchip mit dem Chipträger elektrisch und mechanisch verbinden. Diese Anordnung weist jedoch den Nachteil auf, dass es schwierig ist, mit derartigen Lotkugeln einen definierten Abstand einzustellen.Usually a flip-chip arrangement is arranged by means of solder balls arranged on the connection contacts which also called "Solder Balls " be made of a low-melting metal or a low-melting Alloy realized. During assembly, the semiconductor chip with set the solder balls on the heated chip carrier, wherein the solder balls melt and so the semiconductor chip with the chip carrier electrically and connect mechanically. However, this arrangement has the disadvantage that it is difficult with such solder balls a defined To adjust the distance.

Bei derartigen Halbleiterchips mit Flipchip-Anordnung müssen insbesondere der erste und der zweite Anschlusskontakt jeweils mit einem elektrisch leitenden Anschluss kontaktiert werden. Da diese beiden Anschlusskontakte auf derselben Seite des Halbleiterchips angeordnet sind, dürfen die entsprechenden elektrischen Anschlüsse nicht elektrisch leitend miteinander verbunden sein, was die Verwendung eines vollmetallischen Chipträgers erschwert. Alternativ zu einem vollmetallischen Chipträger werden auch Chipträger mit einem elektrisch isolierenden Träger verwendet, die mit einer strukturierten Metallisierung versehen sind und die außerdem noch eine gute Wärmeleitfähigkeit aufweisen. Derartige Chipträger, beispielsweise mit Kupfer beschichtete Keramikträger, sogenannte DCB-Substrate (DCB = Direct Copper Bonding), weisen den Nachteil auf, dass sie teuer in der Herstellung sind.at Such semiconductor chips with flip-chip arrangement must in particular the first and the second terminal contact each with an electrical conductive connection to be contacted. Because these two connectors are arranged on the same side of the semiconductor chip, the corresponding electrical connections not electrically conductive be related to each other, resulting in the use of a full metallic chip carrier difficult. Alternatively to a full metallic chip carrier also chip carrier used with an electrically insulating support that with a structured metallization are provided and the moreover a good thermal conductivity exhibit. Such chip carriers, For example, coated with copper ceramic carrier, so-called DCB substrates (DCB = direct copper bonding), have the disadvantage that they are expensive to produce.

Es ist daher die Aufgabe der vorliegenden Erfindung, ein Halbleiterbauelement mit einem Halbleiterchip bereitzustellen, das elektrisch mit einem preiswerten Chipträger kontaktiert ist, und bei dem ein einzuhaltender Mindestabstand zwischen dem Halbleiterchip und dem Chipträger auf einfache Weise eingestellt ist.It Therefore, the object of the present invention is a semiconductor device with a semiconductor chip that is electrically cheap chip carrier is contacted, and in which a minimum distance between the semiconductor chip and the chip carrier set in a simple manner is.

Diese Aufgabe wird durch ein Halbleiterbauelement gemäß den Merkmalen des Anspruchs 1 gelöst. Vorteilhafte Ausgestaltungen der Erfindung sind Gegenstand der Unteransprüche.These The object is achieved by a semiconductor component according to the features of the claim 1 solved. Advantageous embodiments of the invention are the subject of the dependent claims.

Das Halbleiterbauelement umfasst einen Halbleiterchip und einen Chipträger, wobei der Halbleiterchip eine erste Seite aufweist, die dem Chipträger zugewandt ist und an der ein erster Anschlusskontakt und ein zweiter Anschlusskontakt angeordnet sind. Der Chipträger umfasst des weiteren einen ersten Chipträgerteil und einen von diesem beabstandeten zweiten Chipträgerteil. Eine erste Kontaktschicht ist zwischen dem ersten Anschlusskontakt und dem ersten Chipträgerteil angeordnet und verbindet diese elektrisch leitend miteinander. Entsprechend ist eine zweite Kontaktschicht zwischen dem zweiten Anschlusskontakt und dem zweiten Chipträgerteil angeordnet und verbindet diese ebenfalls elektrisch leitend miteinander.The semiconductor component comprises a semiconductor chip and a chip carrier, wherein the semiconductor chip has a first side, which faces the chip carrier and on which a first connection contact and a second connection contact are arranged. The chip carrier further comprises a first chip carrier part and a second chip carrier part spaced therefrom. A first contact layer is arranged between the first connection contact and the first chip carrier part and connects them to one another in an electrically conductive manner. Entspre Accordingly, a second contact layer between the second terminal contact and the second chip carrier member is arranged and connects them also electrically conductive with each other.

Die Dicken der ersten und zweiten Kontaktschicht in einer vertikalen Richtung des Halbleiterchips sind so gewählt, dass zwischen der Vorderseite des Halbleiterchips und dem Chipträger ein vorgegebener minimaler Abstand nicht unterschritten ist. Dieser minimale Abstand ist dabei unter Berücksichtigung einer gewünschten Spannungsfestigkeit des Bauelementes gewählt und insbesondere so gewählt, dass eine vorgegebene Mindestspannungsfestigkeit erreicht wird.The Thicknesses of the first and second contact layers in a vertical Direction of the semiconductor chip are chosen so that between the front of the Semiconductor chips and the chip carrier a predetermined minimum distance is not fallen below. This minimum distance is taking into account a desired Dielectric strength of the component selected and in particular chosen so that a predetermined minimum voltage resistance is achieved.

Die erste bzw. zweite Kontaktschicht dienen als Abstandhalter zwischen dem Chipträger und dem Halbleiterchip. Da mit zunehmender Dicke der ersten bzw. zweiten Kontaktschicht der Wärmewiderstand zwischen Halbleiterchip und Chipträger steigt und da die Kosten sowie der Zeitbedarf für die Herstellung derartiger Kontaktschichten mit deren Schichtdicke ansteigen, ist die Dicke Idealerweise so gewählt, dass die erforderliche Isolationsfestigkeit, ggf. unter Berücksichtigung einer bestimmten Sicherheitszuschlages, gerade erreicht ist.The first and second contact layer serve as a spacer between the chip carrier and the semiconductor chip. Since with increasing thickness of the first or second contact layer of the thermal resistance between Semiconductor chip and chip carrier rises and there the costs as well as the time needed for the production of such Contact layers with their layer thickness increase, is the thickness Ideally chosen so that the required insulation resistance, if necessary under consideration a certain security surcharge, has just been reached.

Bei der Herstellung eines erfindungsgemäßen Halbleiterbauelements wird die erste bzw. zweite Kontaktschicht vorzugsweise auf den ersten bzw. zweiten Anschlusskontakt des Halbleiterchips aufgebracht.at the production of a semiconductor device according to the invention is the first or second contact layer preferably on the first or second terminal contact of the semiconductor chip applied.

Anschließend wird der Halbleiterchip mittels Lötverbindungen, die zwischen dem Chipträger und der ersten bzw. zweiten Kontaktschicht angeordnet sind, miteinander verbunden. Dabei ist es vorteilhaft, wenn der Schmelzpunkt der ersten und zweiten Kontaktschicht höher ist als der Schmelzpunkt des dabei verwendeten, externen Anschluss-Lotes von vorzugsweise 180°C-230°C. Dadurch ist es möglich, das Halbleiterbauteil mit dem Chipträger, beispielsweise einem PCB-Träger (PCB = Printed Circuit Board), zu verlöten, ohne gleichzeitig die erste und zweite Kontaktschicht aufzuschmelzen. Der Schmelzpunkt der ersten bzw. zweiten Kontaktschicht liegt vorzugsweise über 260°C und damit über dem Schmelzpunkt typischer Lotkugeln von üblicherweise zwischen 180°C und 230°C.Subsequently, will the semiconductor chip by means of solder joints, the between the chip carrier and the first and second contact layers are arranged with each other connected. It is advantageous if the melting point of the first and second contact layer higher is the melting point of the external connection solder used of preferably 180 ° C-230 ° C. Thereby is it possible that Semiconductor device with the chip carrier, for example, a PCB carrier (PCB = Printed Circuit Board), to be soldered without removing the melt first and second contact layer. The melting point the first or second contact layer is preferably above 260 ° C and thus above the Melting point of typical solder balls usually between 180 ° C and 230 ° C.

Ebenso ist es möglich, die Kontaktschichten auf geeignete Stellen des Chipträgers aufzubringen und sie dann mit den betreffenden Anschlusskontakten des Halbleiterchips zu verlöten.As well Is it possible, apply the contact layers to suitable locations of the chip carrier and They then with the relevant terminal contacts of the semiconductor chip to solder.

Der Chipträger umfasst bevorzugt einen ersten und einen zweiten Chipträgerteil, die voneinander beabstandet sind. Der erste und zweite Chipträgerteil können bei der Herstellung des Halbleiterbauelementes, insbesondere bei der Herstellung der oben genannten Lötverbindung zwischen den Kontaktschichten und dem Chipträger, fest miteinander verbunden sein und in einem späteren Verfahrensschritt voneinander getrennt werden. Dieses Verfahren erleichtert die Justierung zwischen dem Halbleiterchip und dem ersten bzw. zweiten Chipträgerteil. Des Weiteren ermöglicht sie die Verwendung eines vollmetallischen Chipträgers, da der erste und der zweite Chipträgerteil nach der Trennung nicht mehr elektrisch leitend miteinander verbunden sind.Of the chip carrier preferably comprises a first and a second chip carrier part, which are spaced from each other. The first and second chip carrier part can at the production of the semiconductor device, in particular in the Production of the above-mentioned solder joint between the contact layers and the chip carrier, firmly connected together his and later Process step are separated. This method facilitates the adjustment between the semiconductor chip and the first or second chip carrier part. Furthermore, it allows they use a full metallic chip carrier, since the first and the second chip carrier part no longer electrically connected to each other after separation are.

Zur Erhöhung der Isolationsfestigkeit ist es vorgesehen, zwischen den Halbleiterchip und den Chipträger ein Isolationsmaterial einzubringen. Das Isolationsmaterial wird bevorzugt in den zwischen den Halbleiterchip und dem Chipträger ausgebildeten Zwischenraum eingegossen oder eingespritzt. Besonders bevorzugt wird als Isolationsmaterial eine Vergussmasse verwendet, mit der zumindest der Halbleiterchip des Halbleiterbauelementes während eines nachfolgenden Verfahrensschrittes vergossen bzw. umspritzt wird.to increase the insulation resistance is provided between the semiconductor chip and the chip carrier to introduce an insulation material. The insulation material is preferably in the formed between the semiconductor chip and the chip carrier Gap poured or injected. Especially preferred is used as insulation material, a potting compound with the at least the semiconductor chip of the semiconductor device during a potted or encapsulated following process step.

Die typischerweise verwendeten Isolationsmaterialien bzw. Vergussmassen weisen eine Isolationsfestigkeit von vorzugsweise über 50V/μm auf.The typically used insulation materials or potting compounds have an insulation resistance of preferably over 50V / μm.

Die Herstellung der ersten und/oder zweiten Kontaktschicht kann beispielsweise mittels physikalischer (PVD = Physical Vapour Deposition) oder chemischer (CVD = Chemical Vapour Deposition) Abscheidung aus der Gasphase, mittels galvanischer bzw. stromloser Abscheidung oder durch Sputtern erfolgen. Die Abscheidung erfolgt vorzugsweise auf einer mit Öffnungen versehenen Maskenschicht. Bevorzugte Materialien für die erste und zweite Kontaktschicht sind Kupfer, Aluminium und weitere Metalle wie z.B. Gold, Silber, Zinn, Titan, oder Nickel oder Legierungen mit zumindest einem dieser Metalle.The Production of the first and / or second contact layer can be, for example by means of physical (PVD = Physical Vapor Deposition) or chemical (CVD = Chemical Vapor Deposition) deposition from the gas phase, by means of galvanic or currentless deposition or by sputtering respectively. The deposition is preferably carried out on one with openings provided mask layer. Preferred materials for the first and second contact layer are copper, aluminum and other metals such as e.g. Gold, silver, tin, titanium, or nickel or alloys with at least one of these metals.

Das erfindungsgemäße Halbleiterbauelement wird nachfolgend anhand der beigefügten Figuren näher erläutert. In den Figuren bezeichnen, sofern nicht anders angegeben, gleiche Bezugszeichen gleiche Teile mit gleicher Bedeutung. Es zeigen:The inventive semiconductor device will be explained in more detail with reference to the accompanying figures. In denote the figures, unless otherwise stated, the same reference numerals Parts with the same meaning. Show it:

1 einen Querschnitt durch ein erfindungsgemäßes Halbleiterbauelement, bei dem ein für die Isolationsfestigkeit zwischen einem Halbleiterchip und einem Chipträger minimal einzuhaltender Abstand unter Verwendung von Kontaktschichten eingestellt ist, 1 a cross section through a semiconductor device according to the invention, in which a distance to be minimally observed for the insulation resistance between a semiconductor chip and a chip carrier is set by using contact layers,

2 das Halbleiterbauelement gemäß 1 in Draufsicht, und 2 the semiconductor device according to 1 in plan view, and

3 ein Halbleiterbauelement entsprechend 2, bei dem der Steueranschluss des ersten Halbleiterchips mit einem Anschlussbein elektrisch verbunden ist, in Draufsicht. 3 a semiconductor device corresponds accordingly 2 in which the control terminal of the first semiconductor chip is electrically connected to a connection leg, in plan view.

1 zeigt in Seitenansicht im Querschnitt ein Halbleiterbauelement mit einem Halbleiterchip 1, der einen ersten und zweiten Anschlusskontakt 1a, 1b aufweist, die an einer ersten Seite 1d des Halbleiterchips 1 angeordnet sind. Auf einer der ersten Seite 1d gegenüberliegenden zweiten Seite 1e ist ein dritter Anschlusskontakt 1c angeordnet. In dem ersten Halbleiterchip 1 ist ein Leistungstransistor, beispielsweise ein MOSFET, ein IGBT, ein Thyristor oder ein Bipolartransistor realisiert, wobei der erste und dritte Anschlusskontakt 1a, 1c Lastanschlüsse dieses Leistungstransistors und der zweite Anschlusskontakt 1b einen Steueranschluss dieses Leistungstransistors bilden. Bei einem als MOSFET oder IGBT ausgebildeten vertikalen Leistungstransistor stellt der erste Anschlusskontakt 1a beispielsweise den Source-Anschluss, der zweite Anschlusskontakt 1b den Gate-Anschluss und der dritte Anschlusskontakt 1c den Drain-Anschluss dar. 1 shows in side view in cross section a semiconductor device with a semiconductor chip 1 that has a first and second terminal contact 1a . 1b which is on a first side 1d of the semiconductor chip 1 are arranged. On one of the first page 1d opposite second side 1e is a third connection contact 1c arranged. In the first semiconductor chip 1 is realized a power transistor, for example a MOSFET, an IGBT, a thyristor or a bipolar transistor, wherein the first and third terminal contact 1a . 1c Load terminals of this power transistor and the second terminal contact 1b form a control terminal of this power transistor. In a vertical power transistor designed as a MOSFET or IGBT, the first terminal makes contact 1a for example, the source terminal, the second terminal contact 1b the gate terminal and the third terminal contact 1c the drain connection.

Der erste Anschlusskontakt 1a und der zweite Anschlusskontakt 1b des Halbleiterchips 1 sind mit einer ersten Kontaktschicht 6a bzw. einer zweiten Kontaktschicht 6b versehen. Diese Kontaktschichten 6a, 6b sind wegen der guten elektrischen und thermischen Leitfähigkeit beispielsweise aus Kupfer, Aluminium oder einer Legierung dieser Metalle gebildet. Die Herstellung dieser Kontaktschichten 6a, 6b erfolgt bevorzugt mittels eines Abscheideverfahrens, bei dem Teilchen aus einer flüssigen Phase oder einer Gasphase physikalisch oder chemisch abgeschieden werden. Die Abscheidung erfolgt vorzugsweise auf eine erste Maskenschicht, die auf die erste Seite 1d des Halbleiterchips 1 aufgebracht ist.The first connection contact 1a and the second terminal contact 1b of the semiconductor chip 1 are with a first contact layer 6a or a second contact layer 6b Mistake. These contact layers 6a . 6b are formed because of the good electrical and thermal conductivity, for example, copper, aluminum or an alloy of these metals. The production of these contact layers 6a . 6b is preferably carried out by means of a deposition process in which particles are separated from a liquid phase or a gas phase physically or chemically. The deposition preferably takes place on a first mask layer which is on the first side 1d of the semiconductor chip 1 is applied.

Der Halbleiterchip 1 bildet zusammen mit der ersten Kontaktschicht 6a und der zweiten Kontaktschicht 6b eine Einheit. Diese Einheit ist mittels Lotverbindungen 7a, 7b mit einem Chipträger verbunden, der einen ersten Chipträgerteil 2a sowie einen in einer lateralen Richtung des Halbleiterchips 1 dazu beabstandeten zweiten Chipträgerteil 2b umfasst. Die Lotverbindungen 7a, 7b können beispielsweise dadurch erzeugt werden, dass die Kontaktschichten 6a, 6b zunächst mit einer Lotschicht versehen werden. Anschließend kann die Einheit aus Halbleiterchip 1, den Kontaktschichten 6a, 6b sowie den Lotschichten 7a, 7b mit dem aufgeheizten Chipträger 2a, 2b kontaktiert werden, so dass die Lote zunächst schmelzen und anschließend nach dem Aushärten die Lotverbindungen 7a, 7b bilden. Damit sind der Halbleiterchip 1 und der Chipträger 2a, 2b miteinander verbunden und in vertikaler Richtung, das heißt in einer Richtung senkrecht zur ersten Seite 1d des Halbleiterchips 1, voneinander beabstandet.The semiconductor chip 1 forms together with the first contact layer 6a and the second contact layer 6b one unity. This unit is by means of solder joints 7a . 7b connected to a chip carrier having a first chip carrier part 2a and one in a lateral direction of the semiconductor chip 1 spaced second chip carrier part 2 B includes. The solder joints 7a . 7b can be generated for example by the fact that the contact layers 6a . 6b be first provided with a layer of solder. Subsequently, the unit of semiconductor chip 1 , the contact layers 6a . 6b as well as the solder layers 7a . 7b with the heated chip carrier 2a . 2 B be contacted so that the solders melt first and then after curing the solder joints 7a . 7b form. This is the semiconductor chip 1 and the chip carrier 2a . 2 B connected together and in the vertical direction, that is in a direction perpendicular to the first side 1d of the semiconductor chip 1 , spaced from each other.

Um die Isolationsfestigkeit zwischen dem Halbleiterchip 1 und dem Chipträger 2a, 2b weiter zu erhöhen, ist es vorteilhaft, in den Zwischenraum zwischen dem Halbleiterchip 1 und dem Chipträger 2a, 2b ein Isolationsmaterial 8a-8d einzubringen, bevorzugt einzuspritzen oder einzugießen. Dieses Isolationsmaterial 8a-8d ist vorzugsweise Bestandteil einer Vergussmasse 8, die den Halbleiterchip 1 vollständig umschließt, und die ein Gehäuse des Halbleiterbauelements bildet.To the insulation strength between the semiconductor chip 1 and the chip carrier 2a . 2 B To further increase, it is advantageous in the space between the semiconductor chip 1 and the chip carrier 2a . 2 B an insulation material 8a-8d bring in, preferably inject or pour. This insulation material 8a-8d is preferably part of a potting compound 8th that the semiconductor chip 1 completely encloses, and forms a housing of the semiconductor device.

Der zur Isolationsfestigkeit erforderliche Mindestabstand zwischen dem Halbleiterchip 1 und dem Chipträger 2a, 2b ist insbesondere durch das Material des Isolationsmaterials 8a bis 8d bestimmt. Wird als Isolationsmaterial 8a bis 8d eine Vergussmasse 8 verwendet, so lässt sich damit eine Isolationsfestigkeit von typischerweise größer 50 V/μm erreichen. Bei einer erforderlichen Isolationsfestigkeit von 2000 V ergibt sich damit eine vertikale Dicke d1 bzw. d2 der ersten bzw. zweiten Kontaktschicht 6a bzw. 6b von größer 40 μm. Durch die Dicken d1 bzw. d2 ergibt sich ein Minimalabstand zwischen dem Halbleiterchip 1 und dem Chipträger 2a, 2b. Die vertikalen Dicken der Lotverbindungen 7a, 7b können so dünn ausgeführt werden, dass sie gegenüber den vertikalen Dicken d1, d2 der ersten bzw. zweiten Kontaktschicht 6a bzw. 6b vernachlässigbar sind.The required for insulation resistance minimum distance between the semiconductor chip 1 and the chip carrier 2a . 2 B is in particular by the material of the insulating material 8a to 8d certainly. Used as insulation material 8a to 8d a potting compound 8th used, it can thus achieve an insulation resistance of typically greater than 50 V / micron. With a required insulation strength of 2000 V, this results in a vertical thickness d1 or d2 of the first and second contact layer 6a respectively. 6b greater than 40 μm. The thicknesses d1 and d2 result in a minimum distance between the semiconductor chip 1 and the chip carrier 2a . 2 B , The vertical thicknesses of the solder joints 7a . 7b can be made so thin that they are opposite to the vertical thicknesses d1, d2 of the first and second contact layers, respectively 6a respectively. 6b are negligible.

In 2 ist eine Draufsicht auf das Halbleiterbauelement gemäß 1 dargestellt. Die Vergussmasse ist in der Darstellung gemäß 2 weggelassen, lediglich die äußeren Abmessungen des durch die Vergussmasse 8 gebildeten Gehäuses sind gestrichelt dargestellt. Die Ansicht zeigt den Halbleiterchip 1 mit Blick auf die zweite Seite 1e des Halbleiterchips 1 und damit auf den an der zweiten Seite 1e angeordneten dritten Anschlusskontakt 1c.In 2 is a plan view of the semiconductor device according to 1 shown. The potting compound is in the illustration according to 2 omitted, only the outer dimensions of the potting compound 8th formed housing are shown in dashed lines. The view shows the semiconductor chip 1 overlooking the second page 1e of the semiconductor chip 1 and thus on the second page 1e arranged third terminal contact 1c ,

Die an der der zweiten Seite 1e gegenüberliegenden ersten Seite 1d angeordneten Anschlusskontakte 1a, 1b sind jeweils gestrichelt angedeutet. Wie aus 2 ersichtlich ist, ragen die beiden Chipträgerteile 2a, 2b in lateraler Richtung des ersten Halbleiterchips 1 in dem Beispiel über diesen hinaus.The at the second page 1e opposite first side 1d arranged connection contacts 1a . 1b are each indicated by dashed lines. How out 2 it can be seen, protrude the two chip carrier parts 2a . 2 B in the lateral direction of the first semiconductor chip 1 in the example beyond this.

Vor der Herstellung der in 1 dargestellten Lotverbindungen 7a, 7b zwischen der ersten bzw. zweiten Kontaktschicht 6a bzw. 6b sind der erste Chipträgerteil 2a und der zweite Chipträgerteil 2b mittels eines in 2 gestrichelt dargestellten Verbindungssteges 2c miteinander verbunden. Eine derartiger Verbindungssteg 2c erleichtert die Positionierung des Halbleiterchips 1 in Bezug auf den ersten bzw. zweiten Chipträgerteil 2a bzw. 2b. Der Verbindungssteg 2c kann nach dem Herstellen der Lotverbindungen 7a, 7b, bevorzugt nach dem Vergießen zumindest des Halbleiterchips 1, entfernt werden, wodurch der zwei voneinander beabstandete Chipträgerteile 2a, 2b umfassende Chipträger 2 entsteht. In entsprechender Weise kann der Chipträger 2 auch mehr als zwei Chipträgerteile 2a, 2b umfassen, die vor dem Vereinzeln durch eine entsprechend höhere Anzahl von Verbindungsstegen miteinander verbunden sind. Das Vereinzeln kann dabei so erfolgen, dass kein, ein, mehrere oder alle Chipträgerteile aus dem Gehäuse herausgeführt sind.Before making the in 1 illustrated solder joints 7a . 7b between the first and second contact layer 6a respectively. 6b are the first chip carrier part 2a and the second chip carrier part 2 B by means of an in 2 dashed lines shown connecting web 2c connected with each other. Such a connecting bridge 2c facilitates the positioning of the semiconductor chip 1 with respect to the first and second chip carrier parts, respectively 2a respectively. 2 B , The connecting bridge 2c can after making the solder joints 7a . 7b , preferably after the casting of at least the semiconductor chip 1 , are removed, eliminating the two spaced apart chip carrier parts 2a . 2 B comprehensive chip carrier 2 arises. In a corresponding manner, the chip carrier 2 also more than two chip carrier parts 2a . 2 B include, which are connected to each other by a correspondingly higher number of connecting webs prior to separation. The singulation can take place in such a way that none, one, several or all chip carrier parts are led out of the housing.

Die Ansteuerung des in dem ersten Halbleiterchip integrierten Bauelements erfolgt optional mittels eines Steuerschaltkreises, der in einem zweiten Halbleiterchip 3 integriert ist, der in dem Beispiel auf dem ersten Chipträgerteil 2a angeordnet ist. Die dem ersten Chipträgerteil 2a zugewandte Seite dieses zweiten Halbleiterchips 3 kann dabei elektrisch leitend mit dem zweiten Chipträgerteil 2a verbunden sein, oder kann elektrisch gegenüber diesem zweiten Chipträgerteil 2a isoliert sein. Um diesen zweiten Halbleiterchip 3 isoliert auf dem zweiten Chipträgerteil 2a aufzubringen, ist dieser Halbleiterchip 3 beispielsweise mittels eines elektrisch isolierenden Klebers auf das Chipträgerteil 2a aufgeklebt.The control of the component integrated in the first semiconductor chip takes place optionally by means of a control circuit which is located in a second semiconductor chip 3 integrated in the example on the first chip carrier part 2a is arranged. The first chip carrier part 2a facing side of this second semiconductor chip 3 can be electrically conductive with the second chip carrier part 2a be connected, or may be electrically opposite this second chip carrier part 2a be isolated. To this second semiconductor chip 3 isolated on the second chip carrier part 2a to apply, is this semiconductor chip 3 for example by means of an electrically insulating adhesive on the chip carrier part 2a glued.

Des weiteren umfasst das erfindungsgemäße Halbleiterbauelement zu seiner äußeren Kontaktierung und Montage Anschlussbeine 4a – 4g. Ein aus dem durch die Vergussmasse gebildeten Gehäuse herausragendes erstes Anschlussbein 4a kontaktiert den an der zweiten Seite 1e des ersten Halbleiterchips 1 angeordneten dritten Anschlusskontakt 1c. Hierzu ist der dritte Anschlusskontakt 1c mittels eines Bonddrahtes 5a mit dem ersten Anschlussbein 4a verbunden. Ein zweites Anschlussbein 4c ist bevorzugt einstückig mit dem ersten Chipträgerteil 2a verbunden, um den an der ersten Seite 1d angeordneten ersten Anschlusskontakt 1a des ersten Halbleiterchips 1 zu kontaktieren. Das zweite Chipträgerteil 2b und mögliche weitere Chipträgerteile weisen in dem Ausführungsbeispiel keine unmittelbar nach außen reichende elektrisch leitende Verbindung auf. Wie bereits erläutert, entspricht der zweite Anschlusskontakt 1b beispielsweise einem Steueranschluss eines in dem ersten Halbleiterchip 1 integrierten Leistungsbauelements, wobei in dem Ausführungsbeispiel eine Ansteuerung dieses Bauelements über den auf den ersten Chipträgerteil 2a aufgebrachten Steuerschaltkreis 3 erfolgt. Der Steuerschaltkreis 3 ist hierfür mittels eines Bonddrahtes 5b an dem zweiten Chipträgerteil angeschlossen. Der Steuerschaltkreis 3 weist weitere Anschlüsse auf, die mittels Bonddrähten 5d, 5e, 5f, 5g an aus dem Gehäuse herausragende Anschlussbeine 4d, 4e, 4f, 4g angeschlossen sind. Außerdem ist ein weiterer Anschluss des Steuerschaltkreises 3 an dem mit dem ersten Chipträgerteil 2a verbundenen Anschluss 4c über einen Bonddraht 5d angeschlossen, um diesen Anschluss des Steuerschaltkreises 3 auf das Potential des ersten Anschlusskontaktes 1a des Bauelements zu legen.Furthermore, the semiconductor component according to the invention comprises connection legs for its external contacting and mounting 4a - 4g , A protruding from the housing formed by the potting compound first connecting leg 4a contacts the one on the second page 1e of the first semiconductor chip 1 arranged third terminal contact 1c , For this purpose, the third connection contact 1c by means of a bonding wire 5a with the first connecting leg 4a connected. A second connecting leg 4c is preferably integral with the first chip carrier part 2a connected to the one on the first page 1d arranged first terminal contact 1a of the first semiconductor chip 1 to contact. The second chip carrier part 2 B and possible further chip carrier parts have in the exemplary embodiment on no directly outwardly reaching electrically conductive connection. As already explained, the second connection contact corresponds 1b for example, a control terminal of one in the first semiconductor chip 1 integrated power component, wherein in the embodiment, a control of this device via the on the first chip carrier part 2a applied control circuit 3 he follows. The control circuit 3 is for this purpose by means of a bonding wire 5b connected to the second chip carrier part. The control circuit 3 has further connections that by means of bonding wires 5d . 5e . 5f . 5g on protruding from the housing connecting legs 4d . 4e . 4f . 4g are connected. In addition, another connection of the control circuit 3 at the one with the first chip carrier part 2a connected connection 4c over a bonding wire 5d connected to this connection of the control circuit 3 to the potential of the first connection contact 1a to lay the component.

Bei Integration eines Leistungs-MOSFETs oder Leistungs-IGBTs in dem ersten Halbleiterchip 1 bildet das erste Anschlussbein 4a beispielsweise den von Außen zugänglichen Drain-Anschluss des Bauelements, das zweite Anschlussbein 4c den von Außen zugänglichen Source-Anschluss des Bauelements, während der Gate-Anschluss nicht unmittelbar von Außen zugänglich ist, sondern über den Steuerschaltkreis 3 angesteuert ist, der von Außen zugängliche Ein- und Ausgänge 4d-4g aufweist.When integrating a power MOSFET or power IGBT in the first semiconductor chip 1 forms the first connecting leg 4a for example, the externally accessible drain terminal of the device, the second connecting leg 4c the externally accessible source terminal of the device, while the gate terminal is not directly accessible from the outside, but via the control circuit 3 is controlled, the externally accessible inputs and outputs 4d-4g having.

Die äußere Abgrenzung der Vergussmasse 8 ist gestrichelt dargestellt. Die Vergussmasse 8 umschließt zumindest den Halbleiterchip 1, darüber hinaus bevorzugt die Kontaktschicht 6a, 6b und zumindest abschnittweise den ersten und zweiten Chipträgerteil 2a, 2b. Der erste Chipträgerteil 2a weist besonders bevorzugt eine dem Halbleiterchip 1 abgewandte, erste Seite 2h auf, die zumindest nicht vollständig von der Vergussmasse 8 umschlossen ist. Dadurch kann die erste Seite 1h des ersten Chipträgerteils 2a zur elektrischen und/oder thermischen Kontaktierung des Halbleiterbauelementes verwendet werden.The outer boundary of the potting compound 8th is shown in dashed lines. The potting compound 8th encloses at least the semiconductor chip 1 , moreover, preferably the contact layer 6a . 6b and at least in sections, the first and second chip carrier part 2a . 2 B , The first chip carrier part 2a particularly preferably has a semiconductor chip 1 opposite, first page 2h at least not completely from the potting compound 8th is enclosed. This can be the first page 1h of the first chip carrier part 2a be used for electrical and / or thermal contacting of the semiconductor device.

Nach dem Entfernen des Verbindungssteges 2c weisen der erste und zweite Chipträgerteil 2a bzw. 2b Fortsätze 2d bzw. 2e auf, deren Enden 2f bzw. 2g nicht von der Vergussmasse 8 bedeckt sind. Die Enden 2f bzw. 2g sind jedoch nicht zur äußeren Kontaktierung des Halbleiterbauelements vorgesehen und nach dem Vereinzeln elektrisch voneinander getrennt.After removing the connecting bar 2c have the first and second chip carrier part 2a respectively. 2 B projections 2d respectively. 2e on, their ends 2f respectively. 2g not from the potting compound 8th are covered. The ends 2f respectively. 2g However, are not provided for external contacting of the semiconductor device and separated electrically after separation from each other.

Anders als in 2 gezeigt, kann der zweite Chipträgerteil 2b von Außen kontaktierbar sein. Dies ist beispielhaft in 3 dargestellt. Der zweite Chipträger 2b ist mittels eines Bonddrahtes 5i elektrisch leitend mit einem Anschlussbein 4g verbunden, das aus dem Gehäuse 8 heraus ragt und somit von Außen kontaktierbar ist.Unlike in 2 shown, the second chip carrier part 2 B be contacted from the outside. This is exemplary in 3 shown. The second chip carrier 2 B is by means of a bonding wire 5i electrically conductive with a connecting leg 4g connected to the housing 8th protrudes out and thus contactable from the outside.

In dem dargestellten Ausführungsbeispiel ist der zweite Chipträgerteil 2b mit dem Steueranschluss 1b des ersten Halbleiterchips 1 elektrisch verbunden. Auf diese Weise ist es möglich, den ersten Halbleiterchip 1 mittels eines von Außen an das Anschlussbein 4g angelegten Steuersignals anzusteuern. Der Bonddraht 5h, der den Steuerschaltkreis 3 elektrisch leitend mit dem zweiten Chipträgerteil 2b verbindet, ist dann optional und kann beispielsweise dazu genutzt werden, die am zweiten Chipträgerteil 2b bzw. die am zweiten Anschlusskontakt 1b anliegende Spannung zu detektieren, oder beispielsweise den ersten Halbleiterchip 1 anzusteuern, insbesondere an- oder abzuschalten.In the illustrated embodiment, the second chip carrier part 2 B with the control terminal 1b of the first semiconductor chip 1 electrically connected. In this way it is possible to use the first semiconductor chip 1 by means of a from the outside to the connecting leg 4g to control applied control signal. The bonding wire 5h that the control circuit 3 electrically conductive with the second chip carrier part 2 B connects, is then optional and can be used, for example, to the second chip carrier part 2 B or at the second connection contact 1b to detect applied voltage, or for example the first semiconductor chip 1 to turn on, in particular on or off.

Das Anschlussbein 4g kann insbesondere an dem zweiten Chipträgerteil 2b einstückig angeformt sein. Auf den Bonddraht 5i kann dann verzichtet werden.The connecting leg 4g can in particular on the second chip carrier part 2 B be integrally formed. On the bonding wire 5i can then verzich be.

11
erster Halbleiterchipfirst Semiconductor chip
1a1a
erster Anschlusskontaktfirst connection contact
1b1b
zweiter Anschlusskontaktsecond connection contact
1c1c
dritter Anschlusskontaktthird connection contact
1d1d
erste Seite des ersten Halbleiterchipsfirst Side of the first semiconductor chip
1e1e
zweite Seite des ersten Halbleiterchipssecond Side of the first semiconductor chip
22
Chipträgerchip carrier
2a2a
erster Chipträgerteilfirst Chip carrier part
2b2 B
zweiter Chipträgerteilsecond Chip carrier part
2c2c
Verbindungsstegconnecting web
2d2d
Ansatz des ersten Chipträgerteilsapproach of the first chip carrier part
2e2e
Ansatz des zweiten Chipträgerteilsapproach of the second chip carrier part
2f2f
Ende des Ansatzes des ersten ChipträgerteilsThe End the approach of the first chip carrier part
2g2g
Ende des Ansatzes des zweiten ChipträgerteilsThe End the approach of the second chip carrier part
2h2h
erste Seite des ersten Chipträgerteilsfirst Side of the first chip carrier part
33
SteuerschaltkreisControl circuit
4a-4g4a-4g
Anschlussbeinconnecting leg
5a, 5c-5i5a, 5c-5i
Bonddrahtbonding wire
6a6a
erste Kontaktschichtfirst contact layer
6b6b
zweite Kontaktschichtsecond contact layer
7a, 7b7a, 7b
Lotverbindungsolder
88th
Vergussmasse, Gehäusepotting compound casing
8a-8d8a-8d
Isolationsschichtinsulation layer
d1d1
Dicke der ersten Kontaktschichtthickness the first contact layer
d2d2
Dicke der zweiten Kontaktschichtthickness the second contact layer

Claims (14)

Halbleiterbauelement mit wenigstens einem ersten Halbleiterchip (1) und einem Chipträger (2), wobei der Halbleiterchip (1) eine erste Seite aufweist, die dem Chipträger (2) zugewandt ist und an der ein erster Anschlusskontakt (1a) und ein zweiter Anschlusskontakt (1b) angeordnet sind, der Chipträger (2) einen ersten Chipträgerteil (2a) und zumindest einen zu diesem beabstandeten zweiten Chipträgerteil (2b) aufweist, eine erste Kontaktschicht (6a) zwischen dem ersten Anschlusskontakt (1a) und dem ersten Chipträgerteil (2a) angeordnet ist und diese elektrisch leitend miteinander verbindet, eine zweite Kontaktschicht (6b) zwischen dem zweiten Anschlusskontakt (1b) und dem zweiten Chipträgerteil (2b) angeordnet ist und diese elektrisch leitend miteinander verbindet, und die Dicken (d1, d2) der ersten (6a) und zweiten (6b) Kontaktschicht in einer vertikalen Richtung so gewählt sind, dass zwischen dem Halbleiterchip (1) und dem Chipträger (2) ein vorgegebener minimal einzuhaltender Abstand nicht unterschritten ist.Semiconductor device having at least one first semiconductor chip ( 1 ) and a chip carrier ( 2 ), wherein the semiconductor chip ( 1 ) has a first side facing the chip carrier ( 2 ) and at which a first connection contact ( 1a ) and a second connection contact ( 1b ), the chip carrier ( 2 ) a first chip carrier part ( 2a ) and at least one spaced apart second chip carrier part ( 2 B ), a first contact layer ( 6a ) between the first connection contact ( 1a ) and the first chip carrier part ( 2a ) is arranged and this electrically conductively connects, a second contact layer ( 6b ) between the second terminal contact ( 1b ) and the second chip carrier part ( 2 B ) is arranged and this electrically conductively connects, and the thicknesses ( d1 . d2 ) the first ( 6a ) and second ( 6b ) Contact layer in a vertical direction are selected such that between the semiconductor chip ( 1 ) and the chip carrier ( 2 ) a predetermined minimum distance to be maintained is not fallen below. Halbleiterbauelement nach Anspruch 1, bei dem zwischen dem Halbleiterchip (1) und dem Chipträger (2) zumindest abschnittweise ein Isolationsmaterial (8a-8d) angeordnet ist.Semiconductor component according to Claim 1, in which, between the semiconductor chip ( 1 ) and the chip carrier ( 2 ) at least in sections an insulating material ( 8a-8d ) is arranged. Halbleiterbauelement nach Anspruch 2, bei dem das Isolationsmaterial (8a-8d) eine Vergussmasse (8) ist, die den wenigstens einen ersten Halbleiterchip (1) umschließt.Semiconductor component according to Claim 2, in which the insulating material ( 8a-8d ) a potting compound ( 8th ), which comprises the at least one first semiconductor chip ( 1 ) encloses. Halbleiterbauelement nach einem der vorhergehenden Ansprüche, bei dem ein Verhältnis zwischen einer maximalen Sperrspannung des Halbleiterbauelementes und der Dicke (d1, d2) der ersten (6a) bzw. zweiten (6b) Kontaktschicht in vertikaler Richtung über 50 V/μm beträgt.Semiconductor component according to one of the preceding claims, in which a ratio between a maximum reverse voltage of the semiconductor component and the thickness ( d1 . d2 ) the first ( 6a ) or second ( 6b ) Contact layer in the vertical direction is greater than 50 V / μm. Halbleiterbauelement nach einem der vorhergehenden Ansprüche, bei dem die erste (6a) und/oder die zweite (6b) Kontaktschicht einen Schmelzpunkt von über 260°C aufweisen.Semiconductor component according to one of the preceding claims, in which the first ( 6a ) and / or the second ( 6b ) Contact layer have a melting point of about 260 ° C. Halbleiterbauelement nach einem der vorhergehenden Ansprüche, bei dem die erste (6a) und/oder zweite Kontaktschicht (6b) mittels physikalischer oder chemischer Abscheidung aus der Gasphase, Sputtern oder mittels galvanischer bzw. stromloser Abscheidung hergestellt sind.Semiconductor component according to one of the preceding claims, in which the first ( 6a ) and / or second contact layer ( 6b ) are produced by physical or chemical deposition from the gas phase, sputtering or by means of galvanic or currentless deposition. Halbleiterbauelement nach einem der vorhergehenden Ansprüche, bei dem die erste (6a) und/oder zweite Kontaktschicht (6b) aus Kupfer, Aluminium, Gold, Silber, Zinn, Titan, Nickel oder einer Legierung zumindest eines dieser Metalle gebildet ist.Semiconductor component according to one of the preceding claims, in which the first ( 6a ) and / or second contact layer ( 6b ) is formed of copper, aluminum, gold, silver, tin, titanium, nickel or an alloy of at least one of these metals. Halbleiterbauelement nach einem der vorhergehenden Ansprüche, bei dem zwischen der ersten Kontaktschicht (6a) und dem ersten Chipträgerteil (2a) und/oder zwischen der zweiten Kontaktschicht (6b) und dem zweiten Chipträgerteil (2b) eine Lötverbindung (7a, 7b) ausgebildet ist.Semiconductor component according to one of the preceding claims, in which, between the first contact layer ( 6a ) and the first chip carrier part ( 2a ) and / or between the second contact layer ( 6b ) and the second chip carrier part ( 2 B ) a solder joint ( 7a . 7b ) is trained. Halbleiterbauelement nach einem der vorhergehenden Ansprüche, bei dem ein Leistungsbauelement in der den ersten Halbleiterchip (1) integriert ist und das eine Ansteuerschaltung für das Leistungsbauelement aufweist, die in einem zweiten Halbleiterchip (3) integriert ist.Semiconductor component according to one of the preceding claims, in which a power component in which the first semiconductor chip ( 1 ) is integrated and which has a drive circuit for the power device, which in a second semiconductor chip ( 3 ) is integrated. Halbleiterbauelement nach Anspruch 9, bei dem der zweite Halbleiterchip (3) auf einen der Chipträgerteile (2a, 2b) aufgebracht ist.Semiconductor component according to Claim 9, in which the second semiconductor chip ( 3 ) on one of the chip carrier parts ( 2a . 2 B ) is applied. Halbleiterbauelement nach Anspruch 9 oder 10, bei dem das Leistungsbauelement ein MOSFET, ein IGBT, ein Thyristor oder ein Bipolartransistor ist.A semiconductor device according to claim 9 or 10, wherein the power device is a MOSFET, an IGBT, a thyristor or a bipolar transistor. Halbleiterbauelement nach einem der Ansprüche 9 bis 11, bei dem ein Lastanschluss des Leistungsbauelements an den ersten Chipträgerteil (2a) und ein Steueranschluss an den zweiten Chipträgerteil (2b) angeschlossen ist.Semiconductor component according to one of Claims 9 to 11, in which a load connection of the power component to the first chip carrier part ( 2a ) and a control terminal to the second chip carrier part ( 2 B ) connected. Halbleiterbauelement nach Anspruch 12, bei dem der zweite Chipträgerteil (2b) an einen Anschluss des zweiten Halbleiterchips (3) angeschlossen ist.Semiconductor component according to Claim 12, in which the second chip carrier part ( 2 B ) to a terminal of the second semiconductor chip ( 3 ) connected. Halbleiterbauelement nach einem der vorhergehenden Ansprüche mit einem Gehäuse (8), wobei höchstens ein Chipträgerteil (4c) aus dem Gehäuse (8) herausgeführt ist.Semiconductor component according to one of the preceding claims, having a housing ( 8th ), wherein at most one chip carrier part ( 4c ) out of the housing ( 8th ) is led out.
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