DE102004020188B4 - Process to produce a digital output signal gives signal level above permitted voltage of output transistors and uses logic voltage level control between two values - Google Patents

Abstract

A process to produce a digital output signal comprises uses output transistors (1,4) with a signal level above the permitted connection voltage of the transistors which are controlled by upper and lower voltage levels. A logic level of the control voltage is bounded by a change in control voltage between the two voltage levels. - An INDEPENDENT CLAIM is also included for an arrangement for the above process.

Description

The The invention relates to a method and an associated arrangement for generating a digital output signal by means of output transistors, wherein the level of the output signal via the permissible Terminal voltage of the output transistors is located and the transistors controlled by a control voltage with an upper and a lower logic voltage level become.

From the US 5,559,464 A For example, an arrangement for generating a digital output signal is known in which transistors are connected to an internal operating voltage source so that no greater voltages than the maximum permissible terminal voltages occur at their terminals. However, the maximum possible voltage across the transistors is not achieved because the difference between the operating voltage and the internal voltage source is lower.

The means that the transistors are not driven through to the maximum. This has the disadvantage that to achieve the same drain current a transistor with a larger channel width must be used and that thereby a larger chip area for the transistor and its Control is required.

From the EP 0 780 983 B1 a method for generating a digital output signal by means of output transistors is known, wherein the level of the output signal is above the permissible terminal voltage of the output transistors and the transistors are driven by a control voltage having an upper and a lower logic voltage level, wherein a logic voltage level of the control voltage at a change in the logic voltage level of the control voltage is limited to a voltage between the two voltage levels.

Out WO 03/030 360 A2 is an arrangement for generating a digital Output signal known which by means of a "low-voltage" manufacturing technology is produced. The arrangement consists of a level matching circuit, which with a signal level between ground and a low Voltage level works. A corresponding one is issued Signal with a voltage level between a reference voltage and a high voltage level. The reference voltage level is one Tension, which is between half the low voltage level and the high voltage level. The arrangement further consists of an output unit, which with its input connected to the output of the level matching circuit is. The output unit generates an output voltage with a high voltage level when high voltage at the input of the output unit is present or a zero voltage level at the output if at the input the reference voltage is applied.

From the US 6,201,428 B1 an arrangement for generating an output signal from an input signal is known, wherein the output signal has a larger voltage swing. Consequently, it is possible to operate within a circuit, as before the arrangement itself with a low voltage, while the output signal is raised by the described arrangement to a higher voltage.

From the US 6,057,710 A an arrangement for generating an output signal is known, in which by means of low-voltage transistors, a higher voltage having, output voltage is generated by means of different reference voltages.

Out WO 98/28 848 A1 is an arrangement for generating an output signal for the generation a digital output signal with a higher voltage in a CMOS circuit known. The arrangement comprises a signal buffer, a signal level shifter, an output pull-up and an output pull-down arrangement. Of the Signal buffer is with a digital CMOS input for generation coupled to an output signal corresponding to the input signal, which to the output pull-down device and the signal level shifter is issued. The output pull-down arrangement gives a low voltage level if a logic "low" voltage level is present at the input of the signal buffer at a logic "high" voltage level at Input of the signal buffer via the signal level shifter and the output pull-up circuit Voltage level of 2.5 volts or more generated.

Of the Invention is therefore the object of a method and a associated Specify circuit arrangement, whereby a better control of the Output transistors when using one above the maximum allowable terminal voltage the output transistors lying operating voltage of the circuit possible is and thus a larger output current achieved and needed chip area can be minimized.

According to the invention, the object in a method for generating a digital output signal of the type mentioned is characterized solved that a respective charging or discharging a control voltage node, which is used to drive the output transistors is limited by the control voltage is measured and is interrupted upon reaching a reference voltage value of the charging or discharging and the control voltage with an exceed a maximum allowable Voltage is applied to the respective transistor preventing charge retention voltage.

The the output transistors have driving control voltages, conditional due to the digital nature of the arrangement, two voltage levels each by means of which the associated output transistor either locked or controlled. With an increase of the operating voltage, the output stage containing the output stage comes it also increases the Voltages between the terminals the output transistors, which only up to the maximum permissible terminal voltage limit without destruction of the components allowed is. According to the invention is a the two voltage levels of each driving the output transistors Control voltages limited so that the maximum allowable voltage between exceeded in each case the critical component connections in any case is, but where the respective output transistor to achieve a maximum output current is fully controlled.

According to the invention, it is provided that the control voltage when reaching a reference voltage with an additional voltage is applied between the two Voltage levels of the control voltage is.

In Another method feature is provided that the respective Charging or discharging process is limited by the fact that the control voltage is measured and upon reaching a reference voltage value of Charging or discharging process is interrupted and the control voltage with one passing a maximum allowable voltage applied to the respective transistor preventing charge retention voltage becomes.

through a voltage comparison of a reference voltage with a control voltage monitoring takes place the course of the control voltage at a transition from a logical State of tension in another. When reaching the modulation limit the control voltage in the direction of the maximum allowable voltage the output transistors become the process of voltage change canceled. At the same time, the connection of an additional voltage takes place to the control voltage, which between the two voltage levels of Control voltage is located and the control voltage thus limited on one side.

According to the invention The object is in an arrangement for generating a digital Output signal of the type mentioned solved in that a first input (FGP) having a gate terminal of a first transistor whose source terminal is connected to a first potential (VCC) is connected to a drain terminal of the first transistor with a first terminal of a first switch, a first one Connection of a voltage sensor, a first connection of a second Switch and a control voltage output (GP), which is used to control the output transistors is connected, that is a second Connection of the second switch with a second potential (VCC_1) connected to a second terminal of the first switch with a drain terminal of a second transistor is connected, whose Gate terminal with a data input and its source terminal with a second terminal of the voltage sensor and a ground potential (GND) is connected to a third terminal of the voltage sensor with a complementary one Data input, a fourth connection of the voltage sensor with the Data input and a fifth Connection of the voltage sensor with a reference potential (VCC_2) are connected.

one Arrangement for implementing the method according to the invention become the signals DATA, the negated signal DATAC, also according to the inventive method in a previous, not closer illustrated, generated signal FGP, two reference voltages (VCC_1, VCC_2) and an operating voltage supplied (VCC). A voltage sensor compares the control voltage to be generated at the output of the arrangement according to the invention, which is called hereinafter output GP, with the reference voltage VCC_2.

In the event that the control voltage at the output GP has high potential and should change to low potential, controlled by the signal DATA / DATAC, a discharge of the output GP must be done. This discharge takes place via the closed switch SW1 and the drain-source path of the transistor 4 against the GND potential. Upon reaching the equality of the voltages to be compared by the voltage sensor, the discharging operation is terminated by opening the switch SW1 and at the same time closing the switch SW2, setting the voltage of the output GP to the reference voltage VCC_1. The output GP is now at low potential.

For the opposite case, namely that Control voltage at the output GP has low potential and high-potential, controlled by the signals DATA / DATAC to change, the switch SW2 is opened, the switch SW1 remains open. The charging of the output GP takes place via the transistor 1 until reaching the modulation limit, which is determined by the operating voltage of VCC.

Consequently the course of the control voltage for this driving case of the first output transistor between the potentials VCC and VCC_1 move. For a second, complementary Output transistor, the control is also by a such arrangement according to the invention, wherein the course of the control voltage for this second output transistor between the potential GND and another reference voltage, which below the operating voltage, must move.

The Invention will be explained in more detail below with reference to five exemplary embodiments. In the associated Drawings shows

1 a basic circuit for implementing the method according to the invention,

2 a first embodiment,

3 a second embodiment,

4 a third embodiment,

5 a fourth embodiment and

6 a fifth embodiment.

The particular advantages of the invention are that the transistors are operated with the maximum possible terminal voltage be that that only the minimum necessary chip area for them and their control is needed and that the already existing internal power sources without additional Adjustments can be used.

The operation of the inventive solution is based on a in the 1 illustrated principle circuit will be explained. A p-type MOS transistor 1 , its source and bulk terminal with a voltage source VCC 2 are connected via a switch SW1 3 with an n-type MOS transistor 4 connected. Source and bulk terminal of the n-type MOS transistor 4 are GND to ground 5 connected. The node between transistor 1 and switch SW1 3 is with the control voltage output GP 6 connected. He is using a second switch SW2 7 and the voltage sensor 8th connected. Both switches SW1 3 and SW2 7 be from the voltage sensor 8th controlled. The signal DATA 9 and the complementary signal DATAC 10 a preceded, not shown, logic control the voltage sensor 8th and the transistor 4 , Switch SW2 7 connects the control voltage output GP 6 with the internal first voltage source VCC_1 11 , The p-type transistor 1 is from the digital signal FGP 13 controlled, that between the potential VCC 2 and a voltage on the order of VCC_1 11 replaced. voltage sensor 8th receives its operating voltage from the internal second voltage source VCC_2 12 ,

In the first state, the signal FGP 13 a potential of VCC_1 11 to have. The signal DATA 9 should be 0V and DATAC 10 a voltage the size of VCC_2 12 have. This is due to the voltage sensor 8th Switch SW1 3 closed and switch SW2 7 open. The control voltage output GP 6 thus has VCC potential.

The signal DATA 9 should now from 0 V to the VCC_2 potential 12 switch. Parallel to this signal DATAC changes 10 from the VCC_2 potential 12 after 0 V. Due to the positive voltage at the gate of transistor 4 the node GP is unloaded in the direction of mass. Parallel to the decreasing voltage at node GP 6 the voltage at the signal input FGP increases 13 to VCC potential and thus becomes the transistor 1 blocked.

The decreasing voltage at node GP 6 is from the sensor 8th evaluated. If it reaches a predetermined value Vref, then the sensor will 8th the switch SW1 3 opened and unloading aborted. At the same time by sensor 8th the switch SW2 7 closed and the node GP 6 with the internal voltage source VCC_1 11 connected. Thus, the signal GP changes 6 from VCC potential to VCC_1 potential 11 ,

In 2 For example, a first embodiment suitable for implementation in a circuit is shown. In this example, the first internal voltage source VCC_1 11 have a voltage of 1.8V and are referred to as VCC_1.8V. The second internal voltage source VCC_2 12 should here have a voltage of 3.3 V and carry the designation VCC_3.3V.

The connections for the control voltage output GP 6 correspond to those in 1 , The generation of the voltage for the input FGP 13 The same applies to elements whose name has been extended by the letter "a". For these elements, the control signals DATA and DATAC are reversed.

The sensor 8th consists in this embodiment of two gates. The first gate is made of the n-type transistor 14 and the p-type transistors 15 and 16 educated. The gates of the transistors 14 and 15 are connected to the signal DATAC. The gate of the transistor 16 is with the node GP 6 connected. This connection is used to query the voltage on the node GP. The output of the first gate 17 is to the input of the second gate, consisting of the n-type transistor 18 and the p-type transistor 19 , connected. The output of the second gate 20 controls the first switch SW1 3 , At the same time the output controls 17 the switch SW2 7 , The transistor 21 can be the node between the p-type transistors 22 to the internal power source VCC_1.8V. The gate of transistor 21 is with the signal input DATA 9 connected.

The switch SW1 3 consists only of an n-type transistor. Switch SW2 7 becomes of the n-type transistors connected in series 23 and 24 educated. The transistor 23 is from the voltage sensor 8th controlled. transistor 24 acts as potential separator. Its gate is therefore connected to the internal operating voltage source VCC_3.3V.

In the initial state, the input signal is DATA 9 at ground potential and the signal DATAC 10 has a high level of 3.3V. This is the transistor 4 blocked. transistor 21 connects the intermediate node 22 with the internal voltage source VCC_1.8V and precharges it to 1.8V. By the signal DATAC 10 is transistor 14 conductive and the node 17 discharged to ground potential. The low potential blocks the transistor 23 of the switch SW2 7 and interrupts the connection of the node GP 6 to the internal VCC_1.8V voltage source. The second gate from the transistors 18 and 19 inverts the potential of the node 17 too high and the n-channel transistor in SW1 becomes conductive.

On the left side of the circuit of the embodiment in 2 was discharged in the previous cycle of the signal nodes FGP. The voltage sensor 8a then has the switch SW1a 25 opened and the switch SW2a 26 closed. Thus, the signal node FGP 13 a low potential of 1.8V. transistor 1 is fully conductive and holds the control voltage output GP 6 on the 5V potential.

The in the embodiment used voltage source for generating the internal voltage of 1.8 V is only stabilized on one side of the voltage. She can do one Charge node to 1.8V but not a higher loaded node to 1.8 V discharged.

Now changes the signal DATA 9 from 0V to 3.3V and the signal DATAC 10 from 3.3V to 0V, so does the transistor 4 conductive and the transistor 27 blocked. The control voltage output GP 6 is then discharged to ground. If the voltage is below the value (3.3 V - Vthp), the transistor becomes 16 conductive and the node 17 charged to 3.3V. The exit 20 of the downstream inverter from the transistors 18 and 19 changes from high to low and thus opens switch SW1 3 , The discharge is thereby stopped. node 17 offset with its high potential the transistor 23 in the conductive state. Switch SW2 7 is thus closed and the control voltage output GP 6 connected to the internal voltage source VCC 1.8V.

transistor 28 whose gate is connected to the control voltage output GP 6 connected, pulls the node FGP 13 to 5 V. This is FGP for the node 13 the initial state restored.

The signal GP 6 becomes the data output stage 29 fed. It consists of the p-type series-connected transistors 30 and 31 , as well as the n-type series-connected transistors 32 and 33 , The signal GP 6 is to the gate of the transistor 30 connected. The gate of the transistor 31 is connected to the voltage source VCC_1.8V. This allows the intermediate node 34 be pulled to a potential lower than 1.8V. The drain of the transistor 31 is connected to the drain terminal of the n-type transistor 32 connected. This node represents the data output DATA_OUT 35 dar. The gate of the transistor 32 is connected to the voltage source VCC_3.3V. Thus, the node between the n-type transistors 32 and 33 assume no higher potential than 3.3V. The transistor 33 is driven by signal GN, which can take the voltage values 0 and 3.3V. In the same way, the voltage change of the signal FGP 13 respectively.

In 3 a second embodiment is shown. To ensure that the signal nodes FGP 13 and control voltage output GP 6 are not discharged to too low a potential, diodes are between the signal nodes FGP 13 or control voltage output GP 6 and the switches SW1 3 or SW1a 25 inserted. The with D 36 and since 37 labeled diodes can in turn be made up of different individual elements. In the embodiment shown here, two p-type transistors each are arranged in separate n-wells whose gate terminals are connected to the respective drain terminals.

Should the sensor 8th respectively. 8a do not interrupt the discharge path in time, the diodes D prevent 36 or Da 37 with their forward voltages that the signal node FGP 13 and control chip output GP 6 be discharged to the ground potential.

A third embodiment shows 4 , To secure the desired output state after the application of the operating voltage in addition to the circuit after 3 nor the n-type transistor 38 inserted. It has a relatively high resistance and connects the output node during the build-up of the operating voltages 39 of the sensor 8a with the ground potential. The starting node 40 of the following inverter switches to high and, together with the high of the DATAC signal 10 the discharge of the node FGP 13 over the device span transistor 27 , SW1a switch 25 and diode Da 37 one. transistor 38 is the signal PU 41 controlled, which provides a high potential for a predetermined time at the beginning of the voltage build-up (Power Up).

5 shows a fourth embodiment. A faster switching of the data output 35 can be achieved with larger data output transistors in the data output stage 29 when the p-type transistor 30 not the previously described control voltage signal GP 6 is supplied directly, but if it is generated via a separate stage of the same type. The signal is also inverted with it. Therefore, the drive signals DATA 9 and DATAC 10 it will be exchanged. The former control voltage signal GP 6 in this embodiment receives the new name NGP, such as "negated signal GP" and the signal FGP 13 the new name FNGP.

The newly introduced elements p-type transistor 42 , n-type transistor 43 , Voltage sensor 8b , the switches SW1b 44 and SW2b 45 and the diode Db 46 serve to charge or discharge the new control voltage output GP 6 ,

This circuit variant also has the advantage that the gates for the generation of the signals FNGP and NGP can be constructed with narrower transistors since they no longer have the gate of the output driver transistor 30 have to drive with its relatively large gate capacity, but only its precursor.

In a first state, the signal DATA 9 have a potential of 0 V and the complementary signal DATAC 10 3.3V. According to the previously described operation of the circuit, the signals FNGP were pulled to 5V and NGP to 1.8V.

The signal DATAC 10 pulls the knot 47 over the transistor 48 to mass. The exit 49 of the inverter from the transistors 50 and 51 is thereby charged to 3.3V, thus allowing the discharge of the control voltage output GP 6 in the following cycle. On the other hand, DATAC prefers 10 also the knot 17 to mass. This is currently the transistor 43 blocked. About the transistor 42 the signal NGP may be the control voltage output GP 6 pull to 5V potential. The transistor 30 is thus blocked.

To secure the initial state, as described above, the circuit part 52 of p-type transistors and the n-type transistor 53 integrated. Should the node FNGP in the direction of 1.8 V and the node NGP in the direction of 5 V tip over for any reason after switching on the operating voltage, the low potential of the node FNGP is reduced, reduced by the forward voltage of the diode Da 37 , the transistor 54 make conductive. The transistor 55 acts as potential separator and is always conductive at 1.8V at the gate. In the initial state DATA 9 Ground potential and the transistor 56 is also conductive. The knot 40 is pulled in this case to 3.3V and transistor 53 conducting the high at the inverter output 40 stabilized.

This high level will also switch SW1a 25 supplied, which initiates the discharge of the node NGP. If NGP is discharged far enough, node FNGP tilts to 5V in the manner previously described and the correct output state is established. The transistor 54 will be blocked. node 39 is pulled to 3.3V and the subsequent inverter can make its output 40 discharged to mass.

The signal DATA 9 will have two inverters 57 inverted twice and stands at the output of the second inverter as the signal DATA2 58 to disposal. As a result, the capacitive loading of the signals DATA 9 and DATAC 10 almost the same.

transistor 59 serves to stabilize the knot 39 , Changes the signal DATA 9 from a high level to the low level, so keeps transistor 59 with DATA2 at the gate the node 39 two more inverter delay times on earth.

6 shows a fifth embodiment. Across from 5 here was the diode 46 omitted. This is possible because switching off the discharge of the control voltage output GP 6 through the gates of the voltage sensor 8b sufficiently fast and a discharge of the control voltage output GP 6 is not possible until near the ground potential.

1

first Transistor, p-type

2

voltage source VCC

3

switch SW1

4

second Transistor, n-type

5

Dimensions GND

6

Control voltage output GP

7

switch SW2

8th

voltage sensor

9

signal DATA

10

signal DATAC

11

internal first voltage source VCC_1

12

internal second voltage source VCC_2

13

signal FGP

14

n-type transistor

15

P-type transistor

16

P-type transistor

17

first Gate output

18

n-type transistor

19

P-type transistor

20

second Gate output

21

transistor

22

node

23

n-type transistor

24

n-type transistor

25

switch SW1a

26

switch SW2a

27

transistor 4a

28

transistor 1a

29

Data output stage

30

P-type transistor

31

P-type transistor

32

n-type transistor

33

n-type transistor

34

between nodes

35

data output DATA_OUT

36

diode D

37

diode There

38

n-type transistor

39

output node

40

output node

41

signal PU

42

P-type transistor

43

n-type transistor

44

switch SW1b

45

switch SW2b

46

diode

47

node

48

transistor

49

output node

50

transistor

51

transistor

52

circuit part

53

transistor

54

transistor

55

transistor

56

transistor

57

two inverter

58

signal DATA2

59

transistor

Claims (2)

A method for generating a digital output signal by means of output transistors, wherein the level of the output signal is above the permissible terminal voltage of the output transistors and the transistors are driven by a control voltage having an upper and a lower logic voltage level, wherein a logic voltage level of the control voltage at a change of Logic voltage level of the control voltage is limited to a voltage between the two logic voltage levels, characterized in that a respective charging or discharging a control voltage node, which serves to drive the output transistors, is limited by the control voltage is measured and upon reaching a Reference voltage value of the charging or discharging process is interrupted and the control voltage is applied to a exceeding a maximum allowable voltage at the respective transistor preventing charging hold voltage. Arrangement for generating a digital output signal by means of output transistors, characterized in that a first input (FGP / 13 ) with a gate terminal of a first transistor ( 1 ), whose source terminal is connected to a first potential (VCC / 2), that a drain terminal of the first transistor ( 1 ) with a first terminal of a first switch ( 3 ), a first terminal of a voltage sensor ( 8th ), a first terminal of a second switch ( 7 ) and a control voltage output (GP / 6 ), which is used to drive the output transistors, is connected to a second terminal of the second switch ( 7 ) with a second potential (VCC_1 / 11 ), that a second terminal of the first switch ( 3 ) with a drain terminal of a second transistor ( 4 ) whose gate terminal is connected to a data input ( 9 ) and its source terminal to a second terminal of the voltage sensor ( 8th ) and a ground potential (GND / 5 ), that a third terminal of the voltage sensor ( 8th ) with a complementary data input ( 10 ), a fourth connection of the voltage sensor ( 8th ) with the data input ( 9 ) and a fifth connection of the voltage sensor ( 8th ) with a reference potential (VCC_2 / 12 ) are connected.