DE102004005938A1 - Speicherzelle mit Speicherschicht - Google Patents

Speicherzelle mit Speicherschicht Download PDF

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Publication number
DE102004005938A1
DE102004005938A1 DE102004005938A DE102004005938A DE102004005938A1 DE 102004005938 A1 DE102004005938 A1 DE 102004005938A1 DE 102004005938 A DE102004005938 A DE 102004005938A DE 102004005938 A DE102004005938 A DE 102004005938A DE 102004005938 A1 DE102004005938 A1 DE 102004005938A1
Authority
DE
Germany
Prior art keywords
channel region
layer
region
lateral edges
bounding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE102004005938A
Other languages
English (en)
Inventor
Jan-Malte Fischer
Jens-Uwe Sachse
Guenter Wein
Christoph Kleint
Joachim Deppe
Mathias Krause
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Priority to DE102004005938A priority Critical patent/DE102004005938A1/de
Publication of DE102004005938A1 publication Critical patent/DE102004005938A1/de
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Zur Verminderung des Effekts eines Corner-Devices wird eine zwischen dem Kanalbereich (4) und der Gate-Elektrode (6) vorhandene Speicherschichtfolge (109 an den vorzugsweise mit Verrundungen (8) versehenen seitlichen Rändern (7) des aktiven Bereiches (2) zu seitlich angeordneten Isolationsbereichen (3) hin dicker ausgebildet, wobei insbesondere eine vorzugsweise aus Oxid gebildete untere Begrenzungsschicht (11) außen eine größere Dicke (d2) aufweist als im mittleren Bereich (d1). Zusätzlich kann von dem aktiven Bereich (2) zu dem Isolationsbereich (3) hin eine Stufe (9) in dem dielektrischen Material vorhanden sein.
DE102004005938A 2004-02-06 2004-02-06 Speicherzelle mit Speicherschicht Ceased DE102004005938A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE102004005938A DE102004005938A1 (de) 2004-02-06 2004-02-06 Speicherzelle mit Speicherschicht

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE102004005938A DE102004005938A1 (de) 2004-02-06 2004-02-06 Speicherzelle mit Speicherschicht

Publications (1)

Publication Number Publication Date
DE102004005938A1 true DE102004005938A1 (de) 2005-04-21

Family

ID=34353581

Family Applications (1)

Application Number Title Priority Date Filing Date
DE102004005938A Ceased DE102004005938A1 (de) 2004-02-06 2004-02-06 Speicherzelle mit Speicherschicht

Country Status (1)

Country Link
DE (1) DE102004005938A1 (de)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5354703A (en) * 1991-06-28 1994-10-11 Texas Instruments Incorporated EEPROM cell array with tight erase distribution
US20020149081A1 (en) * 2001-02-06 2002-10-17 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5354703A (en) * 1991-06-28 1994-10-11 Texas Instruments Incorporated EEPROM cell array with tight erase distribution
US20020149081A1 (en) * 2001-02-06 2002-10-17 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ARITOME,S., et.al.: A 0.67 EmC Self-Aligned Shallow Trench Isolation Cell (SA-STI Cell) for 3V-only 256Mbit NAND EEPROMs. In: Electron DevicesMeeting, Technical Digest, Dec. 1994, S.61-64 *

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OP8 Request for examination as to paragraph 44 patent law
8131 Rejection