DE10138659B4 - Method for producing an arrangement comprising a semiconductor chip and a conductor track structure connected thereto - Google Patents
Method for producing an arrangement comprising a semiconductor chip and a conductor track structure connected thereto Download PDFInfo
- Publication number
- DE10138659B4 DE10138659B4 DE10138659A DE10138659A DE10138659B4 DE 10138659 B4 DE10138659 B4 DE 10138659B4 DE 10138659 A DE10138659 A DE 10138659A DE 10138659 A DE10138659 A DE 10138659A DE 10138659 B4 DE10138659 B4 DE 10138659B4
- Authority
- DE
- Germany
- Prior art keywords
- metal
- chip
- conductor track
- track structure
- carrier plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2208—Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems
- H01Q1/2225—Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems used in active tags, i.e. provided with its own power source or in passive tags, i.e. deriving power from RF signal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
- H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Verfahren
zur Herstellung einer Anordnung aus einem Halbleiterchip und einer
damit verbundenen Leiterbahnstruktur, bei dem
in einem ersten
Schritt unter Verwendung einer Maske (8) entweder eine Trägerplatte
(6) aus Metall durch Ätzen
einer Oberseite mit einer herzustellenden Leiterbahnstruktur (2) versehen
wird oder eine Trägerplatte
(6) aus Metall durch elektrolytische Abscheidung eines Metalles
mit einer herzustellenden Leiterbahnstruktur (2) versehen wird,
die so hergestellt wird, dass sie eine für ein elektronisches Etikett oder
eine kontaktlose Chipkarte geeignete Antennenstruktur umfasst,
in
einem zweiten Schritt ein Chip (1), der mit mindestens einem Anschlusskontakt
versehen ist, auf der Metallplatte oder Trägerplatte (6) befestigt wird
und zumindest der besagte Anschlusskontakt mit einer vorgesehenen
Kontaktfläche
der Leiterbahnstruktur elektrisch leitend verbunden wird,
in
einem dritten Schritt der Chip (1) in eine Abdeckung (5) eingeschlossen
wird und
in einem vierten Schritt die Trägerplatte (6) aus Metall derart
entfernt wird, dass vorhandene Anteile der Leiterbahnstruktur...Method for producing an arrangement comprising a semiconductor chip and a conductor track structure connected thereto, in which
in a first step using a mask (8) either a support plate (6) made of metal is provided by etching an upper side with a printed conductor structure (2) or a support plate (6) made of metal by electrolytic deposition of a metal with a printed conductor structure ( 2), which is manufactured to include an antenna structure suitable for an electronic tag or contactless chip card,
in a second step, a chip (1), which is provided with at least one connection contact, is fastened to the metal plate or carrier plate (6) and at least the said connection contact is electrically conductively connected to an intended contact surface of the conductor structure,
in a third step, the chip (1) is enclosed in a cover (5) and
in a fourth step, the support plate (6) is removed from metal so that existing portions of the conductor track structure ...
Description
Die vorliegende Erfindung betrifft ein Verfahren zur Herstellung einer Anordnung aus einem Halbleiterchip und einer damit verbundenen Leiterbahnstruktur, insbesonders einer Antennenstruktur auf einem Träger, wie sie insbesondere für elektronische Etiketten oder Chipkarten eingesetzt wird.The The present invention relates to a process for the preparation of a Arrangement comprising a semiconductor chip and a conductor track structure connected thereto, in particular an antenna structure on a support, as in particular for electronic Labels or smart cards is used.
Elektronische Tags (ID-Tags, RF-ID-Tags, das sind elektronische Etiketten mit in einem IC-Chip gespeicherter Information) oder Chipkarten für kontaktlose Übermittlung von Energie und Daten bilden eine Anordnung aus einem Halbleiterchip und einer Antennenstruktur auf einem Träger. Bisher werden derartige Anordnungen hergestellt, indem eine elektrisch leitende Antennenstruktur aus einer ganzflächigen Metallisierung ausgeätzt oder in der gewünschten Struktur aufgedruckt oder als Spulenwicklung aufgeklebt oder eingeschmolzen wird. Der Chip wird getrennt davon hergestellt, gehäust und nachträglich auf dem Träger der Antennenstruktur befestigt und mit der Antennenstruktur verbunden. Das geschieht mit einem der bekannten Verfahren durch Wire-Bonding oder Flip-Chip-Montage.electronic Tags (ID tags, RF ID tags, these are electronic labels with information stored in an IC chip) or chip cards for contactless transmission of energy and data form an array of a semiconductor chip and an antenna structure on a carrier. So far, such Arrangements made by an electrically conductive antenna structure from a whole-area Etched metallization or in the desired Structure printed or glued or fused as a coil winding becomes. The chip is made separately, housed and clad retrospectively the carrier attached to the antenna structure and connected to the antenna structure. This happens with one of the known methods by wire-bonding or flip-chip mounting.
In
der
In
der
Aufgabe der vorliegenden Erfindung ist es, ein vereinfachtes Verfahren zur Herstellung eines elektronischen Tags oder einer kontaktlosen Chipkarte anzugeben.task The present invention is a simplified method for Production of an electronic tag or a contactless chip card specify.
Diese Aufgabe wird mit dem Verfahren mit den Merkmalen des Anspruches 1 gelöst. Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.These Task is with the method with the features of the claim 1 solved. Embodiments emerge from the dependent claims.
Bei dem erfindungsgemäßen Verfahren wird eine Leiterbahnstruktur durch oberseitige Ätzung einer Metallplatte oder durch elektrolytische Abscheidung eines Metalles auf eine maskierte Oberseite einer Trägerplatte aus demselben Metall hergestellt. Ein Halbleiterchip wird auf der Leiterbahnstruktur befestigt. Anschlusskontakte des Halbleiterchips werden mit dafür vorgesehenen Kontaktflächen der Leiterbahnstruktur verbunden. Das kann mittels Bonddrähten geschehen oder durch Herstellung eines direkten Kontaktes nach Art einer Flip-Chip-Montage, bei der der Chip mit einer mit Schaltungselementen und Anschlusskontakten versehenen Oberseite nach unten auf die Kontaktflächen aufgesetzt und damit dauerhaft elektrisch leitend verbunden wird, z. B. durch Löten. Nach dem Einkapseln des Halbleiterchips in eine Abdeckung, z. B. Umspritzen mit einer Vergussmasse, wird die Metall- oder Trägerplatte von der von dem Chip abgewandten Rückseite her soweit entfernt, dass nur die somit funktionsfähige Leiterbahnstruktur an der Rückseite vorhanden ist. Die Leiterbahnstruktur umfasst bei den vorgesehenen Anwendungen die Antennenstruktur, die jetzt noch auf einen Träger, z. B. einen Chipkartenkörper, ein Papieretikett oder eine Folie aufgebracht oder darin einlaminiert werden kann.at the method according to the invention is a conductor track structure by top-side etching of a metal plate or by electrolytic deposition of a metal on a masked Top of a backing plate made of the same metal. A semiconductor chip will be on the Wired track structure attached. Connection contacts of the semiconductor chip be with for provided contact surfaces connected to the interconnect structure. This can be done by means of bonding wires or by making a direct contact in the manner of a flip-chip mounting, at the chip with one with circuit elements and connection contacts provided upper side down on the contact surfaces and thus permanently connected electrically conductive, z. B. by Soldering. After encapsulating the semiconductor chip in a cover, for. B. Encasing with a potting compound, the metal or carrier plate far away from the reverse side of the chip, that only the thus functional Conductor structure at the back is available. The interconnect structure includes the intended Applications the antenna structure, which is now still on a support, for. B. a chip card body, a paper label or a foil applied or laminated therein can be.
Es
folgt eine genauere Beschreibung von Beispielen des erfindungsgemäßen Verfahrens
anhand der beigefügte
Die
Die
Die
Die
Die
Die
Die
Bei
beiden vorgestellten Ausführungsformen kann
der Chip statt mit Bonddrähten
direkt mit seinen Anschlusskontakten auf Kontaktflächen der
Leiterbahnstruktur nach Art einer Flip-Chip-Montage angebracht werden.
Statt der Klebemasse
Die
Die
Claims (3)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10138659A DE10138659B4 (en) | 2001-08-07 | 2001-08-07 | Method for producing an arrangement comprising a semiconductor chip and a conductor track structure connected thereto |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10138659A DE10138659B4 (en) | 2001-08-07 | 2001-08-07 | Method for producing an arrangement comprising a semiconductor chip and a conductor track structure connected thereto |
Publications (2)
Publication Number | Publication Date |
---|---|
DE10138659A1 DE10138659A1 (en) | 2003-03-06 |
DE10138659B4 true DE10138659B4 (en) | 2006-04-06 |
Family
ID=7694612
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10138659A Expired - Fee Related DE10138659B4 (en) | 2001-08-07 | 2001-08-07 | Method for producing an arrangement comprising a semiconductor chip and a conductor track structure connected thereto |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE10138659B4 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005007643A1 (en) * | 2005-02-19 | 2006-08-31 | Assa Abloy Identification Technology Group Ab | Method and device for contacting semiconductor chips on a metallic substrate |
GB2466255B (en) | 2008-12-17 | 2013-05-22 | Antenova Ltd | Antennas conducive to semiconductor packaging technology and a process for their manufacture |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19840220A1 (en) * | 1998-09-03 | 2000-04-20 | Fraunhofer Ges Forschung | Transponder module and method for producing the same |
DE19639902C2 (en) * | 1996-06-17 | 2001-03-01 | Elke Zakel | Process for the production of contactless chip cards and contactless chip card |
-
2001
- 2001-08-07 DE DE10138659A patent/DE10138659B4/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19639902C2 (en) * | 1996-06-17 | 2001-03-01 | Elke Zakel | Process for the production of contactless chip cards and contactless chip card |
DE19840220A1 (en) * | 1998-09-03 | 2000-04-20 | Fraunhofer Ges Forschung | Transponder module and method for producing the same |
Also Published As
Publication number | Publication date |
---|---|
DE10138659A1 (en) | 2003-03-06 |
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Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8364 | No opposition during term of opposition | ||
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |