DE1012378B - Semiconductor arrangement with p-n transition - Google Patents

Semiconductor arrangement with p-n transition

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Publication number
DE1012378B
DE1012378B DES38554A DES0038554A DE1012378B DE 1012378 B DE1012378 B DE 1012378B DE S38554 A DES38554 A DE S38554A DE S0038554 A DES0038554 A DE S0038554A DE 1012378 B DE1012378 B DE 1012378B
Authority
DE
Germany
Prior art keywords
substance
junction
layer
arrangement
arrangement according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DES38554A
Other languages
German (de)
Inventor
Dr Walter Heywang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to NLAANVRAGE7906612,A priority Critical patent/NL189573B/en
Priority to NL269212D priority patent/NL269212A/xx
Priority to NL101504D priority patent/NL101504C/xx
Priority to NL269213D priority patent/NL269213A/xx
Priority to NL109229D priority patent/NL109229C/xx
Priority to NL107276D priority patent/NL107276C/xx
Priority to DES11109D priority patent/DE911529C/en
Priority to DES34551A priority patent/DE969465C/en
Priority to DES34714A priority patent/DE1115838B/en
Priority to DES34794A priority patent/DE977619C/en
Application filed by Siemens AG filed Critical Siemens AG
Priority to DES38554A priority patent/DE1012378B/en
Priority to FR1112727D priority patent/FR1112727A/en
Publication of DE1012378B publication Critical patent/DE1012378B/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/02—Details
    • H01J37/04—Arrangements of electrodes and associated parts for generating or controlling the discharge, e.g. electron-optical arrangement, ion-optical arrangement
    • H01J37/147—Arrangements for directing or deflecting the discharge along a desired path
    • H01J37/15—External mechanical adjustment of electron or ion optical components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • Analytical Chemistry (AREA)
  • Formation Of Insulating Films (AREA)

Description

DEUTSCHESGERMAN

Die bekannten Anordnungen mit p-n-Übergang oder mehreren p-n-Übergängen, z. B. Flächenrichtleiter, Flächentransistoren, z. B. mit p-n-p- oder n-p-n-Übergängen, oder auch Spitzentransistoren mit mindestens zwei auf die Oberfläche des Halbleiterkristalls aufgesetzten Emitter- und Kollektorelektroden haben den Nachteil, daß die Oberflächenisolation dieser Einrichtungen an den p-n-Übergängen mit der Zeit absinkt. Dies scheint daher zu rühren, daß sich allmählich die Oberfläche mit einer Feuchtigkeitsschicht überzieht. Diese Wirkung tritt auch dann ein, wenn der Halbleiterkörper in ein Schutzgehäuse eingebaut ist oder mit einer Isolationsschicht überzogen ist. Die Feuchtigkeit dringt auch durch kleinste Risse einer sonst gut elektrisch isolierenden und an sich feuchtigkeitsundurchlässigen Schutzschicht hindurch. Der Erfindung liegt die Erkenntnis zugrunde, daß das Ausbreiten einer Feuchtigkeitsschicht an den p-n-Übergängen besonders dadurch begünstigt wird, daß an diesen Stellen bei elektrischer Belastung der Anordnung hohe elektrische Felder auftreten, welche die Feuchtigkeit anziehen.The known arrangements with p-n junction or several p-n junctions, e.g. B. surface guide, Junction transistors, e.g. B. with p-n-p or n-p-n junctions, or even tip transistors with at least two emitter and collector electrodes placed on the surface of the semiconductor crystal have the Disadvantage is that the surface insulation of these devices at the p-n junctions decreases over time. This seems to be due to the fact that the surface gradually becomes coated with a layer of moisture. This effect also occurs when the semiconductor body is built into a protective housing or is covered with an insulating layer. The moisture penetrates even through the smallest cracks Well electrically insulating and inherently moisture-impermeable protective layer through. The invention is based on the knowledge that the spreading of a layer of moisture at the p-n junctions is particularly favored by the fact that the arrangement is under electrical load at these points high electric fields occur, which attract moisture.

Die Erfindung bezieht sich auf solche Halbleiteranordnungen mit p-n-Übergang, vorzugsweise Richtleiter oder Transistor.The invention relates to such semiconductor arrangements with p-n junction, preferably directional conductors or transistor.

Erfindungsgemäß wird der obige Nachteil bei solcher Halbleiteranordnung dadurch vermieden, daß seine Oberfläche mindestens an der Stelle bzw. an den Stellen, an der bzw. an denen sich ein p-n-Übergang befindet, vollständig mit einem Stoff einer hohen Dielektrizitätskonstante und/oder eines hohen Dipolmoments abgedeckt ist und außerdem von einem isolierenden und feuchtigkeitsundurchlässigen Schutzstoff umgeben und/oder in ein vakuumdicht geschlossenes Gefäß eingebaut ist. Durch solche Abdeckstoffe wird die Ausbreitung eines elektrischen Feldes vermindert. Statt dessen oder außerdem kann auch eine hochpermeable Substanz, z. B. Bariumtitanat od. dgl., an einer derartigen Stelle der Oberfläche einer Halbleiteranordnung angeordnet werden. Durch diese wird der elektrische Kraftfluß zwischen den beiden Seiten des p-n-Überganges gebündelt und die Feldstärke erniedrigt. Gemäß einer besonderen Ausbildung des Erfindungsgedankens wird eine solche Schicht während elektrischer Belastung der Halbleiteranordnung auf deren Oberfläche aufgetragen, damit sich die Teilchen der Schutzschicht in der Weise ausrichten können, daß die für das Auftreten der Feuchtigkeit schädliche Feldstärke möglichst stark reduziert wird. Unter Umständen kann die Halbleiteranordnung sogar während des Auftragens der Schicht überbelastet werden. Die Schicht besteht beispielsweise aus Wachs oder Lack oder einer polymerisierenden Substanz, in die permanente Dipole oder im elektrischen Feld sich Halbleiteranordnung mit p-n-ÜbergangAccording to the invention, the above disadvantage is avoided in such a semiconductor arrangement in that its surface at least at the point or points at which there is a p-n junction located completely with a substance of a high dielectric constant and / or a high dipole moment is covered and also by an insulating and moisture-proof protective material surrounded and / or installed in a vacuum-tight closed vessel. By such covering materials the spread of an electric field is reduced. Instead of this or in addition, a highly permeable substance, e.g. B. od barium titanate. Like. At such a point on the surface of a semiconductor device to be ordered. Through this the electrical power flow between the two sides of the p-n junction is bundled and the field strength is reduced. According to a special training of the Such a layer becomes an inventive concept during electrical loading of the semiconductor arrangement applied to their surface so that the particles of the protective layer align themselves in this way can that the harmful field strength for the occurrence of moisture is reduced as much as possible. Under certain circumstances, the semiconductor arrangement can even be overloaded during the application of the layer will. The layer consists for example of wax or lacquer or a polymerizing substance in the permanent dipoles or, in the electric field, a semiconductor arrangement with a p-n junction

Anmelder:
Siemens & Halske Aktiengesellschaft,Applicant:
Siemens & Halske Aktiengesellschaft,

Berlin und München,
München 2, Witteisbacherplatz 2Berlin and Munich,
Munich 2, Witteisbacherplatz 2

Dr. Walter Heywang, Karlsruhe,
ist als Erfinder genannt wordenDr. Walter Heywang, Karlsruhe,
has been named as the inventor

bildende Dipole eingelagert sind, welche durch das angelegte elektrische Feld polarisiert werden. Gegebenenfalls erfolgt das Aufbringen der Schicht und/ oder das Anlegen des Feldes unter erhöhter Temperatur. Zweckmäßigerweise wird die hochpermeable bzw. Dipolschicht durch eine weitere Schutzschicht bedeckt, welche gegebenenfalls in an sich bekannter Weise die gesamte Halbleiteroberfläche einhüllt. Das Ganze kann zur Sicherheit zusätzlich noch in ein hochevakuiertes, gegebenenfalls gegettertes und vakuumdicht geschlossenes Gehäuse gesetzt werden.forming dipoles are incorporated, which are polarized by the applied electric field. Possibly the application of the layer and / or the creation of the field takes place at elevated temperature. The highly permeable or dipole layer is expediently covered by a further protective layer covered, which optionally envelops the entire semiconductor surface in a manner known per se. That To be on the safe side, the whole thing can also be transferred to a highly evacuated, possibly gettered and vacuum-tight closed housing can be set.

In der Zeichnung ist eine Ausführungsform der Anordnung nach der Erfindung beispielsweise dargestellt, η und ρ bedeuten die beiden entgegengesetzt leitenden Zonen eines Germaniumrichtleiterkristalls. Wenn der Richtleiter in Sperrichtung belastet ist, herrscht unmittelbar an der Oberfläche an der Stelle des Überganges von der n- zur p-Zone eine sehr große Feldstärkendichte, welche dazu geeignet ist, Wassermoleküle anzuziehen und eine Wasserschicht an dieser Stelle zu erzeugen. Fig. 1 zeigt eine solche bekannte Anordnung mit gestreuten Kraftlinien 3. Erfindungsgemäß (Fig. 2) wird an dieser Stelle des Kristalls eine Schicht von in einer mindestens bei erhöhter Temperatur plastischen Masse 1 suspendiertem Bariumtitanatpulver 2 angeordnet, das sich in der in der Zeichnung angedeuteten Weise auf der Oberfläche anlagert und dessen permanente Polarisation sich parallel zu den Kraftlinen 3 ausrichtet. Die Bariumtitanatteilchen sind im Überschuß vorhanden, damit sie mindestens an der n-p-Oberfläche einen gut ■zusammenhängenden Film ergeben.In the drawing, an embodiment of the arrangement according to the invention is shown, for example, η and ρ denote the two oppositely conductive zones of a germanium directional conductor crystal. If the Directional conductor is loaded in the reverse direction, prevails directly on the surface at the point of transition from the n- to the p-zone a very high field strength density, which is suitable for water molecules to attract and create a layer of water at this point. Fig. 1 shows such a known one Arrangement with scattered lines of force 3. According to the invention (FIG. 2), at this point of the crystal a layer of suspended in a mass 1 which is plastic at least at an elevated temperature Barium titanate powder 2 arranged, which is in the manner indicated in the drawing on the surface and its permanent polarization is aligned parallel to the force lines 3. the Barium titanate particles are in excess to have good appearance at least on the n-p surface ■ result in a coherent film.

Hierdurch wird das elektrische Feld in die so entstandene Bariumtitanatschicht hineingezogen. Außerdem ist durch die hohe Dielektrizitätskonstante die Feldstärke als Ganzes erheblich verringert. Über der Bariumtitanat enthaltenden Schicht 1 ist außerdemAs a result, the electric field is drawn into the barium titanate layer created in this way. aside from that the field strength as a whole is considerably reduced due to the high dielectric constant. Above the Barium titanate containing layer 1 is also

709 588/202709 588/202

eine übliche elektrisch isolierende, feuchtigkeitsundurchlässige Schutzschicht 4, beispielsweise eine Lackschicht oder eine aufgedampfte Ouarzschicht, angeordnet. Während des Auftragens der Bariumtitanatschicht ist der Richtleiter in Sperrichtung stark ber lastet und das Ganze auf eine erhöhte Temperatur gebracht. a conventional electrically insulating, moisture-impermeable protective layer 4, for example a Lacquer layer or a vapor-deposited Ouarzschicht arranged. During the application of the barium titanate layer the directional guide is heavily overloaded in the reverse direction and the whole thing is brought to an elevated temperature.

Claims (6)

Patentansprüche:Patent claims: 1. Halbleiteranordnung mit p-n-Übergang, vorzugsweise Richtleiter oder Transistor, dadurch gekennzeichnet, daß seine Oberfläche mindestens an der Stelle bzw. an den Stellen, an der bzw. an denen sich ein p-n-Übergang befindet, vollständig mit einem Stoff einer hohen Dielektrizitätskonstanten und/oder einem hohen Dipolmoment abgedeckt ist und außerdem von einem isolierenden und feuchtigkeitsundurchlässigen Schutzstoff umgeben und/oder in ein vakuumdicht geschlossenes Gefäß eingebaut ist.1. Semiconductor arrangement with p-n junction, preferably Directional conductor or transistor, characterized in that its surface is at least at the point or points at which a p-n junction is located, completely covered with a substance with a high dielectric constant and / or a high dipole moment and is also surrounded by an insulating and moisture-proof protective material and / or is installed in a vacuum-tight closed vessel. 2. Anordnung nach Anspruch 1, dadurch gekennzeichnet, daß der Stoff ein Titanat, beispielsweise Bariumtitanat ist.2. Arrangement according to claim 1, characterized in that the substance is a titanate, for example Is barium titanate. 3. Anordnung nach Anspruch 1 oder 2, dadurch gekennzeichnet, daß der Stoff in Wachs, Lack oder eine polymerisierende Substanz eingebettet ist.3. Arrangement according to claim 1 or 2, characterized in that the substance in wax, lacquer or a polymerizing substance is embedded. 4. Verfahren zum Aufbringen der hochpermeablen Schicht nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß der Richtleiter während des Auftragens der Deckschicht in Sperrrichtung belastet, gegebenenfalls mindestens zeitweilig überlastet wird.4. A method for applying the highly permeable layer according to any one of claims 1 to 3, characterized in that the directional conductor during the application of the cover layer in the blocking direction loaded, possibly at least temporarily overloaded. 5. Verfahren zum Aufbringen der Deckschicht nach einem der Ansprüche 1 bis 3 oder nach An · Spruch 4, dadurch gekennzeichnet, daß das Aufbringen bei erhöhter Temperatur stattfindet.5. The method for applying the top layer according to one of claims 1 to 3 or according to an Claim 4, characterized in that the application takes place at an elevated temperature. 6. Anordnung nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, daß sie in einem evakuierten, gegebenenfalls gegetterten und vakuumdicht geschlossenen Gefäß angeordnet ist.6. Arrangement according to one of claims 1 to 4, characterized in that it is in an evacuated, optionally gettered and vacuum-tight closed vessel is arranged. In Betracht gezogene Druckschriften:
USA.-Patentschriften Nr. 2 669 692, 2 592 683.Considered publications:
U.S. Patent Nos. 2,669,692, 2,592,683. Hierzu 1 Blatt Zeichnungen1 sheet of drawings © 709 588/202 7.57© 709 588/202 7.57
DES38554A 1941-08-06 1954-04-05 Semiconductor arrangement with p-n transition Pending DE1012378B (en)

Priority Applications (12)

Application Number Priority Date Filing Date Title
NL107276D NL107276C (en) 1953-07-28
NL269212D NL269212A (en) 1953-07-28
NL101504D NL101504C (en) 1953-07-28
NL269213D NL269213A (en) 1953-07-28
NL109229D NL109229C (en) 1953-07-28
NLAANVRAGE7906612,A NL189573B (en) 1953-07-28 HINGE FOR A WINDOW WITH A FRAME MADE FROM STRING PROFILES.
DES11109D DE911529C (en) 1941-08-06 1941-08-06 Process for the production of stereo images with the aid of corpuscular beam devices
DES34551A DE969465C (en) 1953-07-28 1953-07-28 Semiconductor element with sharp p-n or p-n-p junctions
DES34714A DE1115838B (en) 1953-07-28 1953-08-07 Process for the oxidizing chemical treatment of semiconductor surfaces
DES34794A DE977619C (en) 1953-07-28 1953-08-13 Method for producing a protective layer on a semiconductor arrangement with at least one p-n junction
DES38554A DE1012378B (en) 1953-07-28 1954-04-05 Semiconductor arrangement with p-n transition
FR1112727D FR1112727A (en) 1953-07-28 1954-07-28 semiconductor element and method of manufacturing said element

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DES34551A DE969465C (en) 1953-07-28 1953-07-28 Semiconductor element with sharp p-n or p-n-p junctions
DES34714A DE1115838B (en) 1953-07-28 1953-08-07 Process for the oxidizing chemical treatment of semiconductor surfaces
DES34794A DE977619C (en) 1953-07-28 1953-08-13 Method for producing a protective layer on a semiconductor arrangement with at least one p-n junction
DES38554A DE1012378B (en) 1953-07-28 1954-04-05 Semiconductor arrangement with p-n transition

Publications (1)

Publication Number Publication Date
DE1012378B true DE1012378B (en) 1957-07-18

Family

ID=27437475

Family Applications (4)

Application Number Title Priority Date Filing Date
DES34551A Expired DE969465C (en) 1941-08-06 1953-07-28 Semiconductor element with sharp p-n or p-n-p junctions
DES34714A Pending DE1115838B (en) 1941-08-06 1953-08-07 Process for the oxidizing chemical treatment of semiconductor surfaces
DES34794A Expired DE977619C (en) 1941-08-06 1953-08-13 Method for producing a protective layer on a semiconductor arrangement with at least one p-n junction
DES38554A Pending DE1012378B (en) 1941-08-06 1954-04-05 Semiconductor arrangement with p-n transition

Family Applications Before (3)

Application Number Title Priority Date Filing Date
DES34551A Expired DE969465C (en) 1941-08-06 1953-07-28 Semiconductor element with sharp p-n or p-n-p junctions
DES34714A Pending DE1115838B (en) 1941-08-06 1953-08-07 Process for the oxidizing chemical treatment of semiconductor surfaces
DES34794A Expired DE977619C (en) 1941-08-06 1953-08-13 Method for producing a protective layer on a semiconductor arrangement with at least one p-n junction

Country Status (3)

Country Link
DE (4) DE969465C (en)
FR (1) FR1112727A (en)
NL (6) NL269213A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1244966B (en) * 1962-01-17 1967-07-20 Telefunken Patent Process for the production of surface-stabilized semiconductor components
DE1246886B (en) * 1960-07-30 1967-08-10 Elektronik M B H Process for stabilizing and improving the blocking properties of semiconductor components
DE1246888B (en) * 1960-11-24 1967-08-10 Semikron Gleichrichterbau Process for the production of rectifier arrangements for small currents

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE629065A (en) * 1960-08-30
NL282407A (en) * 1961-08-30
DE2413608C2 (en) * 1974-03-21 1982-09-02 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Method for manufacturing a semiconductor component
DE2700463A1 (en) * 1977-01-07 1978-07-13 Siemens Ag Semiconductor component edge passivating process - involves stacking of semiconductor components and passivating outer surface of stack

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2592683A (en) * 1949-03-31 1952-04-15 Bell Telephone Labor Inc Storage device utilizing semiconductor
US2669692A (en) * 1951-08-10 1954-02-16 Bell Telephone Labor Inc Method for determining electrical characteristics of semiconductive bodies

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE626305C (en) * 1928-03-10 1936-03-02 Siegmund Loewe Dr Multiple tubes
DE724888C (en) * 1936-05-30 1942-09-09 Siemens Ag Method of manufacturing selenium rectifiers
US2362545A (en) * 1942-01-29 1944-11-14 Bell Telephone Labor Inc Selenium rectifier and method of making it
US2469569A (en) * 1945-03-02 1949-05-10 Bell Telephone Labor Inc Point contact negative resistance devices
NL34436C (en) * 1945-04-20
NL129688C (en) * 1945-04-28
NL84057C (en) * 1948-02-26
US2524033A (en) * 1948-02-26 1950-10-03 Bell Telephone Labor Inc Three-electrode circuit element utilizing semiconductive materials
US2497770A (en) * 1948-12-29 1950-02-14 Bell Telephone Labor Inc Transistor-microphone
NL153395B (en) * 1949-02-10 Contraves Ag IMPROVEMENT OF BISTABLE TRACTOR SWITCH
CA478611A (en) * 1949-12-29 1951-11-13 Western Electric Company, Incorporated Etching processes and solutions
US2619414A (en) * 1950-05-25 1952-11-25 Bell Telephone Labor Inc Surface treatment of germanium circuit elements
BE507187A (en) * 1950-11-30
BE511009A (en) * 1951-04-28
GB1576783A (en) * 1977-11-07 1980-10-15 Teledyne Canada Control apparatus for a pneumaticallyoperated hopper feeder

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2592683A (en) * 1949-03-31 1952-04-15 Bell Telephone Labor Inc Storage device utilizing semiconductor
US2669692A (en) * 1951-08-10 1954-02-16 Bell Telephone Labor Inc Method for determining electrical characteristics of semiconductive bodies

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1246886B (en) * 1960-07-30 1967-08-10 Elektronik M B H Process for stabilizing and improving the blocking properties of semiconductor components
DE1246888B (en) * 1960-11-24 1967-08-10 Semikron Gleichrichterbau Process for the production of rectifier arrangements for small currents
DE1244966B (en) * 1962-01-17 1967-07-20 Telefunken Patent Process for the production of surface-stabilized semiconductor components

Also Published As

Publication number Publication date
NL189573B (en) 1900-01-01
NL269213A (en) 1900-01-01
DE969465C (en) 1958-06-04
NL107276C (en) 1900-01-01
NL101504C (en) 1900-01-01
DE977619C (en) 1967-08-31
NL269212A (en) 1900-01-01
FR1112727A (en) 1956-03-19
DE1115838B (en) 1961-10-26
NL109229C (en) 1900-01-01

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