DE10085273T1 - Verfahren und Einrichtung zum Konstruieren eines Vorab-eingeplante Befehle-Cache - Google Patents

Verfahren und Einrichtung zum Konstruieren eines Vorab-eingeplante Befehle-Cache

Info

Publication number
DE10085273T1
DE10085273T1 DE10085273T DE10085273T DE10085273T1 DE 10085273 T1 DE10085273 T1 DE 10085273T1 DE 10085273 T DE10085273 T DE 10085273T DE 10085273 T DE10085273 T DE 10085273T DE 10085273 T1 DE10085273 T1 DE 10085273T1
Authority
DE
Germany
Prior art keywords
constructing
instruction cache
scheduled instruction
scheduled
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10085273T
Other languages
English (en)
Other versions
DE10085273B4 (de
Inventor
Gad S Sheaffer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE10085273T1 publication Critical patent/DE10085273T1/de
Application granted granted Critical
Publication of DE10085273B4 publication Critical patent/DE10085273B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3808—Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Complex Calculations (AREA)
DE10085273T 1999-12-03 2000-10-09 Verfahren und Einrichtung zum Einplanen und Abfertigen von Befehlen in einer Prozessor-Pipeline Expired - Fee Related DE10085273B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/454,266 US6351802B1 (en) 1999-12-03 1999-12-03 Method and apparatus for constructing a pre-scheduled instruction cache
US09/454,266 1999-12-03
PCT/US2000/027887 WO2001040935A1 (en) 1999-12-03 2000-10-09 Method and apparatus for constructing a pre-scheduled instruction cache

Publications (2)

Publication Number Publication Date
DE10085273T1 true DE10085273T1 (de) 2003-10-09
DE10085273B4 DE10085273B4 (de) 2007-04-12

Family

ID=23803978

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10085273T Expired - Fee Related DE10085273B4 (de) 1999-12-03 2000-10-09 Verfahren und Einrichtung zum Einplanen und Abfertigen von Befehlen in einer Prozessor-Pipeline

Country Status (8)

Country Link
US (1) US6351802B1 (de)
KR (1) KR100483463B1 (de)
CN (1) CN1227584C (de)
AU (1) AU7875700A (de)
DE (1) DE10085273B4 (de)
GB (1) GB2374698B (de)
HK (1) HK1047485B (de)
WO (1) WO2001040935A1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6944750B1 (en) * 2000-03-31 2005-09-13 Intel Corporation Pre-steering register renamed instructions to execution unit associated locations in instruction cache
US6662293B1 (en) * 2000-05-23 2003-12-09 Sun Microsystems, Inc. Instruction dependency scoreboard with a hierarchical structure
US6687845B2 (en) * 2000-12-20 2004-02-03 Bull Hn Information Systems Inc. Fault vector pointer table
GB2393274B (en) 2002-09-20 2006-03-15 Advanced Risc Mach Ltd Data processing system having an external instruction set and an internal instruction set
US6965962B2 (en) * 2002-12-17 2005-11-15 Intel Corporation Method and system to overlap pointer load cache misses
US20050149680A1 (en) * 2003-12-30 2005-07-07 Intel Corporation Fast associativity collision array and cascaded priority select
US7181575B2 (en) * 2004-09-29 2007-02-20 Hewlett-Packard Development Company, L.P. Instruction cache using single-ported memories
US20070198812A1 (en) * 2005-09-27 2007-08-23 Ibm Corporation Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system
US7350056B2 (en) * 2005-09-27 2008-03-25 International Business Machines Corporation Method and apparatus for issuing instructions from an issue queue in an information handling system
US7454597B2 (en) * 2007-01-02 2008-11-18 International Business Machines Corporation Computer processing system employing an instruction schedule cache
US20090210664A1 (en) * 2008-02-15 2009-08-20 Luick David A System and Method for Issue Schema for a Cascaded Pipeline
US8069376B2 (en) * 2009-05-20 2011-11-29 Intel Corporation On-line testing for decode logic
KR101236562B1 (ko) 2010-01-08 2013-02-22 한국과학기술연구원 캐시 프로파일을 이용한 향상된 소프트웨어 파이프라인 스케줄링 방법
US10061746B2 (en) 2014-09-26 2018-08-28 Intel Corporation Instruction and logic for a vector format for processing computations
US11256511B2 (en) * 2019-05-20 2022-02-22 International Business Machines Corporation Instruction scheduling during execution in a processor
CN112602094A (zh) * 2020-03-11 2021-04-02 深圳市大疆创新科技有限公司 数据处理装置、数据处理方法以及加速器

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5021945A (en) * 1985-10-31 1991-06-04 Mcc Development, Ltd. Parallel processor system for processing natural concurrencies and method therefor
US5127093A (en) * 1989-01-17 1992-06-30 Cray Research Inc. Computer look-ahead instruction issue control
WO1991004536A1 (en) * 1989-09-20 1991-04-04 Dolphin Server Technology A/S Instruction cache architecture for parallel issuing of multiple instructions
US5295249A (en) * 1990-05-04 1994-03-15 International Business Machines Corporation Compounding preprocessor for cache for identifying multiple instructions which may be executed in parallel
EP0459232B1 (de) * 1990-05-29 1998-12-09 National Semiconductor Corporation Cache-Speicher von partiell decodierten Befehlen und Verfahren hierfür
DE69325785T2 (de) 1992-12-29 2000-02-17 Koninkl Philips Electronics Nv Verbesserte Architektur für Prozessor mit sehr langem Befehlswort
EP0652509B1 (de) * 1993-11-05 2000-05-10 Intergraph Corporation Befehlscachespeicher mit Kreuzschienenschalter
GB2293670A (en) 1994-08-31 1996-04-03 Hewlett Packard Co Instruction cache
US5742784A (en) * 1995-01-25 1998-04-21 International Business Machines Corporation System for reordering of instructions before placement into cache to reduce dispatch latency
JP3597540B2 (ja) * 1995-06-01 2004-12-08 富士通株式会社 並列データプロセッサにおけるアクティブ命令を回転させる方法および装置
US5923862A (en) 1997-01-28 1999-07-13 Samsung Electronics Co., Ltd. Processor that decodes a multi-cycle instruction into single-cycle micro-instructions and schedules execution of the micro-instructions
US5913049A (en) * 1997-07-31 1999-06-15 Texas Instruments Incorporated Multi-stream complex instruction set microprocessor
US6212623B1 (en) * 1998-08-24 2001-04-03 Advanced Micro Devices, Inc. Universal dependency vector/queue entry
DE69938621D1 (de) 1999-05-03 2008-06-12 St Microelectronics Sa Befehlausgabe in einem Rechner

Also Published As

Publication number Publication date
DE10085273B4 (de) 2007-04-12
AU7875700A (en) 2001-06-12
KR20020087392A (ko) 2002-11-22
GB0214664D0 (en) 2002-08-07
GB2374698A (en) 2002-10-23
CN1227584C (zh) 2005-11-16
HK1047485B (zh) 2004-09-10
WO2001040935A1 (en) 2001-06-07
GB2374698B (en) 2003-12-24
KR100483463B1 (ko) 2005-04-15
HK1047485A1 (en) 2003-02-21
US6351802B1 (en) 2002-02-26
CN1433538A (zh) 2003-07-30

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