DE10057489B4 - Integrated memory - Google Patents

Abstract

Integrated memory
- having a memory cell array (1), the row lines (WL1, WL2) for selecting memory cells (MC) and column lines (BL1, BL2) for reading or writing data signals of the memory cells,
- which is operable in a normal mode or in a test mode, wherein in the test mode, deactivating the row lines (WL1, WL2) in relation to a deactivation in the normal mode is performed slowed down,
- a controllable switching device (4) for connecting one of the column lines (BL1) to a connection for a deactivation potential (GND) for a deactivated state of the column lines,
- With a control circuit (3) having an output for outputting a deactivation control signal (EQL), which is connectable to the switching device (4) for triggering a switching operation of the switching device,
In which the control circuit (3) comprises a delay circuit (31, 33) which can be switched on by a selection signal (TM) and which, in the test mode in the switched-on state, delays the switching operation of the switching device (4) with respect to ...

Description

The The present invention relates to an integrated memory with a Memory cell array, the row lines for selecting memory cells and column lines for reading or writing data signals the memory cells, with a controllable switching device for connecting one of the column lines to a deactivation potential terminal for one deactivated state of the column lines.

Such integrated memory are for example from the US 6,038,183 or even from the EP 0 071 245 A2 known.

One integrated memory generally has one or more memory cell arrays each comprising column lines and row lines. The memory cells are in crossing points of the column lines and row lines arranged. Selection of the memory cells are selection transistors of respective memory cells through an activated row line turned on, thereby reading out or writing a Data signal of a selected Memory cell can be done. The selected memory cell is about the Selection transistor connected to one of the column lines, via the the respective data signal is read out or written becomes.

To a read or write access is made to the relevant column line disabled again by bringing it to a deactivation potential becomes. A corresponding circuit arrangement of the memory has to a controllable switching device through which the relevant Column line with a connection for the deactivation potential is connected. Likewise, after the memory access is the relevant Row line disabled again by pointing to a deactivation potential is brought, which blocks the selection transistors.

at some functional tests that have been made to check the functioning of the memory be deviated from a normal operation several row lines of the memory cell array simultaneously to save test time. The selection of such row lines can for example be made in this way be that activated row lines are not activated. Such an operation is also referred to as so-called multiple wordline select operation.

at the simultaneous deactivation of several active row lines add up the over the associated deactivation transistors flowing discharge currents to a relatively high total current that pollutes the grid, which is the deactivation potential leads. This network is mainly composed from the inactive row lines and one for reasons of space relative narrow and thus relatively high-impedance wiring in the row decoder. Due to the comparatively high resistance of this wiring forming metallization occurs during simultaneous deactivation the active row lines an ohmic voltage drop across said network on which loads the inactive row lines. There is a Voltage boost on the inactive row wires, in general proportional to the number of simultaneously active row lines and thus proportional to the desired time savings. The occurring Voltage boosting may result in a reduction in the affected row wirings blocking effect of the associated selection transistors of the memory cells cause, causing the information in the connected memory cells partially or completely deleted becomes.

Limited in multiple wordline select operation, the resulting discharge current Disabling the activated row lines, this is advantageous for the Hold time of the memory cells, which on the non-active row lines are connected because the voltage boost is reduced accordingly is. It can be a relatively large number akti ver row lines a memory cell array are disabled simultaneously. This can However, the situation occur that the relevant column lines be disabled at a memory access before the selection transistors of the Memory cells on the row lines to be deactivated completely closed are. This can lead to destruction the information to be read or stored during memory access to lead.

The The object of the present invention is an integrated memory specify the type mentioned, in which in a normal operation and in a multiple wordline select operation the store a reliable Reading, writing and holding cell information is possible.

The Task is solved by the subject matter of claim 1.

By the memory according to the invention, it is possible, for example, in the test mode of the integrated memory in the case of a multiple wordline select operation to control the deactivation of the relevant column lines such that the cell information is maintained even with comparatively slow deactivation of the row lines. A slow deactivation of the row lines is advantageous for the retention time of the memory cells. A test operation to be performed is displayed via the selection signal. The switchable by means of the selection signal delay circuit provides in that the deactivation of the respective column lines is appropriately delayed with respect to a deactivation time in a normal operation of the memory. The delay circuit is only in test mode in the on state, in normal operation it is operated in the non-on state.

In an advantageous embodiment According to the invention, the control circuit has a transistor on the deactivation control signal can be tapped off and its control terminal is connected to a terminal for a control signal connected is. The delay circuit contains Means for reducing an amplitude of the control signal in switched state of the delay circuit serve. This can be achieved that in the test mode of the transistor not fully turned on to generate the deactivation control signal what its current driving ability decreases. This will cause a switching edge of the deactivation control signal or, for example, a switching operation of a downstream inverter delayed.

To contains this purpose the delay circuit advantageously a connection for a supply potential, the with the connection for the control signal is connectable. The supply potential is dimensioned such that that the Transistor is placed in a limited conductive state.

Additionally or alternatively, the delay circuit Also included are the slope of the switching edge of the control signal decrease in the on state of the delay circuit. Due to a reduced steepness of the switching edge of the transistor triggering control signal is also a delay of the Switching edge of the deactivation control signal reached.

Especially Advantageously, the invention is applicable in the event that for deactivating the row lines a similar contrast Principle of action is applied. In such an embodiment are controllable connection devices for connecting the row lines to one terminal for another Deactivation potential, which is controlled by another control circuit become. This has an output for outputting a further deactivation control signal on, that's for triggering a switching operation of the terminal devices is used. each connecting device has a deactivation transistor whose main current path between the relevant row line and the connection for the further deactivation potential is switched. The control terminal of the deactivation transistor receives the further deactivation control signal. The further control circuit contains by a further selection signal switchable means for reducing serve an amplitude of the further deactivation control signal. additionally or alternatively, the control circuit may include means for Reduction of the slope of a switching edge of the further deactivation control signal. In this way, the resulting discharge current when deactivating in multiple wordline select mode be reduced and limited.

The Control of the deactivation process of the row lines is done with it after a similar one Principle of operation such as controlling the deactivation of the column lines. This makes it possible in particular that dependencies of technological fluctuations or voltage fluctuations the supply voltage can be compensated because such fluctuations are similar Effect on the behavior of the deactivation circuit Row lines and the behavior of the disabling circuit have the column lines. This makes it possible to delay the Deactivation of column lines precisely after the end of deactivation to set the row lines. This is also in test mode a comparatively high data throughput possible, since the delay is not unnecessary must be chosen large.

there It is also advantageous to design the layout of the two circuit parts as similar as possible. In particular, local fluctuations can be optimally compensated when the two circuit parts in the layout are close to each other and use the same supply and drive signals. Accordingly, the Selection signals of the two circuit parts correspond to each other. It is likewise advantageous for the control circuit and the further control circuit to apply to a common supply voltage.

Further advantageous embodiments and further developments are specified in subclaims.

The Invention will be described below with reference to the drawing Figures, the embodiments represent the invention, closer explained. Show it

1 a memory cell array of a memory with row lines and column lines,

2 a potential profile of a row line and a column line in a read operation,

3 an embodiment of a control circuit of the integrated memory,

4 an embodiment of another control circuit for deactivating Zeilenleitun gene.

In 1 is a memory cell array 1 of an integrated memory having row lines in the form of word lines WL1 and WL2 and column lines in the form of bit lines BL1 and BL2. At intersections of the word lines WL1, WL2 and the bit lines BL1, BL2, the memory cells MC1 and MC2 are arranged. These are selected via a respective word line for a read or write operation. For this purpose, the word lines are each connected to an activation potential, so that the connected selection transistors are turned on. A data signal is read from the memory cells or written into one of the memory cells via the bit lines. The bit lines BL1, BL2 are connected via a sense amplifier 4 selected for this purpose. After the read or write operation, the bit lines BL1, BL2 are deactivated, that is, brought to a deactivation potential GND. This process is also referred to as "equalizing". The deactivation process is controlled by a deactivation control signal EQL. The sense amplifier 4 includes controllable switching means by which the bit lines BL1, BL2 are connected to a corresponding terminal for the deactivation potential GND.

In 2 a potential profile (VWL1, VBL1) of the word line WL1 and the bit line BL1 is shown in a read operation. To activate the word line WL1, this is connected to an activation potential which has a positive value relative to a reference potential (H level, eg 2.0 V) and defines a logic value "1". Accordingly, in the deactivated state, the word line WL1 has a deactivation potential which, for example, corresponds to the reference potential or to a negative potential in opposition thereto (L level, eg 0 V or -0.3 V) and defines the logic value "0".

At the beginning of the read operation, the word line WL1 is activated, whereby a data signal of the memory cell MC1 reaches the bit line BL1 (time t0). At time t1, the sense amplifier becomes 4 is activated, whereby the bit line BL1 is raised to the H level due to the data signal. During normal operation of the memory, the word line WL1 is deactivated according to the dashed curve. During test operation of the memory, the word line WL1 is deactivated correspondingly more slowly for a multiple wordline select operation. In order to avoid data loss in this case, the Deacti vation of the bit line BL1 compared to a normal operation (dashed curve) is delayed accordingly.

In 3 an embodiment of a control circuit of an integrated memory according to the invention is shown. The circuit shown serves to generate the deactivation control signal EQL for supply to the sense amplifier 4 according to 1 , The control circuit 3 is used to output the deactivation control signal EQL. The input signals used are a test mode signal TM, which indicates a test operation of the memory, and a selection signal BSEL, which in particular indicates an end of a read operation.

The control circuit 3 contains two alternatively switchable current branches 31 and 32 , The current branch 32 is switched on, for example, in a normal operation of the memory, the test mode signal TM in this case has the L level. As a result, the transistor P5 is conductive, the transistor P3 of the current branch 31 in the locked state. At the end of a read access, the signal BSEL changes from H level to L level. As a result, the transistor P4 is activated, the transistor N1 is deactivated. Accordingly lies at the entrance of the inverter 33 a potential which substantially corresponds to the supply voltage V1. This has a positive value and is dimensioned such that the transistor N2 of the inverter 33 is driven into saturation due to the potential of its control signal S. The transistor N2 is therefore fully turned on. About another inverter 34 the deactivation control signal EQL can be tapped by the transistor N2.

During test operation of the memory, the test mode signal TM has the H level. Accordingly, the transistor P3 is conductive, the transistor P5 in a blocking state. At the end of a memory access, the signal BSEL falls again from the H level to the L level. Accordingly, the transistor P2 is turned on. The current branch 31 is therefore in an on state. The control signal S at the input of Inver age 33 has correspondingly a potential or an end amplitude, which results from the supply voltage VH less the forward voltages of the transistors P1-P3 and is reduced compared to the normal operation. The supply voltage VH is dimensioned such that the transistor N2 is operated due to the potential of the control signal S in a limited conductive state. The supply voltage VH is, for example, 1.6 V with respect to a supply voltage V1 of, for example, 2.0 V. The amplitude of the control signal S can additionally be adjusted by targeted adjustment of the transistor P1, which is connected as a diode. This has a constant voltage drop in the amount of its threshold voltage (for example, 0.6 V), whereby the potential of the control signal S remains much lower than in normal operation (supply voltage V1 minus the forward voltages of the transistors P4 and P5).

The transistor N2 thus does not reach its full conductivity and consequently drives a clot lower power than in normal operation. As a result, the switching operation of the subsequent inverter 34 delayed, so that a delay of the signal EQL is achieved compared to a normal operation. The delay can be in the interplay of the current branch 31 and the inverter 33 and 34 be adjusted in a suitable manner, which accordingly act together as a delay circuit. This is switched on or off by the test mode signal TM.

A delay can also be achieved by reducing the slew rate of the control signal S. In a suitable measure to the transistors P2 and P3 are designed so that the current branch 31 in the on state has a significant on-resistance (higher than the on-resistance of transistors P4 and P5). The higher this resistance, the flatter the rising edge of the control signal S. The significant on-resistance is preferably provided by a relatively small dimensioning tion of the transistors P2 and P3 (compared to the dimensioning of the transistors P4 and P5).

In 4 a circuit part of the memory is shown with a further control circuit, which serves for the corresponding deactivation of word lines of the memory cell array. The 4 shows right part of the edge of the memory cell array 1 in which individual word lines WL are arranged. Each word line WL can be driven to an activation potential via a respective word line transistor T1, hereinafter referred to as activation transistor. In the case described here, this potential is the H level, so that the selection transistors, which are connected to the word lines, are turned on. To select the word lines WL, a word line selection signal / WAS is applied. The H level is supplied to the transistors T1 via a common drive line TL.

Furthermore, each word line WL is connected via a second word line transistor T2, hereinafter referred to as deactivation transistor, to a supply line DL, which is connected to a source of a deactivation potential LL. This potential is preferably a level which is even lower or more negative than the L level (eg -0.3 V), around the selection transistors of the memory cell array connected to the word lines 1 to lock with security.

to Activation of word lines WL brings an address decoder the Word line drive signal WTS to the H level and controls the word line selection signal / WHAT to the L level. Thus, the associated activation transistors T1 switch through, and the word lines in question are driven to the H level. Before activation and after the activation is completed, the Signal WTS held low.

To deactivate the word lines WL is a control circuit 2 intended. This has an output line AL, which is connected to the control terminals of all deactivation transistors T2. The output line AL supplies a deactivation control signal DSS for the modulation of these transistors. A first input line EW is connected to receive the word line driver signal WTS, a second input line EM is connected to receive a test mode signal MES. A third input line ED is connected to receive a deactivation command signal / DBS.

The control circuit 2 is switchable between two modes, for example, between the normal operation and the test operation of the memory. For switching purposes, the test mode signal MES is used, which has the L level for normal operation and the H level for test mode. The level converter 20 and 30 are equal to each other and constructed in a manner known per se to provide H level at their output when their signal input has the binary value "1" and to provide LL level (derived from the potential LL) when their signal input is the binary value Has "0".

In normal operation, the control circuit operates 2 in the usual way, when receiving a word line deactivation command on the input line ED, the output line AL is abruptly brought to an H level, thereby saturating the deactivation transistors T2 with a steep rising edge. As a result, the connected word lines WL are discharged as quickly as possible via the supply line DL to the LL level. In normal operation only a single word line WL is activated in this case and then deactivated by means of the transistors T2. For this purpose, the test mode signal MES is kept at the L level.

Of the Test mode is set so that for the test of the memory of the Multiple Wordline Select operation is used, with each one several word lines WL through L level of the signal / WAS at several Transistors T1 have been activated and deactivated together should be. For this purpose, the test mode signal MES is set to "1". Upon termination of word line activation the signal WTS received at the input line EW becomes L level connected. As a result, the transistor T4 is conditioned to passage.

Before the deactivation command appears, the signal / DBS at the command input ED is still at "1", so that the level converter 20 the H-Pe gel coupled to the gate electrode of the transistor T6. The transistor T6 is thus conductive and keeps the output line AL still at LL level, so that the word line deactivation transistors T2 are still kept locked. The transistor T5 remains in the test mode of the control circuit permanently non-conductive, because its gate electrode H level ("1") from the output of an OR gate 10 receives as it receives the "1" from the input line MES at one of its two inputs during the test mode. Transistor T7 is turned on by the output of the level converter during the duration of the test mode 30 is turned on, which is now at LL level, because at the input of this level converter a "0" appears (inverted "1" of the test mode signal MES by inverter 40 ). The transistor T8 remains at the H level from the output of the level converter 20 for now still locked.

Now, when the deactivation command is applied by changing the signal / DBS from "1" to "0", the level converter converts 20 this "0" in LL level at its output, so that the NFET T6 blocks, whereby the LL potential is separated from the output line AL. The LL potential of the output of the level converter 20 now switches on the P-FET T8, so that via this transistor T8, the likewise conductive P-FET T7 and the "diode" T9, a conductive connection between the output line AL and the HL potential is established. As a result, the deactivation transistors T2 connected to the output line AL are put into a conducting state in order to discharge the assigned word lines WL to the deactivation potential LL.

The Transistors T7, T8, T9 and the potential HL are dimensioned that this deactivation control signal generated in response to the deactivation command DSS on line AL has a different characteristic than in normal mode, around the discharge currents in the opened deactivation transistors T2. A current limit results when the end amplitude of the signal DSS is kept below the level which is for full switching the deactivation transistors T2 leads. This is achieved by Using the potential HL, which is less positive than the H level is (e.g., +1.6 volts) and through the diode-connected P-FET T9, at which an additional constant Voltage drop in height the threshold voltage Vth of P-FET T9 occurs (e.g., about 0.6 volts). Thus, the deactivation control signal DSS to a level HL-Vth raised, which remains much lower than that in normal operation via the transistors T4 and T5 reached H level. The deactivation transistors T2 reach so not their full conductivity and thus drive less power than in normal mode. Also the inactive remained copies of the word lines are thus high impedance connected to the supply system DL. The ratio of effective channel resistances the deactivation transistors T2 to the resistance of the supply system DL is increased in this way, so that on the inactive word lines no harmful voltage increases due the discharge currents arising from the active word lines.

A Current limitation can also be achieved by reducing the edge steepness of deactivation control signal DSS. With steep rising edge this signal has the over the deactivation transistors T2 flowing discharge currents from the active word lines WL at the beginning of discharge a high peak, which contributes a lot to the unwanted voltage increases on the inactive word lines. In a particular embodiment The invention is therefore a measure for Reduction of said edge steepness hit.

In the illustrated control circuit 2 this measure consists in designing the circuit branch comprising the series connection of the FETs T7 and T8 so that, when switched on, it has a marked on-resistance (higher than the on-resistance of the P-FETs T4 and T5). The higher this resistance, the flatter the rising edge of the deactivation control signal DSS, because of the increased RC time constant with the gate-ground capacitances of the deactivation transistors T2. The significant on-resistance is preferably provided by a relatively small size of the P-FETs T7 and T8 (compared to the dimensioning of the P-FETs T4 and T5).

In In the drawing, P-FETs T7 and TB are reduced-pass transistors Threshold voltage shown. The use of such elements may be advantageous in the sense of the desired properties of the relevant circuit be. It can but also transistors without reduced threshold voltage used become. In the same sense, it may be advantageous to the substrate connections of Transistors T7, T8, T9 to the potential HL, as shown.

The diode-connected P-FET T9 can also be replaced by a real diode; it can also be omitted without substitution if the potential HL alone is already low enough to achieve the desired reduction in the end amplitude of the signal DSS. Also, instead of the potential HL, it is possible to apply the full H level to the end of the relevant current branch if the threshold voltage of the diode-connected P-FET T9 (or a diode located there) satisfies only the level reduction; if desired, a plurality of diode-connected transistors (or multiple diodes) may be connected in series. Of the appreciable resistance of said current branch to reduce the slope of the signal DSS can also be achieved by inserting an additional ohmic element, or in that at least one of the transistors T7 and T8 is limited to controlled, such as by reducing the level converter 30 delivered switch-on level. It may also be sufficient to reduce either only the end amplitude or only the edge steepness of the deactivation control signal DSS. The foregoing is also analogously applicable to the control circuit 3 according to 3 ,

specification is general when several active word lines are deactivated each of the individual word lines flowing individual streams in each case so far to limit that Sum of these currents below remains a critical value. The measure of the current limit to be established depends on it It depends on how many active word lines you disable at the same time wishes and how high the critical value is. The latter is mainly determined by the design impedance of the deactivation potential lead system. These specifications form the boundary conditions for setting the current limit and thus for the dimensioning of the components and levels in the reduction device according to the invention used for current limitation.

Due to the similarity of the circuit parts 3 to disable the bitlines and off 4 for deactivating the word lines or by the similarity of their control circuits 3 respectively 2 Deactivation of the word lines and the bit lines is well tuned to each other. In both control circuits also a reduced potential VH or HL is used. As a result, each subsequent switching transistors are driven weaker, so that their Stromtreibefähigkeit is reduced. The bit lines are therefore similarly delayed connected to the corresponding deactivation potential as the word lines. By a similar circuit design dependencies of technological fluctuations and dependencies of voltage fluctuations of the supply voltage can be compensated because such fluctuations exert similar effects on both circuit parts. This effect can be amplified if both circuit parts in the layout are close to each other and use the same supply and control signals. In this case, the test mode signal corresponds to MES off 4 and the test mode signal TM 3 each other. It is also advantageous if both control circuits 2 and 3 abut against a common supply voltage, that is, the potentials of the supply voltages V1 and VH 3 correspond to the H potential or HL potential 4 ,

1

Memory cell array

2

control circuit

3

control circuit

4

sense amplifier

10

OR gate

20 30

level converter

31 32

current branch

33 34, 35, 36

inverter

40

inverter

BL1, BL2

bit

WL WL1, WL2

wordline

MC1, MC2

memory cell

EQL

Deactivation control signal

S

control signal

V1

supply voltage

GND

deactivation potential

VH

supply voltage

T1 to T9

transistor

P1 to P6

transistor

N1, N2

transistor

BSEL

select signal

TM

Test mode signal

H, HL, L, LL

potential

VWL1, VBL1

potential curve

AL

output line

DL

supply

ED

input line

EM

input line

EW

input line

TL

drive line

MES

Test mode signal

/ DBS

Deactivation command signal

/WHAT

Word line selection signal

WTS

Word line drive signal

DSS

Deactivation control signal

Claims (9)

Integrated memory - with a memory cell array ( 1 ) having row lines (WL1, WL2) for selecting memory cells (MC) and column lines (BL1, BL2) for reading or writing data signals of the memory cells, operable in a normal mode or in a test mode, wherein in the test mode Deactivating the row lines (WL1, WL2) in relation to a deactivation in the normal mode slowed down, - with a controllable switching device ( 4 ) for connecting one of the column lines (BL1) to a deactivation potential (GND) terminal for a deactivated state of the column lines, - to a control circuit (BL1) 3 ) with an output for outputting a deactivation control signal (EQL) associated with the switching device ( 4 ) is connectable for triggering a switching operation of the switching device, - in which the control circuit ( 3 ) a switchable by a selection signal (TM) delay circuit ( 31 . 33 ) in which, in the test mode in the switched-on state, the switching operation of the switching device ( 4 ) is delayed with respect to a switching operation of the switching device ( 4 ) in the non-activated state of the delay circuit. Integrated memory according to Claim 1, characterized in that - the control circuit ( 3 ) includes a transistor (N2) at which the deactivation control signal (EQL) is tapped and whose control terminal is connected to a terminal for a control signal (S), - the delay circuit comprises means (VH, P1) for reducing an amplitude of the control signal (S) in the on state of the delay circuit. Integrated memory according to Claim 2, characterized in that the delay circuit ( 31 . 33 ) includes a terminal for a supply potential (VH), which is connectable to the terminal for the control signal (S), wherein the Versorgungspo potential (VH) is such that the transistor (N2) is placed in a limited conductive state. Integrated memory according to one of Claims 1 to 3, characterized in that - the control circuit ( 3 ) includes a transistor (N2) at which the deactivation control signal (EQL) is tapped and whose control terminal is connected to a terminal for a control signal (S), - the delay circuit comprises means (P2, P3) for reducing a slope of a switching edge the control signal (S) in the on state of the delay circuit. Integrated memory according to one of Claims 2 to 4, characterized in that - the control circuit ( 3 ) for generating the deactivation control signal, two alternatively switchable current branches ( 31 . 32 ), - a first branch ( 32 ) is acted upon in its switched-on state, the control terminal of the transistor (N2) with a first potential (V1) driving the transistor into saturation, - a second current branch ( 31 ) is in its on state, the control terminal of the transistor (N2) biased to the transistor forward biasing second potential (VH, P1) and means (VH, P1) for reducing an amplitude of the control signal (S) and / or means (P2, P3) for reducing a slope of a switching edge of the control signal (S). Integrated memory according to Claim 5, characterized in that in the second current branch ( 31 ) is inserted as a diode acting element (P1). Integrated memory according to one of Claims 1 to 6, characterized in that - controllable connection devices (T2) for connecting the row lines (WL) to a connection (DL) for a further deactivation potential for a deactivated state of the row lines are included, - a further control circuit ( 2 ) is provided with an output for outputting a further deactivation control signal (DSS) which is connectable to the connection means (T2) for triggering a switching operation of the connection means, - each connection means comprises a deactivation transistor (T2) whose main current path is between one of the row lines ( WL) and the terminal (DL) is connected for the further deactivation potential and whose control terminal receives the further deactivation control signal (DSS), - the further control circuit ( 2 ) by means of a further selection signal (MES) switchable means (T9, HL) for reducing an amplitude of the further deactivation control signal (DSS). Integrated memory according to one of Claims 1 to 7, characterized in that - controllable connection devices (T2) for connecting the row lines (WL) to a connection (DL) for a further deactivation potential for a deactivated state of the row lines are included, - a further control circuit ( 2 ) is provided with an output for outputting a further deactivation control signal (DSS) which is connectable to the connection devices (T2) for triggering a switching operation of the connection devices, - each connection device has a deactivation transistor (T2) whose main current path is between one of the row lines ( WL) and the terminal (DL) is connected for the further deactivation potential and whose Steueran circuit receives the further deactivation control signal (DSS), - the further control circuit ( 2 ) by means of a further selection signal (MES) switchable means (T7, T8) for reducing a slope of a switching edge of the further deactivation control signal (DSS). Integrated memory according to Claim 7 or 8, characterized in that the further selection signal (MES) corresponds to the selection signal (TM) and the control circuit ( 3 ) and the other control scarf tion ( 2 ) abut against a common supply voltage (V1, H; VH, HL).