DE10057489A1 - Integrated memory has memory cell field and control circuit connected to deactivation switch with delay stage activated by selection signal for delaying switching process - Google Patents

Abstract

The memory has a memory cell field with row lines for selecting memory cells and column lines for reading or writing data signals to/from cells, a controllable switch for controlling one of the column lines to a connection for a deactivation potential and a control circuit (3) connected to the switch and with a delay stage (31,33) activated by a selection signal (TM) for delaying the switching process.

Description

The present invention relates to an integrated memory cher with a memory cell array, the row lines to Selection of memory cells and column lines for reading out or writing data signals from the memory cells, with a controllable switching device for connecting a the column lines with a connection for a deactivation potential for a deactivated state of the columns cables.

An integrated memory generally has one or more rere memory cell fields, each column lines and row lines. The memory cells are included at intersections of column lines and row lines arranged. Selection will be used to select the memory cells transistors of respective memory cells by an act fourth row line switched on, which subsequently reading out or writing a data signal selected memory cell can take place. The selected food For this purpose, the cell is connected to one of the selection transistors Column lines connected via which the respective data si gnal read or registered.

After a read or write access, the be hitting column line again by clicking on a deactivation potential is brought. A corresponding For this purpose, the circuit arrangement of the memory has a controllable one Switching device through which the relevant column line device with a connection for the deactivation potential is bound. Likewise, after the memory has been accessed, the concerned row line deactivated again by clicking on a deactivation potential is brought, which the Aus select transistors blocked.  

For some function tests that are used to test the function of the Memory made will be different from one Normal operation of several row lines of the memory cell array activated at the same time to save test time. The out Such row lines can be selected, for example be made that the activated row lines are not activated row lines are adjacent. Such a Be drive is also known as a multiple wordline select Operation designated.

When several active lines are deactivated at the same time lines add up via the assigned deactivation discharge transistors flowing to a relative high total current, which loads the network, which the Deakti potential leads. This network mainly settles together from the inactive row lines and one For reasons of space, they are relatively narrow and therefore relatively high-impedance Wiring in the row decoder. As a result of the comparatively ho hen resistance of the metallization forming this wiring tion occurs when the active time is deactivated at the same time oil lines an ohmic voltage drop on said network that loads the inactive row lines. It takes place a voltage boost on the inactive row lines that generally proportional to the number of simultaneously active ven row lines and thus proportional to the desired Is time saving. The voltage increase can occur in block the affected row lines the effect of the associated selection transistors of the memory cause cher cells, whereby the information in the specified closed memory cells is partially or completely deleted.

If you limit the resul in multiple wordline select mode discharge current when deactivating the activated time lenleitung, this is advantageous for the holding time of the Memory cells on the inactive row lines are connected because the voltage boost accordingly is reduced. There can be a relatively large number of active ones  Row lines of a memory cell array at the same time be deactivated. However, this can result in the situation ten that the relevant column lines in a Spei access can be deactivated before the selection transistors of the memory cells on the row lines to be deactivated are completely closed. This can lead to destruction the information to be read out or stored at Lead memory access.

The object of the present invention is an inte to specify free storage of the type mentioned at the beginning in normal operation and in a multiple wordline Select operation of the memory reliable reading, Write and hold cell information is enabled.

The task is solved by an integrated memory type mentioned with a control circuit with a Output for the output of a deactivation control signal, the is connectable to the switching device to trigger a Switching of the switching device, in which the tax circuit a delay that can be switched on by a selection signal tion circuit comprises, in the on state the switching process of the switching device can be delayed in Reference to a switching operation of the switching device in the on state of the delay circuit.

The memory according to the invention makes it possible for for example in test operation of the integrated memory in case le of a multiple wordline select mode the deactivation to control the relevant column lines in such a way that the Cell information even with comparatively slow deactivation row lines is retained. A slow deak tivieren the row lines is advantageous for the hold time of memory cells. A test operation to be carried out is displayed via the selection signal. The means of Selection signal switchable delay circuit ensures that for that deactivating the relevant column lines  in relation to a deactivation time in a normal area drive of the memory is delayed in a suitable manner. The The delay circuit is only switched on in test mode switched state, in normal operation it is not in switched on state operated.

In an advantageous embodiment of the invention the control circuit has a transistor on which the Deakti Vierungs control signal is tapped and its Steueran circuit is connected to a connection for a control signal. The delay circuit contains means for reducing an amplitude of the control signal in the on state serve the delay circuit. This way, who can be reached that in test mode the transistor for generating the De activation control signal is not fully switched through, which reduces its current driving ability. This will make one Switching edge of the deactivation control signal or example a switching operation of a downstream inverter hesitates.

For this purpose, the delay circuit advantageously contains a connection for a supply potential that is connected to the An is connectable for the control signal. The supply potential is dimensioned such that the transistor in is in a limited conductive state.

Additionally or alternatively, the delay scarf tion also contain means that the steepness of the Schaltflan ke of the control signal when the delays are switched on reduce the circuit. Due to a reduced slope the switching edge of the control driver controlling the transistor gnals is also a delay in the switching edge of the Deactivation control signal reached.

The invention is particularly advantageously applicable to the Case that a demge for deactivating the row lines similar principle of action is applied. In a  Such embodiment are controllable connecting devices lines for connecting the row lines with a connection for a further deactivation potential provided by another control circuit can be controlled. This has an output for the output of a further deactivation tion control signal to trigger a Schaltvor gear of the connecting devices. Every connection device device has a deactivation transistor, the main current path between the relevant line and the Connection for the further deactivation potential switched is. The control terminal of the deactivation transistor emp catches the further deactivation control signal. The further one Control circuit contains a further selection signal switchable means for reducing an amplitude of the serve further deactivation control signal. In addition or alternatively, the control circuit may contain means for Reduction of the steepness of a switching edge further Disable control signal. In this way the resul discharging current when deactivated in multiple wordline Select operation can be reduced and limited.

Controlling the row line deactivation process takes place according to a similar principle of action as that Control the deactivation of the column lines. This is it is particularly possible that dependencies on technology fluctuations or voltage fluctuations of the supplier voltage can be compensated because such fluctuations are similar effects on the behavior of the circuit to the deak Activation of the row lines and the behavior of the circuit to deactivate the column lines. That’s it allows a delay in the deactivation of the columns lines precisely after the end of the deactivation of the lines adjust lines. This is also in test mode enables comparatively high data throughput because the Ver delay must not be chosen unnecessarily large.  

It is also advantageous to lay out the two scarves training parts as similar as possible. Local in particular Fluctuations can be optimally compensated if the at the circuit parts in the layout are close together and use the same supply and control signals. Accordingly, the selection signals of the two circuit parts can each other correspond. It is also advantageous to use the control circuit and the further control circuit at a common supplier supply voltage.

Further advantageous training and further education are in Un claims specified.

The invention is described below with reference to the drawing illustrated figures, the embodiments of the invention represent, explained in more detail. Show it

Fig. 1 a memory cell array lines of a memory with row and column lines,

Fig. 2 shows a potential profile of a row line and column line ei ner in a read operation,

Fig. 3 shows an embodiment of a control circuit of the in tegrated memory

Fig. 4 shows an embodiment of a further control circuit for deactivating row lines.

In Fig. 1, a memory cell array 1 is shown an integrated memory, the row lines in the form of wordline WL1 and WL2 obligations and column lines in the form of Bitlei obligations BL1 and BL2 has. The memory cells MC1 and MC2 are arranged at intersections of the word lines WL1, WL2 and the bit lines BL1, BL2. These are selected from a respective word line for a read or write operation. For this purpose, the word lines are each connected to an activation potential, so that the connected selection transistors are turned on. A data signal is read from the memory cells or written into one of the memory cells via the bit lines. The bit lines BL1, BL2 are selected via a sense amplifier 4 for this purpose. After the read or write process, the bit lines BL1, BL2 are deactivated, that is to say brought to a deactivation potential GND. This process is also known as "equalizing". The deactivation process is controlled by a deactivation control signal EQL. The sense amplifier 4 contains controllable switching devices through which the bit lines BL1, BL2 are connected to a corresponding connection for the deactivation potential GND.

In Fig. 2 shows a potential profile (VWL1, VBL1) of wordline WL1 and the bit line is tung shows ge in a read operation BL1. To activate the word line WL1, it is connected to an activation potential which has a positive value (H level, for example 2.0 V) and a logic value "1" compared to a reference potential. Correspondingly, the word line WL1 in the deactivated state has a deactivation potential which, for example, corresponds to the reference potential or to a negative potential (L level, for example 0 V or -0.3 V) and defines the logic value “0”.

At the beginning of the reading process, the word line WL1 is activated, as a result of which a data signal from the memory cell MC1 reaches the bit line BL1 (time t0). At time t1, the sense amplifier 4 is activated, as a result of which the bit line BL1 is raised to the H level as a result of the data signal. In normal operation of the memory, the word line WL1 is deactivated in accordance with the dashed curve. In the test mode of the memory, the word line WL1 is deactivated correspondingly more slowly for a multiple wordline select mode. In order to avoid data loss in this case, the deactivation of the bit line BL1 compared to normal operation (dashed line) is delayed accordingly.

In Fig. 3, an embodiment of a control circuit shown ei nes integrated memory according to the invention. The ge shown circuit is used to generate the deactivation control signal EQL for supply to the sense amplifier 4 shown in FIG. 1. The control circuit 3 is used to output the deactivation control signal EQL. A test mode signal TM, which indicates a test operation of the memory, and a selection signal BSEL, which in particular indicates an end of a reading process, serve as input signals.

The control circuit 3 contains two alternatively switchable current branches 31 and 32 . The current branch 32 is connected, for example, in normal operation of the memory, in this case the test mode signal IM has the L level. As a result, the transistor PS is conductive, the transistor P3 of the current branch 31 in the blocking state. At the end of a read access, the signal BSEL changes from H level to L level. This activates the transistor P4, the transistor N1 is de-activated. Accordingly, there is a potential at the input of the inverter 33 which essentially corresponds to the supply voltage V1. This has a positive value and is dimensioned such that the transistor N2 of the inverter 33 is driven into saturation as a result of the potential of its control signal S. The transistor N2 is therefore fully connected. The deactivation control signal EQL can be tapped from the transistor N2 via a further inverter 34 .

In the test mode of the memory, the test mode signal TM has the H level. Accordingly, the transistor P3 is conductive, the transistor P5 in the blocking state. At the end of a memory access, the signal BSEL again drops from the H level to the L level. Accordingly, the transistor P2 is turned on. The current branch 31 is consequently in a switched-on state. The control signal S at the input of the inverter 33 accordingly has a potential or an end amplitude which results from the supply voltage VH minus the forward voltages of the transistors P1-P3 and is reduced compared to normal operation. The supply voltage VH is dimensioned such that the transistor N2 is operated due to the potential of the control signal S in a limited conductive state. The supply voltage VH is, for example, 1.6 V compared to a supply voltage V1 of, for example, 2.0 V. The amplitude of the control signal S can additionally be set by specifically setting the transistor P1, which is connected as a diode. This has a constant voltage drop at the level of its threshold voltage (for example 0.6 V), so that the potential of the control signal S remains significantly lower than in normal operation (supply voltage V1 less the forward voltages of the transistors P4 and P5).

The transistor N2 does not reach its full conductivity and consequently drives a lower current than in normal operation. As a result, the switching process of the subsequent inverter 34 is delayed, so that the signal EQL is delayed compared to normal operation. The delay can be adjusted in a suitable manner in the interaction of the current branch 31 and the inverter 33 and 34 , which accordingly accordingly act together as a delay circuit. This is switched on or off by the test mode signal TM.

A delay can also be achieved by reducing the steepness of the edge of the control signal S. In a suitable measure, the transistors P2 and P3 are designed so that the current branch 31 has a noticeable on-resistance when switched on (higher than the on-resistance of the transistors P4 and P5). The higher this resistance, the flatter the rising edge of the control signal S. The noticeable forward resistance is preferably created before by a relatively small dimensioning of the transistors P2 and P3 (compared to the dimensioning of the transistors P4 and P5).

In FIG. 4 is a circuit portion of the memory is shown with a further control circuit, the activation to the corresponding De serving of word lines of the memory cell array. Fig. 4 shows on the right part of the edge of the memory cell array 1 , in which individual word lines WL are arranged. Each word line WL can be driven to an activation potential via a word line transistor T1, hereinafter referred to as an activation transistor. In the described case, this potential is the H level, so that the selection transistors which are connected to the word lines are switched on. To select the word lines WL, a word line selection signal / WAS is applied. The H level is supplied to the transistors T1 via a common driver line TL.

Furthermore, each word line WL is connected via a second word line transistor T2, hereinafter referred to as a deactivation transistor, to a feed line DL which is connected to a source of a deactivation potential LL. This potential is preferably a level which is even lower or more negative than the L level (for example -0.3 V) in order to reliably block the selection transistors of the memory cell array 1 connected to the word lines.

An address end brings about the activation of word lines WL coder the word line driver signal WTS to the H level and drives the word line selection signal / WAS to the L level. The assigned activation transistors T1 thus switch through, and the relevant word lines are Level driven. Before activation and after termination of When activated, the WTS signal is kept at L level.  

A control circuit 2 is provided for deactivating the word lines WL. This has an output line AL, which is connected to the control connections of all deactivation transistors T2. The output line AL supplies a deactivation control signal DSS to control these transistors. A first input line EW is connected to receive the word line driver signal WTS, a second input line EM is connected to receive a test mode signal MES. A third input line ED is connected to receive a deactivation command signal / DBS.

The control circuit 2 is switchable between two types of operation, for example between normal operation and test operation of the memory. The test mode signal MES is used for switching, which has the L level for normal operation and the H level for test operation. The level converters 20 and 30 are identical to one another and are built up in a manner known per se in order to provide an H level at their output if their signal input has the binary value "1", and an LL level (derived from the potential LL) deliver if their signal input has the binary value "0".

In normal operation, the control circuit 2 works in the usual manner, in order to jump to the output line AL when receiving a word line deactivation command on the input line ED, and thereby drive the deactivation transistors T2 with a steep rising edge to saturation. As a result, the connected word lines WL are discharged to the LL level as quickly as possible via the line DL. In normal operation, only a single word line WL is activated each time and then deactivated using transistors T2. For this purpose, the test mode signal MES is kept at the L level.

The test mode is set so that for the test of the Memory using the multiple wordline select mode, in each of which several word lines WL by L level  of the signal / WAS has been activated on several transistors T1 are and should be deactivated together. For this, the Test mode signal MES set to "1". When the word ends Line activation will be done on the incoming line EW emp caught signal WTS switched to L level. This will Transistor T4 conditioned to pass.

Before the deactivation command appears, the signal / DBS at the command input ED is still at "1", so that the level converter 20 couples the H level to the gate electrode of the transistor T6. The transistor T6 is thus conductive and keeps the output line AL still at LL level, so that the word line deactivation transistors T2 are still kept blocked. The transistor T5 remains non-conductive in the test mode of the control circuit, because its gate electrode receives H level ("1") from the output of an OR gate 10 , since it ses the "1" at one of its two inputs during the test mode. receives from the input line MES. The transistor T7 is turned on for the duration of the test mode by the output signal of the level converter 30 , which is now at LL level, because a "0" appears at the input of this level converter (inverted "1" of the test mode signal MES by inverter 40 ). The transistor T8 remains blocked by the H level from the output of the level converter 20 for the time being.

If the deactivation command is now applied by changing the signal / DBS from "1" to "0", the level converter 20 converts this "0" to LL level at its output, so that the N-FET T6 blocks, thereby the LL potential is separated from the output line AL. The LL potential from the output of the level converter 20 now switches through the P-FET T8, so that this transistor T8, the likewise conductive P-FET T7 and the "diode" T9 establish a conductive connection between the output line AL and the HL potential is established. In this way, the deactivation transistors T2 connected to the output line AL are brought into the conductive state in order to discharge the associated word lines WL to the deactivation potential LL.

The transistors T7, T8, T9 and the potential HL are di mentions that this is in response to the deactivation command resulting deactivation control signal DSS on the line AL has a different characteristic than in normal mode to the Discharge currents in the activated deactivation transistors limit their T2. There is a current limitation if the final amplitude of the signal DSS is below the level ten, which is for the full switching of the Deactiv tion transistors T2 leads. This is achieved through use the potential HL, which is less positive than the H level is (e.g. +1.6 volts), and by the connected as a diode P-FET T9, on which an additional constant voltage ab falls at the level of the threshold voltage Vth of the P-FET T9 (e.g. about 0.6 volts). Thus the deactivation Control signal DSS raised to a level HL-Vth, the remains significantly lower than that in normal operation via the Transistors T4 and T5 reached H levels. The deactivator tion transistors T2 do not reach their full guide ability and therefore drive less electricity than in the north painting mode. Even the inactive copies of the Wortlei lines are thus connected to the supply system DL with high resistance closed. The ratio of the effective channel resistances of the Deactivation transistors T2 to the resistance of the lead system DL is increased in this way, so that the inactive Word lines no harmful voltage increases as a result the discharge currents arise from the active word lines.

Current limitation can also be achieved by reducing the flan ken steepness of the deactivation control signal DSS reached become. With a steep rising edge of this signal discharge flowing through the deactivation transistors T2 flows from the active word lines WL at the beginning of the discharge dung a high tip that contributes a lot to the unwanted Voltage increases on the inactive word lines. In a  particular embodiment of the invention is therefore a measure taken to reduce the slope fen.

In the control circuit 2 shown , this measure consists in designing the circuit branch which contains the series circuit of the FETs T7 and T8 in such a way that it has a noticeable on-resistance when switched on (higher than the on-resistance of the P-FETs T4 and T5). The higher this resistance, the flatter the rising edge of the deactivation control signal DSS, because of the increased RC time constant with the gate-ground capacitances of the deactivation transistors T2. The noticeable forward resistance is preferably created by a relatively small dimensioning of the P-FETs T7 and T8 (compared to the dimensioning of the P-FETs T4 and T5).

In the drawing, P-FETs T7 and TB are transistors shown with reduced threshold voltage. The usage such elements can be advantageous in the sense of the intended Properties of the circuit in question. It can but also transistors without reduced threshold voltage be applied. In the same sense, it can be advantageous the the substrate connections of the transistors T7, T8, T9 to the To set potential HL as shown.

The P-FET T9 connected as a diode can also be replaced by a real diode; it can also be omitted without replacement if the potential HL alone is low enough to achieve the desired reduction in the final amplitude of the signal DSS. Also, instead of the potential HL, the full H level can be found at the end of the current branch in question if the threshold voltage of the P-FET T9 connected as a diode (or a diode located there) is sufficient for level reduction alone; if desired, several transistors connected as diodes (or several diodes) can be connected in series. The noticeable resistance of said current branch to reduce the edge steepness of the signal DSS can also be achieved by inserting an additional ohmic element, or by at least opening one of the transistors T7 and T8, for example by reducing the switch-on level provided by the level converter 30 . It may also suffice to reduce either only the end amplitude or only the slope of the deactivation control signal DSS. The above is also applicable in an analogous manner to the control circuit 3 according to FIG. 3.

The default is general, if several are deactivated Word lines that flow from the individual word lines Limit individual flows so far that the sum of the of these currents remains below a critical value. The measure of current limit to be set depends on how many ak tive word lines one wishes to deactivate at the same time and how high the critical value is. The latter is the main one Lich determined by the design-related impedance of the Supply system for the deactivation potential. This before are the boundary conditions for the setting of the Current limitation and thus for dimensioning the components elements and levels that are in the reduction according to the invention direction can be used to limit the current.

The invention is not limited to the above written and shown in the drawing control scarf tions, which are only exemplary embodiments for realizing the Er are thought of. There are different variations of the described circuit arrangements or alternative Ausfüh possible.

Due to the similarity of the circuit parts of Fig. 3 for De activation of the bit lines and in FIG. 4 of the word lines tion to Deaktivie or by the similarity of their control circuits 3 and 2, the deactivation of the word lines and the bit lines well aufeinan the tunable. A reduced potential VH or HL is also used in both control circuits. Since each subsequent switching transistors are driven weaker, so that their current driving ability is reduced. The bit lines therefore bet connected to the corresponding deactivation potential with a delay similar to that of the word lines. Dependencies on technological fluctuations and dependencies on voltage fluctuations in the supply voltage can be compensated for by a similar circuit-technical structure, since such fluctuations have a similar effect on both circuit parts. This effect can be intensified if both circuit parts in the layout are close together and use the same supply and control signals. In this case, the test mode signal MES from FIG. 4 and the test mode signal TM from FIG. 3 correspond to one another. It is also advantageous if both control circuits 2 and 3 are connected to a common supply voltage, that is to say the potentials of the supply voltages V1 and VH from FIG. 3 correspond to the H potential or HL potential from FIG. 4.

LIST OF REFERENCE NUMBERS

1

Memory cell array

2

control circuit

3

control circuit

4

sense amplifier

10

OR gate

20

.

30

level converter

31

.

32

current branch

33

.

34

.

35

.

36

inverter

40

inverter
BL1, BL2 bit line
WL, WL1, WL2 word line
MC1, MC2 memory cell
EQL deactivation control signal
S control signal
V1 supply voltage
GND deactivation potential
VH supply voltage
T1 to T9 transistor
P1 to P6 transistor
N1, N2 transistor
BSEL selection signal
TM test mode signal
H, HL, L, LL potential
VWL1, VBL1 potential curve
AL output line
DL supply line
ED input line.
EM input line
EW input line
TL driver cable
MES test mode signal
/ DBS deactivation command signal
/ WHAT word line selection signal
WTS word line driver signal
DSS deactivation control signal

Claims (9)

1. Integrated memory
with a memory cell array ( 1 ) which has row lines (WL1, WL2) for selecting memory cells (MC) and column lines (BL1, BL2) for reading or writing data signals of the memory cells,
with a controllable switching device ( 4 ) for connecting one of the column lines (BL1) to a connection for a deactivation potential (GND) for a deactivated state of the column lines,
with a control circuit ( 3 ) with an output for outputting a deactivation control signal (EQL) which can be connected to the switching device ( 4 ) for triggering a switching operation of the switching device,
in which the control circuit ( 3 ) by a selectable signal (TM) switchable delay circuit ( 31 , 33 ) comprises by which, in the switched-on state, the switching process of the switching device ( 4 ) can be delayed in relation to a switching process of the switching device ( 4 ) in not switched on state of the delay circuit. 2. Integrated memory according to claim 1, characterized in that
the control circuit ( 3 ) contains a transistor (N2) on which the deactivation control signal (EQL) can be tapped and the control connection of which is connected to a connection for a control signal (S),
the delay circuit means (VH, P1) for reducing an amplitude of the control signal (S) in the switched-on state of the delay circuit. 3. Integrated memory according to claim 2, characterized in that the delay circuit ( 31 , 33 ) contains a connection for a supply potential (VH) which can be connected to the connection for the control signal (S), the supply potential (VH) being so dimensioned is that the transistor (N2) is placed in a limited conductive state. 4. Integrated memory according to one of claims 1 to 3, characterized in that
the control circuit ( 3 ) contains a transistor (N2) on which the deactivation control signal (EQL) can be tapped and the control connection of which is connected to a connection for a control signal (S),
the delay circuit means (P2, P3) contains to reduce a slope of a switching edge of the control signal (S) in the switched-on state of the delay circuit. 5. Integrated memory according to one of claims 2 to 4, characterized in that
the control circuit ( 3 ) for generating the deactivation control signal contains two alternatively switchable current branches ( 31 , 32 ),
a first current branch ( 32 ) in its on state was applied to the control terminal of the transistor (N2) with a first potential driving the transistor into saturation (V1),
a second current branch ( 31 ) in its on state stood the control connection of the transistor (N2) with a second potential biasing the transistor in the forward direction (VH, P1) and means (VH, P1) for reducing an amplitude of the control signal (S) and / or contains means (P2, P3) for reducing a slope of a switching edge of the control signal (S). 6. Integrated memory according to claim 5, characterized in that in the second current branch ( 31 ) an element acting as a diode (P1) is inserted. 7. Integrated memory according to one of claims 1 to 6, characterized in that
controllable connection devices (T2) are provided for connecting the row lines (WL) to a connection (DL) for a further deactivation potential for a deactivated state of the row lines,
a further control circuit ( 2 ) is provided with an output for the output of a further deactivation control signal (DSS), which can be connected to the connection devices (T2) for triggering a switching operation of the connection devices,
each connection device has a deactivation transistor (T2), the main current path of which is connected between one of the row lines (WL) and the connection (DL) for the further deactivation potential and whose control connection receives the further deactivation control signal (DSS),
the further control circuit ( 2 ) by a further selection signal (MES) switchable means (T9, HL) contains for reducing an amplitude of the further deactivation control signal (DSS). 8. Integrated memory according to one of claims 1 to 7, characterized in that
controllable connection devices (T2) are provided for connecting the row lines (WL) to a connection (DL) for a further deactivation potential for a deactivated state of the row lines,
a further control circuit ( 2 ) is provided with an output for the output of a further deactivation control signal (DSS), which can be connected to the connection devices (T2) for triggering a switching operation of the connection devices,
each connection device has a deactivation transistor (T2), the main current path of which is connected between one of the row lines (WL) and the connection (DL) for the further deactivation potential and whose control connection receives the further deactivation control signal (DSS),
the further control circuit ( 2 ) by a further selection signal (MES) switchable means (T7, T8) contains to reduce a slope of a switching edge of the further deactivation control signal (DSS). 9. Integrated memory according to claim 7 or 8, characterized in that the further selection signal (MES) speaks the selection signal (TM) ent and the control circuit ( 3 ) and the further control circuit ( 2 ) at a common supply voltage (V1, H; VH, HL).