DE10049349A1 - Semiconductor memory (DRAM) device capable of reducing its power supply voltage, has for each word line a line decoder having n-channel transistor connected between gate of p-channel transistor and another n-channel transistor - Google Patents

Abstract

The semiconductor memory device is designed so that the read-amplifier is limited in order to incorporate a MOS-transistor with a reduced threshold voltage (Vthn) so as to prevent the MOS-transistor becoming less resistant to punch-through, even when the level of channel doping is lowered. The memory arrangement (35) has several discrete cells arranged in several lines and several columns. Each word line has a line decoder, the latter having one n-channel MOS transistor connected between the gate of a p-channel MOS transistor and the gate of another n-channel MOS transistor.

Description

The invention relates to the field of semiconductor memories directions and in particular a semiconductor memory device device that can reduce its power supply voltage.

Fig. 17 is a block diagram of a configuration of a dynamic random access memory (hereinafter referred to as DRAM). The DRAM in the figure includes a clock generator circuit 31 , a row and column address buffer 32 , a row decoder 33 , a column decoder 34 , a memory array 35 , a sense amplifier and input / output control circuit 36 , an input buffer 37 and an output buffer 38 .

The clock generator circuit 31 responds to the external control signals / RAS and / CAS by selecting a predetermined operating mode for general control of the DRAM.

The row and column address buffer 32 responds to the external address signals A0 to Ai (where i is an integer not less than 0) by generating the row address signals RA0 to RAi and the column address signals CA0 to CAi, which are then input to the row decoder 33 or entered into the column decoder 34 .

The memory arrangement 35 contains a plurality of memory cells, each of which stores the data of one bit. Each memory cell is arranged at a predetermined address, which is determined by a row address and a column address.

The row decoder 33 responds to the row address signals RA0 to RAi from the row and column address buffer 32 by specifying a row address in the memory arrangement 35 . Column decoder 34 responds to column address signals CA0 to CAi from row and column address buffer 32 by specifying a column address in memory array 35 .

The sense amplifier and input / output control circuit 36 connects a memory cell of an address indicated by the row decoder 33 and the column decoder 34 to one end of a data input / output line pair IOP. The other end of the data input / output line pair IOP is connected to the input buffer 37 and to the output buffer 38 . In the write mode, the input buffer 37 responds to an external control signal / W by transmitting data Dj received from the outside (where j is an integer not less than 0) via the data input / output line pair IOP to a selected memory cell. In the read mode, the output buffer 38 responds to an external control signal / OE by outputting data read from a selected memory cell to the outside.

Fig. 18 is a block diagram showing a configuration of the SpeI cheranordnung 35 and the sense amplifier and input / output control circuit 36 of the DRAM of FIG. 17, while Fig. 19 is a detailed circuit diagram of a configuration of a column of the memory array 35 and the sense amplifier and A display / output control circuit 36 of FIG. 17.

As shown in FIGS. 18 and 19, the memory arrangement 35 comprises a plurality of memory cells MC arranged in rows and columns, the word lines WL provided for each row and the bit line pairs BL and / BL provided for each column.

Each memory cell MC is one of them with the word line WL corresponding line connected. The respective multiple spokes cher cells MC odd columns are alternating with the Bit line BL and / BL connected. The respective multiple spokes cher cells MC even-numbered columns are alternating with the Bit line / BL and BL connected.

Each memory cell MC contains an n-channel MOS transistor 60 for access and a capacitor 61 for information storage. The gate of the n-channel MOS transistor 60 of each memory cell is connected to the word line WL of a row corresponding to it. The n-channel MOS transistor 60 is connected between the bit line BL or / BL of a column corresponding to it and an electrode of the capacitor 61 of the memory cell MC (a storage node SN). The other electrode of the capacitor 61 of each memory cell receives a cell plate potential Vcp. The word line WL transmits an output signal from the row decoder 33 and activates the memory cell MC of a selected row. The bit line pair BL and / BL is used for input and output of a data signal to and from a selected memory cell.

The sense amplifier and input / output control circuit 36 includes a column selection gate 41 , a sense amplifier 42 and an equalizer 43 , which are provided for each column. The column selection gate 41 contains the n-channel MOS transistors 51 and 52 connected between the bit lines BL and / BL or between the data input / output lines IO and / IO. The respective gates of the n-channel MOS transistors 51 and 52 are connected to the column decoder 34 via a column selection line CSL. When the column decoder 34 drives the column select line CSL high or to the select level, the n-channel MOS transistors 51 and 52 are turned on with the bit line pair BL and / BL and the data input / output line pair IO and / IO together get connected.

The sense amplifier 42 contains the p-channel MOS transistors 53 and 54 connected between the bit lines BL and / BL and a node N42 and the n-channel MOS transistors connected between the bit lines BL and / BL and a node N42 ' 55 and 56 . The two respective gates of the MOS transistors 53 and 55 are connected to the bit line / BL, while the respective gates of the MOS transistors 54 and 56 are connected to the bit line BL. The nodes N42 and 42 'receive the sense amplifier activation signals SAP and SAN output by the clock generator circuit 31 . If the sense amplifier activation signals SAP and SAN are driven high or low, the sense amplifier 42 amplifies in response to a slight potential difference ΔV between the bit lines BL and / BL to a power supply voltage Vcc.

The equalizer 43 includes an n-channel MOS transistor 57 connected between the bit lines BL and / BL and the n-channel MOS transistors 58 and 59 connected between the bit lines BL and / BL and a node N43 '. The respective gates of the n-channel MOS transistors 57 and 59 are all connected to the node N43. Node N43 receives a bit line equalization signal BLEQ, while node N43 'receives a bit line potential VBL equal to Vcc / 2. In response, when the bit line equalization signal BLEQ is driven high or reaches the active level, the equalizer 43 equalizes a potential of the bit lines BL and / BL to the bit line potential VBL in response.

The DRAM shown in Figs. 17-19 operates as described below: In the write mode, column decoder 34 allows column select signal CSL of a column corresponding to column address signals CA0 to CAi to be driven high or to reach the active level, with column select gate 41 of Column heads.

In response to a signal / W, the input buffer 37 transmits the externally applied write data via the data input / output line pair IOP to the bit line pair BL and / BL of the selected columns. The write data are provided as a potential difference between the bit lines BL and / BL. The row decoder 33 then enables the word line WL of a row corresponding to the row address signals RA0 to RAi to be driven high or to reach the selection level, with the MOS transistor 60 of the memory cell MC of the row being switched on. The capacitor 61 of a selected memory cell stores the electrical charge depending on the potential of the bit line BL or / BL.

In the read mode, the bit line equalization signal BLEQ is initially driven low, the n-channel MOS transistors 57 to 59 of the equalizer being switched off and the equalization bit lines BL and / BL being stopped. As shown in FIGS . 20A to 20E, the line end encoder 33 then enables the word line WL of a line corresponding to the line address signals RA0 to RAi to be driven high (at time t1) or to reach the selection level. As a reaction, the bit lines BL and / BL have a potential which fluctuates slightly with the size of the electrical charge of the capacitor 61 det activated memory cell MC.

Thereupon, the sense amplifier activation signals SAN and SAP (at times t2 and t3) are successively driven low or high in order to activate the sense amplifier 42 . If the potential of the bit line BL is slightly higher than that of the bit line / BL, that of the MOS transistors 53 and 56 is reduced so that they have a smaller resistance than the MOS transistors 54 and 55 to the potential of the bit line BL high and pull the bit line / BL low. In contrast, when the bit line / BL has a slightly higher potential than the bit line BL, the potential of the MOS transistors 54 and 55 is reduced so that they have a smaller resistance than the MOS transistors 53 and 56 ; to pull the potential of the bit line / BL high and that of the bit line BL low.

The column decoder 34 then enables the column selection signal CSL of a column corresponding to the column address signals CA0 to CAi to be driven high or to reach the selection level, the selection gate 41 leading the column. The data on the bit line pair BL and / BL of the selected column are fed via the column selection gate 41 and the data input / output line pair IO and / IO into the output buffer 38 . The output buffer 38 outputs the read data in response to the signal / OE.

To increase the integration of such a DRAM, the DRAM made of MOS transistors, capacitors, wiring and Interlayer films of reduced size are configured the. If e.g. B. a MOS transistor has a reduced gate length L, however, this reduces a threshold voltage Vth,  which leads to increased leakage current leakage, penetration and the like leads.

It is well known that the effect of the short channel is thereby that the thickness of the gate insulating film can be reduced of a MOS transistor is reduced. If a gate insulation receives an increased electric field, however, the Longevity of the film and thus that of the device is reduced device. This phenomenon is considered time-dependent dielectric Breakthrough phenomenon (TDDB phenomenon) known. To the Reduce the thickness of a gate insulating film and at the same time To maintain its reliability, the gate iso lierfilm received a voltage with reduced level.

However, reducing a voltage applied to the gate insulating film has the following disadvantage: In Fig. 21, two memory cells MC1 and MC2 are provided in the same column. The memory cell MC1 is connected to the bit line BL and to a word line WL1, with its storage node SN1 being kept high (or at the power supply potential Vcc). The memory cell MC2 is connected to the bit line / BL and to a word line WL2, its storage node SN2 being kept high (or at the power supply potential Vcc).

In the read mode shown in Figs. 22A-22E, e.g. B. (at time t1) the word line WL1 high or driven to the selection level, while (at time t2) the sense amplifier 42 is activated and the bit line BL is high and the bit line / BL is driven low. Then (at time t3) the word line WL1 is driven low or to the non-selection level, while (at time t4) the sense amplifier 42 is deactivated and, in addition, the equalizer 43 is activated in order to complete data reading.

With this, the potential Vcc of the word line WL1 from time t2 to time t3 must enable the memory cell MC1 to turn on the n-channel MOS transistor 60 so that the potential Vcc of the bit line BL is restored in the memory cell MC1 at the storage node SN1 can. Thus, when the n-channel MOS transistor 60 has a threshold voltage Vthn with a limit of 0.5 V, an expression Vpp <Vcc + Vthn + 0.5 V must be satisfied.

In addition, the n-channel MOS transistor 60 of the memory cell MC2 has a subliminal leakage current from the time t2 to the time t4 while the bit line / BL is kept low, the potential Vcc of the storage node SN2 of the memory cell MC2 gradually decreasing. If the leakage current is large, the memory should be refreshed in a reduced period of time, which means that a refresh standard cannot be met. Thus, the threshold voltage Vthn of the n-channel MOS transistor 60 z. B. is set to approximately 1.1 V. Thus, because of Vpp <Vcc + 1.6 V, the above expression is provided.

To ensure that a MOS transistor has decreased Film thickness and increased reliability should thus Vpp can be reduced. In a system where the word line WL has 0 V or Vpp, but Vpp should not be too small be less than Vcc + 1.6V.

This disadvantage can be overcome by a word line system with negative voltage proposed below: As shown in FIG. 23 with a solid line, the word line WL in this system has a negative potential VbbA = -ΔV1 or a positive potential Vpp '= Vpp - ΔV1 '. ΔV1 and ΔV1 'are essentially the same voltage. Accordingly, the threshold voltage Vthn of the n-channel MOS transistor 60 of the memory cell MC is also set lower than DV1 = ΔV1 '.

As shown in FIG. 24A, when the low level is restored when the memory cell MC is activated, the gate insulating film of the n-channel MOS transistor 60 thus receives only Vpp ', and the gate insulating film may be more reliable than when he receives Vpp. As shown in FIG. 24B, the gate of the n-channel MOS transistor 60 also receives a negative voltage VbbA when the memory cell MC is deactivated. The subliminal leakage current of the n-channel MOS transistor 60 is thus reduced and the refresh time of the memory is increased.

The negative voltage word line system will now be described in detail. Fig. 25 is a block diagram showing a row decoder unit circuit 70 and a word driver 71 .

The row decoder unit circuit 70 and the word driver 71 provided in the row decoder 33 are provided for each word line WL. The row decoder unit circuit 70 responds to the row address signals RA0 to RAi to generate the signals ZMWL, SD, ZSD and to apply the signals to the word driver 71 .

The ZMWL signal is signaled in response to the row addresses nale RA0 to RAi high (Vpp ') or low (VbbA). The ZSD signal is in response to the row address signals RA0 to RAi high (Vcc) or low (VbbA). The signal SD, one to the signal ZSD complementary signal, becomes high (Vpp ') or low (VbbA). The signals ZMWL and ZSD deliver the four combinations 00 (both low levels), 11 (both high levels) 10 (the first high level gel and the second low level) and 01 (the first low level and the second high level). The signals ZMWL and ZSD only reach then 00 when the row address signals RA0 to RAi are input are previously assigned to the corresponding word line WL  were.

The word driver 71 shown in Fig. 26 includes a p-channel MOS transistor QP1 and the n-channel MOS transistors QN1 and QN2. The source of the p-channel MOS transistor QP1 receives the signal SD, while its gate receives the signal ZMWL and its drain is connected to the word line WL assigned to it. The source of the n-channel MOS transistor QN1 receives the negative potential VbbA, while its gate receives the signal ZMWL and its drain is connected to the associated word line WL. The n-channel MOS transistor QN2 is connected in parallel to the n-channel MOS transistor QN1, with its gate receiving the signal ZSD. The ground of the p-channel MOS transistor QP1 receives Vpp ', while the ground of the n-channel MOS transistor QN1 and QN2 receives VbbA.

Fig. 27 illustrates the operation of the word driver 71 and a voltage applied to the gate insulating film of each MOS transistor QP1 and QN1 and QN2.

When the signals ZMWL and ZSD are 00, an active close becomes reached: The p-channel MOS transistor QP1 is switched on tet while the n-channel MOS transistors QN1 and QN2 are off are switched and the word line WL Vpp 'is reached. In the the gate insulating film of the p-channel MOS Transistor QP1 Vpp '+ | VbbA |, while the gate insulating film of the n-channel MOS transistor QN1 or QN2 no voltage emp catches.

If the signals ZMWL and ZSD are 11 , an inactive state (1) is achieved: the p-channel MOS transistor QP1 is switched off, while the n-channel MOS transistors QN1 and QN2 are switched on and the word line WL VbbA achieved. In this state, the respective gate insulating films of the n-channel MOS transistors QN1 and QN2 receive Vpp '+ | VbbA | and Vcc + | VbbA |, respectively, while the gate insulating film of the p-channel MOS transistor QP1 receives no voltage. Since the p-channel MOS transistor QP1 is turned off, a difference between the gate voltage Vpp 'and the ground voltage Vpp' of the p-channel MOS transistor QP1, ie 0 V, is applied to the gate insulating film .

If the signals ZMWL and ZSD are 10 , an inactive state (2) is achieved: The MOS transistors QP1 and QN2 are switched off, while the n-channel MOS transistor QN1 is switched on and the word line WL VbbA is reached. In this state, the gate insulating film of the n-channel MOS transistor QN1 receives Vpp '+ | VbbA |, while the gate insulating film of the MOS transistor QP1 or QN2 receives no voltage.

If the signals ZMWL and ZSD are O1, an is deactivated State (3) reached: The n-channel MOS transistor QN2 is on switched while the MOS transistors QP1 and QN2 out are switched and the word line WL VbbA is reached. In the received the respective gate insulating films MOS transistors QP1 and QN2 Vpp '+ | VbbA | or Vcc + | VbbA |, while the gate insulating film of the n-channel MOS transistor QN1 receives no tension.

In the described word line system with negative voltage receive the respective gate insulating films of the p- and n-channel MOS transistors QP1 and QN1 but Vpp '+ | VbbA | = Vpp what adversely affects that the MOS transistors QP1 and QN1 are less reliable.

There is another bottleneck when reducing the power supply voltage Vcc of a DRAN. As shown in more detail in FIG. 28, the threshold voltage Vthn of the n-channel MOS transistor 56 must be provided in order to provide a gain in which the bit lines BL and / BL have the respective potentials Vcc / 2 and Vcc / 2, respectively - Have Δ and the sense amplifier activation signals SAP and SAN Vcc or 0 V are less than the gate-source voltage Vcc / 2 of the transistor. In order to reduce the power supply voltage Vcc, the threshold voltage Vthn of the n-channel MOS transistor should also be reduced.

However, when the threshold voltage Vthn of the n-channel MOS transistor is reduced, more current is consumed in the active state. When the operation of the sense amplifier 42 is completed, the bit lines BL and / BL have the potentials Vcc and 0 V, respectively, as shown in more detail in FIG. 29, while the sense amplifier activation signals SAP and SAN have the potentials Vcc and 0, respectively V have, the sub-threshold leakage current IL of the n-channel MOS transistor 55 increases when the threshold voltage Vthn of the n-channel MOS transistor is reduced.

If e.g. B. an n-channel MOS transistor has a threshold voltage Vthn of 0.6 V with an active direct current of 100 µA for has the entire chip, a decrease in Vthn increases 0.1 V the sub-threshold leakage current IL ten times. Like this with the Vthn reduced to 0.4 V leads to an increase in the active direct current to 10 mA. The value of 10 mA is not acceptable value for an active direct current.

In order to reduce the threshold voltage Vthn of a MOS transistor, channel doping must also be reduced, which leads to the MOS transistor being less resistant to penetration. To avoid this, the gate length L of the MOS transistor must be increased, which prevents a reduction in the size of the MOS transistor. Thus, the sense amplifier 42 is limited in that it has a MOS transistor with a reduced threshold voltage Vthn.

The invention is therefore based on the object, a half lead  Storage device to create its power supply can reduce tension, is also very reliable and thus does not have the disadvantages mentioned above.

This object is achieved by a half lead Memory device according to one of claims 1, 6 and 12. Further developments of the invention are in the dependent claims Chen specified.

In one aspect, the invention provides a row decoder with:
a first transistor of a first conductivity type with a first electrode that receives a first signal that can take two values that correspond to a high potential that is higher than a power supply potential and a negative potential, a second electrode that has a corresponding one Word line is connected, and an input electrode, which receives a second signal, which can take two values corresponding to the high potential and the negative potential;
a second transistor of a second conductivity type having a first electrode which receives the negative potential and a second electrode which is connected to a word line corresponding to it;
a third transistor of the second conductivity type with a first electrode that receives the second signal and a second electrode that is connected to the input electrode of the second transistor and an input electrode that receives the current supply potential;
and a signal generator circuit responsive to the application of a row address signal previously assigned to a word line corresponding to it to set the first signal and the second signal to the high potential and the negative potential, respectively, and the corresponding word line to a selection level adjust. If the second signal reaches the high potential, the second transistor receives at its input electrode thus a potential which is equal to the power supply potential minus the threshold voltage of the third transistor. Thus, the gate insulating film of the second transistor receives a voltage that is less than when the second signal is directly applied to the input electrode of the second transistor. Thus, the second transistor can have a more reliable gate insulating film.

Preferably, the row decoder also includes a fourth transistor of the second conductivity type connected in parallel with the second transistor and having an input electrode that receives a third signal that can take two values corresponding to the power supply potential and the negative potential;
wherein the signal generator circuit also in response to the application of a row address signal, which was previously assigned to a corresponding word line, sets the third signal to the negative potential. Thus, the fourth transistor can keep an unselected word line at the negative potential, while the corresponding second signal has the negative potential.

Furthermore, the semiconductor memory device is preferably open a semiconductor substrate is provided, the negative poten tial also to the semiconductor substrate or to a tub of first line type is created by him. Thus a Word line and the semiconductor substrate or the tub that have the same negative potential, which is a simplified one Configuration allows.

Furthermore, an external connection can preferably be provided to the negative potential from the outside at the row deco to put on. Thus the negative potential can stabilize be settled.

Furthermore, a plurality of memory arrangements are preferably provided  hen, each with a circuit for generating the negative Potential is provided to a negative potential at the Row decoder of the memory arrangement corresponding to it increase, the respective output nodes of the plurality Circuits for generating the negative voltage from each other are isolated. Thus, a disturbance between the spokes Arrangements can be reduced.

In a further aspect, the invention provides a line end encoder with:
a first transistor of a first line type with a first electrode which receives a first signal which can assume two values which correspond to a high potential which is higher than a power supply potential and a negative potential, and a second electrode, connected to a word line corresponding to it;
a second transistor of a second conduction type with a first electrode which receives the negative potential, a second electrode which is connected to a word line corresponding to it, and an input electrode which receives a second signal which can take two values which correspond to the correspond to high potential and negative potential;
a third transistor of the first conductivity type having a first electrode receiving the second signal, a second electrode connected to the input electrode of the first transistor, and an input electrode receiving a ground potential;
and a signal generator circuit which responds to the application of a row address signal which has previously been assigned to a word line corresponding to it, in order to set the first signal and the second signal to the high potential and to the negative potential and to match the word line corresponding to it Set selection level. Thus, the first transistor receives a threshold voltage of the third transistor at its input electrode when the second signal reaches the negative potential. Thus, the gate insulating film of the first transistor can receive a voltage that is less than when the second signal is directly applied to the input electrode of the first transistor. Thus, the first transistor can have a more reliable gate insulating film.

Preferably, the row decoder also contains a four th transistor of the second conductivity type with a first elec trode, which receives the second signal, a second elec trode with the input electrode of the second transistor is connected, and an input electrode, which Stromver receives potential, with the second transistor on its input electrode through the fourth transistor receives second signal. When the second signal pots up tial reached, the second transistor can thus at its on output electrode reach a potential that is equal to the current supply potential minus a threshold voltage of the fourth Transistor is. Thus, the gate insulating film of the second Transistor receive a voltage that is less than if the second signal directly to the input electrode of the second Transistor is applied. Thus, the second transistor have a more reliable gate insulating film. So you can the first and second transistors work more reliably.

The line decoder preferably also contains a fifth Second conduction transistor connected to the second tran sistor is connected in parallel and an input electrode sits, which receives a third signal that takes two values men, the the power supply potential and the negative Potential, where the signal generator circuit as Response to the application of a row address signal that is too was assigned before a corresponding word line, the sets the third signal to the negative potential. So can the fifth transistor has an unselected word line received a negative potential, the corresponding second signal has a negative potential.  

Furthermore, the semiconductor memory device is preferably open a semiconductor substrate is provided, the negative poten tial also to the semiconductor substrate or to a tub of which the first line type is created. Thus a Word line and the semiconductor substrate or the tub that have the same negative potential, which is a simplified one Configuration allows.

Furthermore, an external connection can preferably be provided, to have a negative potential from the outside of the row decoder to create. Thus, the negative potential can be stabilized the.

Furthermore, a plurality of memory arrangements can preferably be provided be seen, each with a circuit for generating the negative potential is provided to the negative potential to a row decoder corresponding to the memory arrangement to create, with the respective output nodes of the more than a circuit for generating the negative potential of one are isolated. Thus, a disturbance between the Storage arrangements can be reduced.

In yet another aspect, the invention creates: one Row decoder that responds to a row address signal to select any one of the multiple word lines, where he sets the word line to one selection level and several memory cells assigned to the word line are activated; one for each bit line pair provided sense amplifiers that on the row decoder responds to a corresponding memory to activate the cher cell, being between the corresponding ones paired bit lines a slight potential difference is introduced to one of the corresponding paired bitlei settings to a power supply potential while the other bit line initially for a predetermined time  last for a first negative potential and then for one Ground potential is set; and a first outer appearance conclude to the first negative potential from the outside to the reading to put on amplifiers. Because the sense amplifier is a bit line on the power supply potential and the other bit line initially to the first during a predetermined period of time set negative potential and then to ground potential len, the sense amplifier can be made of a MOS transistor a threshold voltage can be configured that is higher is as if a bit line on the power supply supply potential and the other to ground potential is posed. Thus, the sense amplifier can be increased Working limit. In addition, the first negative potential to be stabilized as it has the first external connector can be supplied.

The semiconductor memory device is preferably on one Semiconductor substrate provided, the first negative poten tial also to the semiconductor substrate or to a tub of which the first line type is created. Thus, the Sense amplifier and the semiconductor substrate or the tub that have the same negative potential, which is a simplified one Configuration allows.

Furthermore, each word line is preferably through the end of the line encoder either to one of the first negative potential ver different second negative potential or on the selection pe gel set, also a second outer connection is provided to the second negative potential from the outside to create the line decoder. Thus, the non-selection is gel of the word line the second negative potential, so that the Data from a memory cell cannot be deleted. Except the second negative potential can be stabilized because it can be supplied via the second outer connection.  

Furthermore, the semiconductor memory device is preferably open a semiconductor substrate is provided, the second negative Potential also to the semiconductor substrate or to a Tub of which the first line type is created. Thus, NEN a word line and the semiconductor substrate or the tub have the same negative potential, which is a simplified one Configuration allows.

Furthermore, each word line is preferably through the end of the line encoder either to the first negative potential or to set the selection level, with the row decoder above the first external connection the first negative potential emp catches. Thus the word line non-selection level is that first negative potential so that the data of a memory cell cannot be deleted.

Furthermore, the semiconductor memory device is preferably open a semiconductor substrate is provided, the first negative Potential also to the semiconductor substrate or to a Tub of which the first line type is created. Thus, nen a sense amplifier and a word line and the half lead tersubstrat or the tub the same negative potential emp catch, which allows a simplified configuration.

Further features and advantages of the invention result itself from the description of embodiments of the invention based on the figures. From the figures show:

Fig. 1 is a circuit diagram showing a configuration of a word driver of a DRAM of a first imple mentation of the invention;

Figure 2 shows an operation of the word driver of Figure 1 and a voltage applied to a gate insulating film of each of its transistors;

Fig. 3 is a circuit diagram showing a configuration of a word driver of a DRAM of a second imple mentation of the invention;

Figure 4 shows an operation of the word driver of Figure 3 and a voltage applied to a gate insulating film of each of its transistors;

Fig. 5 is a circuit diagram showing a configuration of a word driver of a DRAM of a third imple mentation of the invention;

Figure 6 shows an operation of the word driver of Figure 5 and a voltage applied to a gate insulating film of each of its transistors;

Fig. 7 shows a modification of the third embodiment;

8 shows a design of a chip SDRAMs a four-th embodiment of the invention.

FIG. 9A-9G are timing charts for explaining a Ef fekts of the SDRAM of FIG. 8;

Fig. 10 is a circuit diagram for explaining an effect of the SDRAM of Fig. 8;

FIG. 11 is a diagram for explaining an effect of the SDRAM from FIG. 8;

FIG. 12 is an outer configuration of a DRAM of a fifth embodiment of the invention;

Fig. 13 is a block diagram of a main portion of the DRAM of Fig. 12;

FIG. 14A-14D are timing charts of an operation of the Figures 12 and 13 shown DRAMs.

FIG. 15 is a modification of the fifth embodiment;

Fig. 16 shows another modification of the fifth embodiment;

FIG. 17 is the aforementioned block diagram of a general configuration of a DRAM;

Fig. 18 shows the block diagram of a configuration of the memory array and the sense amplifier and input / output control circuit of Fig. 17 already mentioned;

FIG. 19 shows the previously mentioned more detailed circuit diagram of a configuration of a column of the memory array and the sense amplifier and input / output control circuit of FIG. 18;

FIG. 20A-20D, the above-mentioned timing charts of a read operation in the DRAM shown in Fig 17-19.

FIG. 21 shows the above-mentioned diagram for explaining a disadvantage of the DRAM from FIG. 17;

22A-22E, the above-mentioned timing charts for explaining a drawback of the DRAM of Fig. 17.;

FIG. 23 is the aforementioned graph Erläute tion of a word line system with a negative voltage;

FIG. 24A, B the aforementioned diagrams for Erläute tion of an effect of the word line with respect to Figure 23 system described with nega tive voltage.

FIG. 25 shows the block diagram of a main section of a DRAM with the word line system with negative voltage from FIG. 23 applied to it.

Fig. 26 is the circuit diagram already mentioned of a configuration of the word driver shown in Fig. 25;

Fig. 27 shows a previously mentioned operation of the word driver of Fig. 26 and a voltage applied to a gate insulating film of each transistor thereof; and

Fig. 28, 29, the already-mentioned circuit diagrams for explaining a disadvantage of a stärkers Lesever.

First embodiment

FIG. 1 is a circuit diagram showing a configuration of a word driver 1 of a DRAM of a first embodiment of the invention compared to FIG. 26.

As shown in FIG. 1, the word driver 1 differs from a word driver 71 shown in FIG. 26 in that the word driver 1 further includes one between the gate of a p-channel MOS transistor QP1 and the gate of an n-channel MOS transistor QN1 has switched n-channel MOS transistor QN3, the gate of which receives a power supply potential Vcc. A signal ZMWL is input to the gate of the p-channel MOS transistor QP1.

FIG. 2 shows an operation of the word driver 1 of FIG. 1 and a voltage applied to a gate insulating film of each MOS transistor QP1 and QN1 to QN3 in comparison with FIG. 27.

When the signals ZMWL and ZSD are 00, an active close becomes reached: The p-channel MOS transistor QP1 and the n-Ka nal-MOS transistor QN3 are turned on, while the n-Ka nal-MOS transistors QN1 and QN2 are turned off and the Word line WL Vpp 'reached. In this state the Gate insulating film of the p-channel MOS transistor QP1 Vpp '+ | VbbA |, while the gate insulating film of the n-channel MOS Transistor QN1 or QN2 receives no voltage and the gate Insulation film of the n-channel MOS transistor QN3 Vcc + | VbbA | emp catches.

If the signals ZMWL and ZSD are 11 , an inactive state (1) is reached: the p-channel MOS transistor QN3 is switched off, while the n-channel MOS transistor QN2 is switched on. In addition, the gate of the n-channel MOS transistor QN1 is charged via the n-channel MOS transistor QM3 to Vcc-Vthn, where the n-channel MOS transistor QN1 is switched on and reaches the word line WL VbbA. In this state, the gate insulating films of the n-channel MOS transistors QN1 to QN3 receive Vcc - Vthn + | VbbA |, Vcc + | VbbA | or Vpp '- Vcc, while the gate insulating film of the p-channel MOS transistor QP1 receives no voltage. Since the p-channel MOS transistor QP1 is turned on, a difference between the gate voltage Vpp 'of the transistor and the ground voltage Vpp', ie 0 V, is applied to the gate insulating film.

If the signals ZMWL and ZSD are 10 , an inactive state (2) is achieved: the MOS transistors QP1 and QN2 are switched off. In addition, the gate of the n-channel MOS transistor QN1 is charged to Vcc-Vthn via the n-channel MOS transistor QN3, the n-channel MOS transistor QN1 being turned on and reaching the word line WL VbbA. In this state, the gate insulating films of the n-channel MOS transistors QN1 and QN3 receive Vcc - Vthn + | VbbA | or Vpp '- Vcc, while the gate insulating film of the MOS transistor QP1 or QN2 receives no voltage.

If the signals are ZMWL and ZSD O1, an inactive Zu Stand (3) reached: The MOS transistors QN2 and QN3 are turned on while the MOS transistors QP1 and QN1 turned off are switched and the word line WL VbbA is reached. In the The gate insulating films of the MOS transistor receive this state ren QP1, QN2 and QN3 Vpp '+ | VbbA |, Vcc + | VbbA | respectively. Vcc + | VbbA |, while the gate insulating film of the n-channel MOS Transistor QN1 receives no voltage.

When comparing FIG. 27 with FIG. 2, the gate insulating film of the n-channel MOS transistor QN1 receives a voltage in the inactive state (1) and in the inactive state (2) which is higher than Vpp '+ | VbbA | on Vcc - Vthn + | VbbA | is reduced. Thus, the n-channel MOS transistor QN1 can operate more reliably in the word line driver 1 than in the word line driver 71 .

It is noted that the inactive state (1) is held for a longer period of time than the other states when the memory device is actually used, and the increased reliability of the n-channel MOS transistor QN1 in the inactive state (1) improves the reliability of the actual word driver 1 can significantly increase.

Second embodiment

FIG. 3 is a circuit diagram of a configuration of a word driver 2 of a DRAM of a second embodiment of the invention compared to FIG. 26.

As shown in Fig. 3, the word driver 26 distinguishes 2 of the word driver 71 of FIG. Characterized in that the word driver 2 also includes a between the gate of the p-channel MOS transistor QP1 and the gate of n-channel MOS transistor QN1 contains switched p-channel MOS transistor QP2, the gate of which is grounded. The ZMWL signal is input to the gate of an n-channel MOS transistor QN1.

Fig. 4 shows an operation of the word driver 2 of Fig. 3 and a voltage applied to a gate insulating film of each MOS transistor QP1, QP2, QN1, QN2.

When the signals ZMWL and ZSD are 00, an active close becomes was reached: The n-channel MOS transistors QN1 and QN2 wer the turned off. In addition, the gate of the p-channel MOS Transistor QP1 via the p-channel MOS transistor QP2 to | Vthp | discharge, where Vthp is a threshold voltage of a p-channel MOS Represents transistor, wherein the p-channel MOS transistor QP1 is switched on and the word line WL Vpp 'is reached. In the gate insulating films of the p-channel MOS transistors QP1 and QP2 Vpp '- | Vthp | or | VbbA |, wuh rend the gate insulating film of the n-channel MOS transistor QN1 or QN2 receives no voltage.

If the signals ZMWL and ZSD are 11 , an inactive state (1) is achieved: the MOS transistors QP2, QN1 and QN2 are switched on, while the p-channel MOS transistor QP1 is switched off and the word line WL VbbA reached. In this state, the gate insulating films of the MOS transistors QN1, QN2 and QP2 receive Vpp '+ | VbbA |, Vcc + | VbbA | or Vpp 'while the gate insulating film of the p-channel MOS transistor QP1 receives no voltage.

If the signals ZMWL and ZSD are 10 , an inactive state (2) is achieved: The MOS transistors QN1 and QP2 are switched on, while the MOS transistors QN1 and QP1 are switched off and the word line WL VbbA is reached. In this state, the gate insulating films of the MOS transistors QN1 and QP2 receive Vpp '+ | VbbA | or Vpp ', while the gate insulating film of the MOS transistor QP1 or QN2 receives no voltage.

If the signals are ZMWL and ZSD O1, an inactive Zu reached (3): The n-channel MOS transistor QN1 is switched off switches while the n-channel MOS transistor QN2 is turned on becomes. In addition, the gate of the p-channel MOS transistor QP1 via the p-channel MOS transistor QP2 to | Vthp | unload whether the signal SD from VbbA enables the p-channel MOS Transistor QP1 is turned off and the word line WL VbbA reached. In this state, the gate insulating films receive of the MOS transistors QP1, QN2 and QP2 Vpp '| Vthp |, Vcc + | VbbA | or | VbbA |, while the gate insulating film of the n- Channel MOS transistor QN1 receives no voltage.

When comparing FIG. 27 with FIG. 4, the gate insulating film of the p-channel MOS transistor QP1 receives one with respect to Vpp '+ | VbbA | in the active state and in the inactive state (3) on Vpp '- | Vthp | reduced tension. Thus, the p-channel MOS transistor QP1 in word driver 2 can work more reliably than in word driver 71 .

Third embodiment

FIG. 5 is a circuit diagram showing a configuration of a word driver 3 of a DRAM of a third embodiment of the invention compared to FIG. 26.

As shown in Fig. 5, the word driver 26 3 differs from the word driver 71 of FIG. Characterized in that the word driver 3 also connected between the gate of the p-channel MOS Tran sistors QP1 and the gate of n-channel -MOS transistor QN1 contains series-connected p- and n-channel MOS transistors QP2 and QN3, the respective gates of which receive a ground potential GND or a power supply potential Vcc. The ZMWL signal is given to a node between the MOS transistors QP2 and QN3.

FIG. 6 shows an operation of the word driver 3 of FIG. 5 and a voltage applied to a gate insulating film of each MOS transistor QP1, QP2 and QN1 to QN3 in comparison with FIG. 27.

When the signals ZMWL and ZSD are 00, an active close becomes reached: The n-channel MOS transistor QN3 is switched on tet while the n-channel MOS transistors QN1 and QN2 are off be switched. In addition, the gate of the p-channel MOS train transistor QP1 via the p-channel MOS transistor QP2 to | Vthp | discharged, with the p-channel MOS transistor QP1 turned on is reached and the word line WL Vpp 'is reached. In this condition receive the gate insulating films of the MOS transistors QP1, QN3 and QP2 Vpp '- | Vthp |, Vcc + | VbbA | or | VbbA |, during the Gate insulating film of the MOS transistor QN1 or QN2 no span receives.

If the signals ZMWL and ZSD are 11 , an inactive state (1) is reached: The MOS transistors QP2 and QN2 are switched on, while the p-channel MOS transistor QP1 is switched off. In addition, the gate of the n-channel MOS transistor QN1 is discharged via the n-channel MOS transistor QN3 to Vcc - Vthn, while the n-channel MOS transistor QN1 is switched on and reaches the word line WL VbbA. In this state, the gate insulating films of the MOS transistors QN1 to QN3 and QP2 receive Vcc - Vthn + | VbbA |, Vcc + | VbbA |, Vpp '- Vcc and Vpp', respectively, while the gate insulating film of the MOS transistor QP1 receives no tension.

If the signals ZMWL and ZSD are 10 , an inactive state (2) is achieved: the p-channel MOS transistor QP2 is switched on, while the MOS transistors QP1 and QN2 are switched off. In addition, the gate of the n-channel MOS transistor QN1 is charged to Vcc-Vthn via the n-channel MOS transistor QN3, the n-channel MOS transistor QN1 being turned on and reaching the word line WL VbbA. In this state, the gate insulating films of the MOS transistors QN1, QN3 and QP2 receive Vcc - Vthn + | VbbA |, Vpp '- Vcc and Vpp', respectively, while the gate insulating film of the MOS transistor QP1 or QN2 receives no voltage receives.

If the signals ZMWL and ZSD are 01, an inactive Zu reached (3): The n-channel MOS transistors QN2 and QN3 are turned on while the n-channel MOS transistor QN1 is turned off. In addition, the gate of the p-channel MOS Transistor QP1 via the p-channel MOS transistor QP2 to | Vthp | discharged, although the VbbA signal SD allows the p-channel MOS transistor QP1 is turned off and the Wortlei Tung WL VbbA achieved. In this state, the gate Insulating films of the MOS transistors QP1, QN2, QN3 and QP2 Vpp '- | Vthp |, Vcc + | VbbA |, Vcc + | VbbA | or | VbbA |, while the gate insulating film of the n-channel MOS transistor QN1 none Receives tension.

When comparing FIG. 27 with FIG. 6, the gate insulating film of the p-channel MOS transistor QP1 receives a voltage in the active state and in the inactive state (3) which is higher than Vpp '+ | VbbA | on Vpp '- | Vthp | is reduced. In addition, in the inactive states (1) and (2), the gate insulating film of the n-channel MOS transistor QN1 receives a voltage which is higher than Vpp '+ | VbbA | on Vcc - Vthn + | VbbA | is reduced. Thus, the p- and n-channel MOS transistors QP1 and QN1 can operate more reliably in the word driver 3 than in the word driver 71 .

It is noted that the negative voltage VbbA in the first to third embodiments can be generated in a DRAM or supplied to the DRAM from the outside. In the latter case, the negative voltage VbbA can be supplied from the outside via an external pin provided for inputting VbbA into the DRAM 4 , as shown in FIG . Generating the negative voltage VbbA in a DRAM enables the VbbA to be more stable than when it is input to the DRAM from the outside.

While a DRAM mentioned in the introduction is a semiconductor substrate or a p-well of which has a negative Receives voltage Vbb, the substrate voltage Vbb to the negative voltage VbbA are equalized, taking the outside supplied negative voltage VbbA as negative voltage ver can be applied both to a word driver as well as substrate voltage Vbb can be used.

Fourth embodiment

Fig. 8 shows a design of a chip synchronous DRAMs (SDRAMs) 10 of a fourth embodiment of the invention. As shown in Fig. 8, the SDRAM 10 includes a rectangular semiconductor substrate 10 a, four memory zones M1 to M4 (banks No. 1 to No. 4) formed at the respective four corners of the semiconductor substrate 10 a and those for the respective four Memory zones M1 to M4 provided circuits 11 to 14 for generating the negative voltage.

As shown in FIG. 17, the memory zones M1 through M4 each include a row decoder 33 , a column decoder 34 , a memory array 35, and a sense amplifier and input / output control circuit 36 . The memory zones M1 to M4 independently create a row selection operation. The circuits 11 to 14 for generating the negative voltage generate the respective negative voltages VbbA1 to VbbA4 and apply them to the respective storage zones M1 to M4. The negative voltages VbbA1 to VbbA4 are isolated from each other.

The SDRAM 10 operates as described below. As shown in Figs. 9A to 9G, the memory areas M1 and M2 are conveniently subjected to a row selection operation independently, while, as shown in Fig. 10, a word line WL connected to a memory cell MC1 whose storage node SN1 is held high is selected in the memory zone M2, wherein the storage node SN2 of a memory cell MC2, which is connected to a word line WL in the same column as the non-selected memory cell MC1, is also held high.

At time t1, an active command (ACT) is applied to bank no. 2 at the same time as a clock signal CLK changes from low to high. Thus, a selected word line WL is driven high in the memory zone M2 or reaches the selection level, while the bit line BL reaches a potential Vcc / 2 + ΔV. Then the sense amplifier 42 of the memory zone M2 is activated to enable the potentials of the bit lines BL and / BL to be amplified high and low.

At time t2, an active command (ACT) is applied to bank no. 1 at the same time as the clock signal CLK changes from low to high. Thus, a selected word line WL in the memory zone M1 is driven high or reaches the selection level, the sense amplifier 42 of the memory zone M1 being activated in order to amplify a potential difference between the paired bit lines BL and / BL.

At time t3, a precharge command (Pre) for bank no. 1 is applied simultaneously with the transition of the clock signal CLK from low to high. The selected word line WL in the memory zone M1 is thus driven low or receives the non-selection level, the sense amplifier 42 being deactivated and the equalizer 43 precharging the bit line pair BL and / BL to Vcc / 2 and thus equalizing.

At time t4, a precharge command (Pre) is applied to bank no. 2 at the same time as the clock signal CLK changes from low to high. The selected word line WL in the memory zone M2 is thus driven low or reaches the non-selection level, the sense amplifier 42 being deactivated and the equalizer 43 precharging the bit lines BL and / BL to Vcc / 2 and thus equalizing them.

In the SDRAM 10 , the memory zones M1 to M4 receive their respective negative voltages VbbA 1 to VbbA 4 separately from one another. As shown in FIGS. 9A to 9G with a solid line, the unselected word line WL suffers in the same memory zone M1 (M2) when the selected word line WL in the memory zone M1 (M2) is driven high or low, a noise, while the word line WL in the other memory area M2 (M1) no noise it suffers.

In contrast, the four memory zones M1 to M4 in the SDRAM 15 shown in Fig. 11 receive the negative voltage VbbA supplied from a single circuit 16 for generating the negative voltage in connection with each other. As shown in FIGS. 9A to 9G with dotted and solid lines, when the selected word line WL in the memory zone M1 (M2) is driven high or low, not only another word line WL in the same memory zone M1 suffers (M2), but also the word line WL in the other memory zone M2 (M1) a noise.

As shown in FIG. 10, the potential of a word line WL not selected is thus higher than the negative potential VbbA, the electrical charge of the storage node SN2 of the memory cell MC2 via the n-channel MOS transistor 60 on the bit line / BL flows out as a leakage current, which leads to a reduced level of the storage node SN2.

Thus, the fourth embodiment can have more noise prevent, which prevents the memory cell MC more data than the memory cell mentioned in the introduction loses.

Fifth embodiment

FIG. 12 shows an external configuration of a DRAM 20 of a fifth embodiment of the invention, while FIG. 13 is a block diagram showing a major portion thereof.

As shown in FIGS . 12 and 13, the DRAN 20 differs from the DRAMs mentioned in the introduction in that the DRAM 20 is provided with an external pin 21 for receiving a negative voltage VbbS, while also having a charging circuit 22 and includes the n-channel MOS transistors 23 and 24 while the sense amplifier enable signal SAN is replaced by the sense amplifier enable signals SOF and SON.

The charging circuit 22 charges the node N42 'of the sense amplifier 42 to Vcc / 2 in response to the two signals SOF and SON being driven low or inactive. The n-channel MOS transistor 23 is connected between the node N42 'of the sense amplifier 42 and the line of the negative potential VbbS, its gate receiving the signal SOF. The n-channel MOS transistor 24 is switched between the node N42 'of the sense amplifier 42 and the line of the ground potential GND, its gate receiving the signal SON. The signals SOF and SON are generated by the clock generator circuit 31 of FIG. 17.

FIG. 14A to 14D are timing charts showing an operation of the DRAM 20 in the read mode. In the initial state, the signals SOF and SON are both kept low or inactive, while the node N42 'of the sense amplifier 42 is charged to Vcc / 2 by the charging circuit 22 and the sense amplifier 42 is also deactivated. At time t1, the word line WL is driven high or receives the selection level. Thus, it is assumed that the potential of the bit line BL is reduced to Vcc / 2 -ΔV with respect to Vcc / 2. At time t2, the signal SOF is driven high or actively, the charging circuit 22 being deactivated, the n-channel MOS transistor 23 being switched on and the node N42 'of the sense amplifier 42 falling to the negative potential VbbS. In addition, the signal SAP is driven high, the resistance of the MOS transistors 54 and 55 is reduced to a smaller value than that of the MOS transistors 53 and 56 , while the potential of the bit line / BL increases to Vcc and the potential of the bit line BL (at time t3) falls to VbbS.

At time t4, the SOF signal is driven low and the SON signal is driven high, the n-channel MOS transistor 23 being switched off and the n-channel MOS transistor 24 being switched on. Thus the potential of the bit line BL increases from VbbS to 0 V.

At time t5, the word line WL is driven low or  receives the non-selection level. At time t6, the Sig nal SON low while a read operation is paused is and the potentials of the bit lines BL and / BL on Vcc / 2 are equalized, completing a read operation becomes.

In the fifth embodiment, the n-channel MOS transistor 55 has a gate-source voltage of Vcc / 2 + | VbbS | which is | VbbS | from time t2 to time t4 is larger than the transistor with a gate-source voltage of Vcc / 2 mentioned in the introduction. Thus, the n-channel MOS transistors of the sense amplifier 42 are only required for the threshold voltage Vthn Vcc / 2 + | VbbS | <Vthn it fills, whereby Vcc is reduced more easily than if Vcc / 2 <Vthn must be fulfilled as in the introduction.

In addition, the introduction of the negative potential VbbS external to the DRAM 20 enables the negative potential VbbS to be more stable than when it is generated in the DRAM. Thus, the sense amplifier 42 can operate reliably.

Needless to say, the first to fourth embodiments can, if appropriate, be combined with the fifth embodiment. As shown in Fig. 15, in such a combination, the external pins 21 and 25 may be provided for supplying the negative potentials VbbS and VbbA to a DRAM 20 ', or the negative potentials VbbS and VbbA may be at the same potential Vbb ent be equalized, which can be supplied to the DRAM 20 'via an external pin as shown in FIG. 16.

Although the semiconductor substrate or a p-well thereof receives the negative potential Vbb in the DRAM described in the introduction, both the substrate potential Vbb and either both negative potentials VbbS and VbbA or one of them can be equalized to the same potential Vbb which as shown in FIGS. 12, 15 and 16, can be supplied from the outside to be used as or to a word driver and / to a sense amplifier applied negative potential as well as a sub stratpotential Vbb.

Although the invention has been described and explained in detail was, of course, that this is only for explanation and serves as an example and not as a limitation should be stood, the inventive idea and the order catch the invention be only by the appended claims is limited.

Claims (17)

1. A semiconductor memory device comprising:
a memory arrangement ( 35 ) with a plurality of memory cells (MCs) which are arranged in a plurality of rows and a plurality of columns, a plurality of word lines (WLs) each provided for the plurality of rows and a plurality of bit line pairs (BL and / BL) each provided for the plurality of columns;
a row decoder ( 1 , 70 ) provided for each word line (WL), which reacts to the application of a row address signal which has previously been assigned to a corresponding word line (WL) in order to set the corresponding word line (WL) to a selection level and to activate several corresponding memory cells (MCs);
a column decoder ( 34 ) responsive to a column address signal to select any one of the plurality of bit line pairs (BL and / BL); and
a read / write circuit ( 36 to 38 ) which, when activated by the row decoder ( 1 , 70 ), via a bit line pair (BL and / BL) selected by the column decoder ( 34 ), data from a memory cell (MC) reads or writes to them;
wherein the row decoder ( 1 , 70 ) comprises:
a first transistor (QP1) of a first conductivity type having a first electrode which receives a first signal (SD) which can take two values which are high potential (Vpp ') which is higher than a power supply potential (Vcc), and correspond to a negative potential (VbbA), a two-th electrode which is connected to a corresponding word line (WL), and an input electrode which receives a second signal (ZMWL) which can assume two values which correspond to the high potential (Vpp ') and the negative potential (VbbA),
a second transistor (QN1) of a second line type with a first electrode which receives the negative potential (VbbA) and a second electrode which is connected to a corresponding word line (WL),
a third transistor (QN3) of the second conductivity type with a first electrode which receives the second signal (ZMWL) and a second electrode which is connected to the input electrode of the second transistor (QN1) and an input electrode which has the power supply potential (Vcc) receives, and
a signal generator circuit ( 70 ), which reacts to the application of a row address signal, which was previously assigned to a word line (WL) corresponding to it, to the first signal (SD) and the second signal (ZMWL) to the high potential (Vpp ' ) or to the negative potential (VbbA) and to set the corresponding word line (WL) to a selection level. 2. A semiconductor memory device according to claim 1, characterized in that
the row decoder ( 1 , 70 ) contains a fourth transistor (QN2) of the second conductivity type, which is connected in parallel with the second transistor (QN1) and has an input electrode which receives a third signal (ZSD) which can take two values which correspond to the power supply potential (Vcc) and the negative potential (VbbA); and
the signal generator circuit ( 70 ) responds to a row address signal previously assigned to a corresponding word line (WL) to set the third signal (ZSD) to the negative potential (VbbA). 3. The semiconductor memory device according to claim 1 or 2, which is provided on a semiconductor substrate, thereby ge indicates that the negative potential (VbbA) also to the Semiconductor substrate or to a trough of the first conductivity type of which is created.   4. Semiconductor memory device according to one of the preceding claims, characterized by an external connection ( 5 ) in order to apply the negative potential (VbbA) from the outside to the row decoder ( 1 , 70 ). 5. Semiconductor memory device according to one of the preceding claims, characterized in that more than one memory arrangement ( 35 ) is provided, each of which is provided with a circuit ( 11 to 14 ) for generating the negative potential in order to transmit the negative potential to the row decoder ( 1 , 70 ) of the corresponding storage arrangement, the respective output nodes of the more than one circuit ( 11 to 14 ) for generating the negative voltage being isolated from one another. 6. A semiconductor memory device comprising:
a memory arrangement ( 35 ) with a plurality of memory cells (MCs) which are arranged in a plurality of rows and a plurality of columns, a plurality of word lines (WLs) each provided for the plurality of rows and a plurality of bit line pairs (BL and / BL) each provided for the plurality of columns;
a line decoder ( 2 , 3 , 70 ) provided for each word line (WL), which reacts to the application of a row address sensor signal that was previously assigned to a corresponding word line (WL) by the corresponding word line (WL) set a selection level and activate several memory cells (MCs) corresponding to it;
a column decoder ( 34 ) responsive to a column address signal to select any one of the plurality of bit line pairs (BL and / BL); and
a read / write circuit ( 36 to 38 ) which, when activated by the row decoder ( 2 , 3 , 70 ), via a bit line pair (BL and / BL) selected by the column decoder ( 34 ), data from a memory cell ( MC) reads or writes to it;
the row decoder ( 2 , 3 , 70 ) comprising: a first transistor (QP1) of a first conductivity type with a first electrode which receives a first signal (SD) which can assume two values which have a high potential (Vpp ') which is higher than a power supply potential (Vcc) and corresponds to a negative potential (VbbA), and a second electrode which is connected to a corresponding word line (WL),
a second transistor (QN1) of a second line type with a first electrode which receives the negative potential (VbbA), a second electrode which is connected to a corresponding word line (WL), and an input electrode which receives a second signal ( ZMWL), which can assume two values that correspond to the high potential (Vpp ') and the negative potential (VbbA),
a third transistor (QP2) of the first conductivity type with a first electrode that receives the second signal (ZMWL), a second electrode that is connected to the input electrode of the first transistor (QP1), and an input electrode that has a ground potential ( GND) receives, and
a signal generator circuit ( 70 ), which reacts to the application of a row address signal, which was previously assigned to a word line (WL) corresponding to it, to the first signal (SD) and the second signal (ZMWL) to the high potential (Vpp ' ) or to the negative potential (VbbA) and to set the corresponding word line (WL) to a selection level. 7. A semiconductor memory device according to claim 6, characterized in that the row decoder ( 3 , 70 ) has a fourth transistor (QN3) of the second conductivity type with a first electrode which receives the second signal (ZMWL), a second electrode which is connected to the input electrode of the second transistor (QN1) is connected, and an input electrode which receives the power supply potential (Vcc), the second transistor (QN1) receiving the second signal (ZMWL) at its input electrode via the fourth transistor (QN3). 8. A semiconductor memory device according to claim 7, characterized in that the row decoder ( 2 , 3 , 70 ) contains a fifth transistor (QN2) of the second conductivity type, which is connected in parallel with the second transistor (QN1) and has an input electrode which has a third Signal (ZSD) receives, which can assume two values, which correspond to the power supply potential (Vcc) and the negative potential (VbbA), wherein the signal generator circuit ( 70 ) reacts to the application of a row address sensor signal that previously a word line corresponding to it (WL) was assigned to set the third signal (ZSD) to the negative potential (VbbA). 9. The semiconductor memory device according to one of claims 6 to 8 which is provided on a semiconductor substrate since characterized by that the negative potential (VbbA) also to the Semiconductor substrate or to a trough of the first conductivity type of which is created. 10. Semiconductor memory device according to one of claims 6 to 9, characterized by an outer connection ( 5 ) in order to apply the negative potential (VbbA) from the outside to the row decoder ( 2 , 3 , 70 ). 11. A semiconductor memory device according to one of claims 6 to 10, characterized in that more than one memory arrangement ( 35 ) is provided, each being provided with a circuit ( 11 to 14 ) for generating the negative potential in order to transmit the negative potential to the one to apply the respective row arrangement corresponding row decoder ( 2 , 3 , 70 ), the respective output nodes of the more than one circuit ( 11 to 14 ) for generating the negative potential being separated from one another. 12. Semiconductor memory device with:
a memory arrangement ( 35 ) with a plurality of memory cells (MCs), which are arranged in a plurality of rows and a plurality of columns, a plurality of word lines (WLs), which are each provided for the multiple rows, and a plurality of bit line pairs (BL and / BL), each are provided for the multiple columns;
a row decoder ( 33 ) responsive to a row address signal to select any one of the plurality of word lines (WLs), setting the selected word line (WL) to a selection level and activating a plurality of memory cells (MCs) corresponding to the word line (WL);
a sense amplifier ( 22 to 24 , 42 ) provided for a bit line pair (BL and / BL), which responds to the cell decoder ( 33 ) in order to activate a memory cell (MC) corresponding to it, with a pair corresponding to it Bit lines (BL and / BL) a slight potential difference is introduced to set one of the paired bit lines (BL and / BL) that corresponds to it to a power supply potential (Vcc), while the other bit line is initially on for a predetermined period of time a first negative potential (VbbS) is maintained and then set to a ground potential (GND);
a row decoder ( 34 ) responsive to a column address signal to select any one of the plurality of bit line pairs (BL and / BL);
an output circuit ( 38 ) which is operable in such a way that it outputs the data of a logic to the outside depending on the potential difference between the paired bit lines (BL and / BL) selected by the column decoder ( 34 ); and
a first outer terminal ( 21 ) to apply the first negative potential (VbbS) from the outside to the sense amplifier ( 22 to 24 , 42 ). 13. The semiconductor memory device according to claim 12, which on a semiconductor substrate is provided, characterized net that the first negative potential (VbbS) to the Semiconductor substrate or to a trough of the first conductivity type of which is created. 14. A semiconductor memory device according to claim 12 or 13, characterized in that each word line (WL) is set by the row decoder ( 33 ) either to a ver from the first negative potential (VbbS) different second negative potential (VbbA) or to the selection level, wherein a second outer connection ( 25 ) is provided, which applies the second negative potential (VbbA) from the outside to the row decoder ( 33 ). 15. A semiconductor memory device according to claim 14, which on a semiconductor substrate is provided, characterized net that the second negative potential (VbbA) also to the Semiconductor substrate or to a trough of the first conductivity type of which is created. 16. A semiconductor memory device according to one of claims 12 to 15, characterized in that:
each word line (WL) is set by the row decoder ( 33 ) either to the first negative potential (VbbS) or to the selection level; and
the row decoder (33) via the first circuit to the outer (21) receives the first negative potential (VbbS). 17. The semiconductor memory device according to claim 16, which on a semiconductor substrate is provided, characterized net that the first negative potential (VbbS) also to the Semiconductor substrate or to a trough of the first conductivity type of which is created.