DE10041688B4 - Integrated memory with memory cells in a plurality of memory cell blocks and method for operating such a memory - Google Patents

Abstract

Method for operating an integrated memory (10) with memory cells (MC) arranged in at least one of the first and second memory cell blocks (1, 2), each having column lines (BL) and row lines (WL), the memory cells (MC) are each connected to one of the row lines (WL) for selecting one of the memory cells (MC) and one of the column lines (BL) and each memory cell block (1, 2) the column lines (BL) are each connected to a sense amplifier (13, 23) .
In which a memory cell access for reading out or writing a data signal of one of the memory cells (MC) takes place in an access cycle (T),
In which a respective memory cell (MC1, MC2) is selected in each of the memory cell blocks (1, 2) during an access cycle (T) and the respective sense amplifier (13, 23) is used to evaluate a data signal of the respective selected memory cell (MC1, MC2 ) is activated,
- Wherein during the access cycle (T) in each of the memory cell blocks (1, 2) at least one deactivation circuit (TD1, ...

Description

The The present invention relates to an integrated memory with memory cells, arranged in at least a first and a second memory cell block are each having column lines and row lines, wherein the memory cells each with one of the row lines for selecting one of the memory cells and one of the column lines and a method of operating such a memory.

integrated Memory generally has memory cells that are often in a plurality of separate similar memory cell blocks are arranged. These usually have each addressable column lines and row lines. these can for example bit lines or word lines, in whose crossing points the memory cells are arranged. The Memory cells are each with one of the row lines, each serving to select one of the memory cells, and with connected to one of the column lines.

at access to one of the memory cells is generally the concerning row line via a decoder selected. After selecting the relevant row line are to the appropriate Column lines data signals of the memory cells along the row line at. A data signal of a selected one Memory cell is in a sense amplifier of the memory cell array rated and strengthened. In a read access, the data signals of selected memory cells become read out for further processing. For a write access to be written data signals written in selected memory cells. The data signals to be written are, for example, from outside of the memory applied to the respective sense amplifier. For one so-called refresh operation, for example, a DRAM memory become the valued and reinforced Data signals written directly back into the relevant memory cells. Does a memory have multiple separate memory cell blocks, which are also referred to as so-called memory banks, made the usually described operations each separately for each of the memory banks.

One Memory cell access is generally done in one access cycle, in which, for example, a respective memory cell is selected in each case, the corresponding sense amplifier is activated, a write command is created and finally the selected Row line is deactivated again. In a normal operation of the Memory is a memory cell access generally only on memory cells one of the memory banks. That is, for one Memory cell access is during an access cycle only one of the memory banks or their sense amplifier activated.

Especially while a test operation of a memory in which generally the same information written into several memory cells and read out again, this results in a time saving compared to a normal operation of Memory by for a memory cell access during a Access cycle memory cells of multiple memory banks in parallel with the information to be discribed. This requires, in particular, several memory banks or their sense amplifier activate in parallel (so-called multi-bank activation). By the parallel activation of a larger number of sense amplifiers can the problem arise that the short - term summed up electricity demand leads to a collapse of the Supply voltage leads. To this unwanted voltage dip To avoid this, it is necessary in this case, the number of parallel to activating memory banks or their sense amplifier to restrict, So that the Approx. Supply voltage remains constant. The time required for a test operation is thereby comparatively increased.

US 6,049,502 relates to a multi-bank memory system in which different memory banks can be accessed simultaneously in a test mode and in a non-test mode, wherein after a memory access, all memory banks are simultaneously pre-loaded by means of a precharge command PRE. This can speed up a write operation.

DE 39 08 723 A1 relates to a semiconductor memory device having a plurality of memory cells and sense amplifiers in a first memory array region and memory cells and sense amplifiers in a second memory array region. In a read operation, first, the sense amplifiers in a region having a memory cell designated by an address signal are activated, and only then are the sense amplifiers in the other region activated. As a result, since the amplification operation of the sense amplifiers is sequential, it is achieved that a peak value of a current taken by the amplification can be reduced.

DE 32 23 599 A1 relates to a method for operating an integrated memory, in which an activation of a deactivation circuit for row lines takes place when a sense amplifier is not activated.

The object of the present invention is to provide a method for operating an integrated memory of the aforementioned type, by the particular time required for a Testbe operation of the memory can be kept relatively low.

Besides that is It is an object of the present invention to provide an integrated memory specify the type mentioned, in which in particular a comparatively less time is required to test the memory.

The Problem concerning the method is solved by a method for Operation of an integrated memory according to claim 1.

The Task concerning the integrated memory is solved by an integrated memory according to claim 6th

According to the inventive method the memory cell blocks of the memory or its sense amplifier during an access cycle activated offset to each other in time. This will in particular achieved that one by the activation resulting power demand in a certain Period is distributed, so that no short-term, comparatively large voltage dip of the supply voltage arises. Accordingly, in principle any number of independent Memory cell blocks or memory banks be activated staggered over time. Since the respective sense amplifier for Evaluation of the respective data signal but quasi parallel in one Access cycle can be activated, especially in a test mode the time needed for a write access can be kept comparatively low.

The time staggering of the activation of the sense amplifier is according to the integrated invention Memory controlled by the control circuit. The control circuit is advantageously realized such that, for example, only one activation command of an external test device or a controller must be created, the time-delayed activation of Memory cell blocks or the sense amplifier however, be made by the control circuit itself.

In an embodiment the memory of the invention contains the control circuit has a memory device for storing Information in which chronological order the sense amplifiers of the first and second memory cell block can be activated. For example is stored in the memory means, that first the sense amplifier of the first memory cell block and then the sense amplifier of the second memory cell block is activated.

In a further advantageous embodiment of the integrated Contains memory the control circuit delay elements for controlling the timing of the activation of the sense amplifier of first and second memory cell blocks. Based on the delay elements can Signals are derived to control the timing the activation of the sense amplifier serve. The setting of the delay elements can be done, for example, in the design process of the memory. As well Is it possible, the delay elements for example about to set programmable elements such as laser fuses accordingly.

In another advantageous embodiment of the integrated memory is the control circuit with a terminal for a clock signal linked to the timing of activation of the sense amplifier of the first and second memory cell block is controllable. Timing of the process is derived from the clock signal.

In an advantageous embodiment the method according to the invention becomes the sense amplifier for example, the second memory cell block is then activated, if the power requirement of the previously activated sense amplifier of the first memory cell block has exceeded a maximum amount. For the Case, that first the sense amplifier of the second memory cell block is activated in reverse Order procedure. By such a procedure is a comparatively greater Burglary of the supply voltage largely prevented.

The inventive method is similar Way to a following on the evaluation of the data signals write access or read access applicable. This is done during the access cycle respectively to one connection each the memory cell blocks a write command to write the data signal into the respective one selected Memory cell or a read command for reading a Data signal from the respective selected memory cell applied. The respective write command or read command, for example from a parent Write command or read command of a test device or Derived from the controller. The creation of the write command or read command to a connection of the second memory cell block is offset in time to the application of the write command or read command to the terminal of the first Memory cell block. This means, a write command with the same data signals for all memory cell blocks or a read command is executed in the same way as the previous one Activation of the sense amplifiers processed.

According to the invention, the deactivation of a previously selected row line is handled in the same way. During the access cycle At least one deactivation circuit for deactivating (deselecting) a respective row line is activated in each of the memory cell blocks. The activation of the deactivation circuit of the second memory cell block takes place at a time offset to the activation of the deactivation circuit of the first memory cell block. Since in this case the deactivation takes place with a time delay, so-called timing parameters, such as so-called writing windows (time interval between the application of a data signal to be written on the relevant column line and the deactivation of the respective row line) or the cycle time for the memory for test the different memory cell blocks in parallel.

The inventive method is also advantageous to a refresh operation of the integrated Memory applicable. By reading out data signals from several selected memory cells quasi-parallel in one access cycle into the respective memory cells written back can be a shortening the refresh time in normal memory operation can be achieved. By the timing of the activation of the respective sense amplifier is a break in the supply voltage during the refresh operation avoided.

The Invention offers the further advantage that in addition to avoiding a comparatively large Burglary of the supply voltage thereby also the time intervals between the individual actions in the memory cell blocks remain essentially unchanged. This means, These so-called core timings correspond during a test operation the respective core timings of a normal operation of the memory.

Further advantageous embodiments and further developments are the subject of dependent claims.

The Invention will now be described with reference to the drawing Figures, each embodiments represent the invention, closer explained. Show it:

1 an embodiment of an integrated memory according to the invention;

2 a timing of command signals to operate the memory according to 1 ,

1 shows an embodiment of an integrated memory 10 comprising memory cells MC, each in a first memory cell block 1 with a memory cell array 11 and in a second memory cell block 2 with a memory cell array 21 are arranged. The memory cell blocks 1 and 2 be here as memory banks 1 and 2 designated. They each have column lines BL and row lines WL. At intersections of row lines WL and column lines BL, the memory cells MC are respectively connected to one of the row lines WL and one of the column lines BL. The memory cells MC of the shown memory each include a selection transistor and a storage capacitor. In this case, control inputs of the selection transistors are connected to one of the row lines WL, while a main current path of the selection transistors is arranged between the storage capacitor of the respective memory cell MC and one of the column lines BL. The row lines WL serve to select one of the memory cells MC, by activating the corresponding row line of the respective selection transistor of a memory cell MC to be selected is turned on.

Each of the memory cell arrays 11 and 21 is a sense amplifier 13 respectively 23 assigned. The column lines BL of the respective memory banks 1 and 2 are each with the respective sense amplifier 13 respectively 23 connectable. The sense amplifiers 13 and 23 serve in particular for evaluating a data signal of a corresponding selected memory cell MC. The sense amplifiers 13 and 23 are also applied to a supply voltage V1.

The row lines WL of the respective memory banks 1 and 2 are via decoder circuits 12 respectively 22 controllable. About the decoder 12 and 22 the relevant row lines WL to be selected are activated. They also serve to control the deactivation of a previously selected row line WL. In order to deactivate the row lines WL, deactivation circuits TD1 and TD2 shown schematically are activated in a suitable manner. The row lines WL are switched to the deactivation voltage VD.

The integrated memory 10 also has a control circuit 4 on top of that with the memory banks 1 and 2 connected is. The control circuit 4 be different signals, for example, from a test device or controller inte grated circuit on which the memory 10 is fed. The signal ADR is an address signal for addressing the memory banks 1 and 2 and for addressing the respective memory cells MC. The control circuit 4 In addition, a bank activation command BA, a write command WR and a deactivation command PC are supplied. In addition, the control circuit 4 connected to a clock signal CLK.

The following is an example operation of the memory according to FIG 1 based on a temporal Sequence of the signals BA, WR and PC according to 2 explained in more detail. In particular, an exemplary test mode is described in which the memory cells MC1 and MC2 are described with data signals DA1 and DA2 during an access cycle. The illustrated operation is similarly applicable to a read operation.

The memory cell access to the memory cells MC1 and MC2 occurs in an access cycle with the time duration T. During the access cycle, in each of the memory banks 1 and 2 the respective memory cell MC1 or MC2 selected by the respective row line WL is activated. For this purpose, an activation command BA to the control circuit 4 created. From the activation command BA, the individual activation signals BA1 and BA2 and BA3 are generated for a third memory bank, not shown. The sense amplifiers BA1 and BA2 activate the sense amplifiers 13 respectively 23 set to an activated state. In this case, the activation of the sense amplifier takes place 23 due to the signal BA2 offset in time to the activation of the sense amplifier 13 due to the signal BA1.

The time-delayed activation of the sense amplifiers is provided by the control circuit 4 performed. This has a memory device for this purpose 5 which contains information as to which of the sense amplifiers is to be activated first. This information may be stored in volatile or non-volatile memory elements. The signal BA1 is generated at the time t01, the signal BA2 at the time t02. Likewise, an analog signal BA3 is generated for another memory bank at the time t03. To determine the individual points in time, the control circuit 4 delay elements 6 on, by which the temporal sequence of the signals BA1 to BA3 can be controlled. The time interval between the times t02 and t01 is advantageously selected such that a current requirement of the first activated sense amplifier 13 has exceeded its maximum. The staggered activation of the sense amplifiers causes a certain drop in the supply voltage V1, which, however, has no significant influence on the operation of the memory.

By activating the sense amplifier 13 and 23 the data signals of the memory cells MC1 and MC2 in the respective sense amplifier are evaluated and amplified. For a refresh operation, the amplified data signals are written back to the respective memory cells MC1 and MC2. To write the data signals DA1 and DA2 in a test operation of the memory is to the control circuit 4 a write command WR has been created. For this, in the same way as the command signals BA1 to BA3, the write commands WR1 to WR3 for the individual memory banks by the control circuit 4 generated. The write accesses to the individual memory banks are delayed in the same order. This results in the same so-called core timing distances Δtc1 and Δtc2. The generation of the individual write commands WR1 to WR3 is in turn in the control circuit 4 performed. Write command WR1 for the memory bank 1 is generated at time t11, the write command WR2 for the memory bank 2 offset in time at time t12.

At the completion of the memory cell access, deactivating circuits TD1 and TD2 are activated to deactivate the respective selected row lines WL. For this purpose, a deactivation command PC to the control circuit 4 created. The se generates the staggered deactivation commands PC1 and PC2 for the memory banks 1 and 2 at the times t21 and t22. The deactivation commands PC1 and PC2 serve to activate the deactivation circuit TD1 or TD2. In this case, the times t21 and t22 are advantageously selected such that again the same core timing intervals Δtc3 and Δtc4 result. The deactivation commands PC1 to PC3 are in the control circuit 4 generated. Alternative to the delay elements 6 The timing of this process can also be derived from the externally applied clock signal CLK.

The Data signals DA1 and DA2 become quasi within the cycle time T. written in parallel in the memory cells MC1 and MC2. As a result, in particular, the time duration for a test operation of the memory shortened, in which the same information in the form of the data signals DA1 and DA2 is written into several memory cells. Because a comparatively greater Voltage drop V1 is avoided, is the timing behavior while the test operation in comparison to a normal operation in an advantageous Way not changed.

1, 2

Memory cell block

4

control circuit

5

memory device

6

delay elements

10

Storage

11 21

Memory cell array

12 22

decoder

13 23

sense amplifier

MC, MC1, MC2

memory cells

BL

column lines

WL

row lines

T

access cycle

WR, WR1, WR2, WR3

write command

BA, BA1, BA2, BA3

activation command

PC, PC1, PC2, PC3

deactivation command

ADR

address signal

DA1, DA2

data signal

V1

supply voltage

VD

deactivation voltage

TD1, TD2

deactivation circuit

CLK

clock signal

Δtc1, Δtc2, Δtc3, Δtc4

Core timing distance

t01, t02, t03, t11, t12, t13, t21, t22, t23

time

Claims (9)

Method for operating an integrated memory ( 10 ) with memory cells (MC), which in at least a first and a second memory cell block (MC) 1 . 2 ) are arranged, each having column lines (BL) and row lines (WL), wherein the memory cells (MC) are each connected to one of the row lines (WL) for selecting one of the memory cells (MC) and one of the column lines (BL) and per memory cell block ( 1 . 2 ) the column lines (BL) each with a sense amplifier ( 13 . 23 ) in which a memory cell access for reading out or writing a data signal of one of the memory cells (MC) takes place in an access cycle (T), in which during an access cycle (T) in each of the memory cell blocks ( 1 . 2 ) a respective memory cell (MC1, MC2) is selected and the respective sense amplifier ( 13 . 23 ) is activated for the evaluation of a data signal of the respective selected memory cell (MC1, MC2), in which case during the access cycle (T) in each of the memory cell blocks ( 1 . 2 ) at least one deactivation circuit (TD1, TD2) for deactivating a respective row line (WL) is activated, characterized in that - the activation of the sense amplifier ( 23 ) of the second memory cell block ( 2 ) offset in time to the activation of the sense amplifier ( 13 ) of the first memory cell block ( 1 ), the activation of the deactivation circuit (TD2) of the second memory cell block ( 2 ) offset in time to the activation of the deactivation circuit (TD1) of the first memory cell block ( 1 ) he follows. Method according to Claim 1, characterized in that the sense amplifier ( 23 ) one of the memory cell blocks ( 2 ) is activated when a power requirement to activate the amplifier ( 13 ) of the respective other memory cell block ( 1 ) has exceeded a maximum amount. Method according to Claim 1 or 2, characterized in that - during the access cycle (T), in each case to one terminal of each of the memory cell blocks ( 1 . 2 ) a write command (WR1, WR2) for writing a data signal (DA1, DA2) to the respective selected memory cell (MC1, MC2) is applied, - the application of the write command (WR2) to the terminal of the second memory cell block ( 2 ) offset in time to the application of the write command (WR1) to the terminal of the first memory cell block ( 1 ) he follows. Method according to Claim 1 or 2, characterized in that - during the access cycle (T), in each case to one terminal of each of the memory cell blocks ( 1 . 2 ) a read command for reading a data signal (DA1, DA2) from the respective selected memory cell (MC1, MC2) is applied, - the application of the read command to the terminal of the second memory cell block ( 2 ) offset in time from the application of the read command to the terminal of the first memory cell block ( 1 ) he follows. Method according to one of Claims 1 to 4, characterized in that information is stored about the order in which the activation of the sense amplifiers ( 13 . 23 ) of the first and second memory cell blocks ( 1 . 2 ) is made. Integrated memory - with memory cells (MC), which are in at least a first and a second memory cell block ( 1 . 2 ), each of which has column lines (BL) and row lines (WL), in which the memory cells (MC) are each connected to one of the row lines (WL) for selecting one of the memory cells (MC) and one of the column lines (BL) are, - in which per memory cell block ( 1 . 2 ) the column lines (BL) each with an activatable sense amplifier ( 13 . 23 ) are connectable for evaluating a data signal of a corresponding memory cell (MC), - in which per memory cell block ( 1 . 2 ) at least one deactivation circuit (TD1, TD2) is provided for deactivating a respective row line (WL), - with a control circuit ( 4 ) associated with the memory cell blocks ( 1 . 2 ), characterized in that - the memory cell blocks ( 1 . 2 ) in such a way by the control circuit ( 4 ), that the sense amplifiers ( 13 . 23 ) of the respective memory cell blocks ( 1 . 2 ) are operable overlapping in an activated state and the sense amplifier ( 23 ) of the second memory cell block ( 2 ) offset in time to the sense amplifier ( 13 ) of the first memory cell block ( 1 ) is activatable, - the deactivation circuits (TD1, TD2) in such a way by the control circuit ( 4 ), that the activation of the deactivation circuit (TD2) of the second memory cell block ( 2 ) time-shifted for the activation of the deactivation circuit (TD1) of the first memory cell block ( 1 ) he follows. Integrated memory according to Claim 6, characterized in that the control circuit ( 4 ) a memory device ( 5 ) for storing information, in which chronological order the sense amplifiers ( 13 . 23 ) of the first and second memory cell blocks ( 1 . 2 ) are activated. Integrated memory according to Claim 6 or 7, characterized in that the control circuit ( 4 ) Delay elements ( 6 ) contains for controlling the timing of the activation of the sense amplifier ( 13 . 23 ) of the first and second memory cell blocks ( 1 . 2 ). Integrated memory according to Claim 6 or 7, characterized in that the control circuit ( 4 ) is connected to a terminal for a clock signal (CLK), based on which the timing of the activation of the sense amplifier ( 13 . 23 ) of the first and second memory cell blocks ( 1 . 2 ) is controllable.