DD288684A5 - CIRCUIT ARRANGEMENT FOR A CONTROL UNIT OF THE DMA MODULE FOR SCREEN REFRESH CONTROL WITH SCREEN CONTROL FOR QUICK MICROPROCESSOR SYSTEMS OR LONG-DYNAMIC STORAGE IN REAL-TIME OPERATION - Google Patents

Abstract

The invention relates to a circuit arrangement for a control unit of the DMA module for screen refresh control with screen control for fast microprocessor systems or slow dynamic memory in real-time operation. It includes a control unit of the DMA module for screen refresh control with screen control for fast microprocessor systems or slow dynamic memory in real-time operation, which for the dynamic memory of the screen control independently refresh cycles can be generated. To the ready signal flip-flop (FF1) and the bus shut-off flip-flop (FF2) with the clocking gates (G1) and clocking gates (G2) connected upstream from the clock inputs (C), a reset gate (G3) is connected according to the invention and a control circuit is controlled via a pulse shortening circuit (IVS) Write and DMA acknowledge signal flip-flop (FF3) whose output (Q) is connected both to the DMA acknowledge and write signal line (DACK; WRCRT) and to a clock input (C) of a controlled memory flip-flop (FF4 ) for switching the data * is connected. Fig. 1 {control unit; DMA block; Screen refresh controller; fast microprocessor systems; slow dynamic memory; Real time; Refresh cycles; Ready signal flip-flop; Busabschaltungs flip-flop; Clock gate; Clock control gates}

Description

For this 2 pages drawings

Field of application of the invention

The invention relates to a circuit arrangement for a control unit of the DMA module for screen refresh control with screen control for fast microprocessor systems or slow dynamic memory in real-time operation.

Characteristic of the known technical solutions

Known technical solutions use a separate image memory for the realization of a screen control (see DE-OS 3222704).

However, such a solution requires a lot of effort for the separate image refresh memory and for the multiplexer used, which are needed for the address, data and control lines.

Another solution (Intel Component Data Catalog p. 9-358) assumes that part of the system memory is used as a frame buffer. The data access is practiced; implemented a DMA block.

The work of the microprocessor is interrupted by the DMA accesses. It takes up to 30% of the runtime of a program to access the image refresh memory. In a further technical solution (see DD-WP 148 267 G 06 F3 / 147), it is proposed to perform a transparent DMA access using refresh cycles. No additional time is required for the system and no separate frame buffer is required.

Since the remaining refresh cycles need to be sufficient to refresh the dynamic memories, this solution can only be used on systems with a small display repository (e.g., small LED displays).

Another solution (see DD-WP 231971 G 06 F 3/153) is based on the simultaneous use of the DMA read cycles as refresh cycles for the entire dynamic memory.

A disadvantage is in addition to the high component cost that the default DMA controller requires fixed addresses for the frame buffer. Thus, the advantages of the CRT controller can not be fully exploited.

In a further developed solution (DD-WP 233003 G 06 F 3/153), the screen control is equipped with a DMA module and a DMA-capable CRT controller. Refresh cycles are also shared by the DMA controller.

A disadvantage of this solution is that in all refresh cycles of the central processing unit, which has a decoding phase of not more than 2 clocks, an additional BUSRQ clock must be inserted. This increases the program runtime and the microprocessor system can not reach its full capacity.

In order to avoid interruptions of the CPU, another solution (see DD-WP 245281 G 06F 3/153) again uses a separate frame buffer. The advantage of being able to do without the insertion of additional clocks is due to a limitation of the flexibility of the system.

By means of a further solution (see DD-WP 270396 G 06 F 03/153), it is achieved to use a part of the system memory as a frame buffer, wherein the data access by the DMA controller takes place in the refresh clocks of the CPU. There is no interruption of the work of the CPU. The system is flexible. All the advantages of the CRT controller can be used.

A provided with such a screen control microprocessor system is not affected by the operation of the screen in its performance.

If the processing width is maintained, a further increase in the computing power of the system can only be achieved by increasing the system clock frequency. However, using the described technical solution in high-speed microprocessor systems with high system clock frequencies is not possible, nor is it possible to use a RAS-CAS controller with a long detection time to drive slow memory circuits.

Object of the invention

The aim of the invention is to develop a screen control that is suitable for use in fast microprocessor systems with low component cost or allows the use of slow dynamic memory, without the advantages of the known technical solutions such as reducing the software cost, the freely programmable screen format, the comfortable Screen design, ease of adaptation to existing systems, and the ability to display pseudo-graphics.

Explanation of the essence of the invention

The invention has for its object to develop a screen control, which works without additional Hitistakte and without interruption of the central processing unit and by a modified control of the DMA controller and providing the data for the CRT controller use in fast microprocessor systems or use slow dynamic memory allowed. This control should work regardless of the type of RAS-CAS control when using dynamic storage.

AusfOhrungsbelspIel The invention will be explained in more detail using an exemplary embodiment. The figures show Fig. 1: Circuit arrangement for a control unit of the DMA module for controlling the CRT controller, the DM V

Controller, the address, data and control bus drivers as well as for the intermediate buffering of the data for the CRT controller Fig. 2: Timing diagram for a command slave cycle M1 with transparent DMA transfer.

In the control unit of the DMA module gem. Fig. 1 is the line for the DMA request signal DRQ once to the control input D of the ready signal flip-flop FF1 with the output Q for the line of the ready signal RDY to the DMA controller and on the other to the input D of the bus-off flip-flop FF2 with the output O ' ¹ Jr connected the line of the bus shutdown BAO to the DMA co- controller. The lines for the command summer cycle M1 and the memory request signal MREQ are connected to the clock input C of the ready signal flip-flop FF1 via the clock gate G1, and the lines for the command summer cycle MT and the ready signal RDY are connected to the clock input C of the bus-off flip-flop FF2 via the clock control gate G 2 , The lead for the read signal RD leads to the reset input_R of the ready signal flip-flop FF1 and to a pulse extension circuit IVS which leads both to the reset input R of a write and DMA acknowledge signal flip-flop FF3 and to the input of a reset gate G3 another input is connected to the line for the reset signal RESET. The output of the reset gate G 3 is connected to the reset input R of the bus-off flip-flop FF2. Furthermore, the lines for the reset signal RESET are connected to the set input S and that of the memory request signal MREQ to the clock input C, the write-in and DMA confirmation signal flip-flop FF3. A controlled memory flip-flop FF4 whose clock input C is connected to the output Q for the DMA acknowledge signal DAKK and the write signal WRCRT of the write-in and DMA acknowledge signal flip-flop FF3, turns on the data bus DO ... D7. The embodiment shows the application of the invention in a high-speed microprocessor system with a UA880 D central processing unit, a UA858 D DMA controller, and a DAM-capable 8275 CRT controller.

The on-screen display requires the corresponding data from the frame buffer that is part of the system memory. This is done by alternately filling one of his 2 line puffs. The signals swept over are low-active gostaltet.

To fill the memory of the CRT controller, it sends the DMA request signal DRQ to the control unit of the DMA module to the control input D of the ready signal flip-flop FF1 (see Fig. ₁ ). About the clock gate G1 coming from the central processing unit via the lines for the instruction summer cycle M1 and the memory request signal MREQ signals are linked and fed to the clock input C of the ready signal flip-flop FF1. If both signals are low and the DMA request signal DRQ is present, the standby signal flip-flop FF1 has the standby signal RDY activated and started at the output Q of the DMA controller. The corresponding pulse course for the command shell is; ycl M1 shown in Fig. 2. The output Q of the ready signal flip-flop FF1 with the ready signal RDY is supplied to the clock control gate G 2, thus preparing the take-over clock for the bus-off flip-flop FF2. If the line connected to the second input of the clock control gate G 2 has high potential for the Bofehlsholezylklus M1, then high potential reaches the clock input C of the bus shutdown flip-flop FF2, so that its output Q, the present at the control input D high potential of the DMA Request signal DRQ. With this formed Busabschaltungssignal BAO the address, data and control bus drivers are switched to the high-impedance state.

If the read signal RD assumes a low potential, the ready signal flip-flop FF1 is reset via its reset input R, so that a low potential is present at the output Q. The pulse shortening circuit IVS is activated by the low / high edge of the read signal RD coming from the DMA controller. On the output side, a short low signal is generated which resets the write-in and DAM confirmation signal flip-flop FF3 via the reset input R, so that the controlled memory flip-flop FF4 is switched to the storage mode via the clock input C connected to the output Q. Thus, the applied data DO .D.7 are stored in the controlled memory flip-flop FF4 and can be queried by the CRT controller a . The data D0... D7 remain active until, with the low / high edge of the memory request signal MREQ at the clock input C of the write-in and DMA confirmation signal flip-flop FF3, this is set so that the clock input C connected to the output Q is set the controlled memory flip-flop FF4 is switched to the transparent mode. This means that the data can be written to the CRT controller even after the refresh cycle has ended, without burdening the computer bus and interrupting the work of the CPU. This circuit configuration now also allows the use of slow dynamic memory or faster clock systems and thus a significant extension of the application. With the resetting of the write-in and DMA confirmation signal flip-flop FF3 by the pulse shortening circuit IVS, the signals DMA confirmation signal DACK and write signal WRCRT become further active. In addition, the low signal is the

Pulse shortening circuit IVS summarized with the reset signal RESET via the reset gate G 3 and to the

Reset input R of the bus shutdown flip-flop FF2 out, so that this reset and the bus disconnection signal BAO is inactive. This concludes a function p cycle.

Claims (1)

-1- 288 634 Claim: Circuitry for a control unit of a DMA module for screen Refr jshsteuerung with screen control for fast microprocessor systems or slow dynamic storage in real-time operation, wherein a line for a DMA request signal to a control input, the lines for a command loop cycle and a memory request signal via a clock gate to a Clock input and a line for a read signal to a reset input of a ready signal flip-flop are connected to the output of a line for a ready signal is connected and that a line for a DMA request signal with a control input and a line from the output of a ready signal flip-flop and a are connected for a command loop cycle via a clock control gate to a control input of a bus shut-off flip-flop, at whose output the line for the bus disconnection signal is connected, characterized in that that the L for a read signal (RD) via a pulse shortening circuit (IVS) on the one hand via a reset input (R) of a write and DMA acknowledgment signal flip-flop (FF3) and the other with the input of a reset gate JG 3) _ interconnected, whose further Eingang_an the line for a reset signal (RESET) and its output to the reset input (R) of the bus shutdown flip-flop (FF2) _ is guided and that the write-in and DJMA acknowledgment signal flip-flop (FF3) a set input (S) with the line for the Reset signal (RESET), a positive input control input JDJ, a clock input (C) to the memory request signal line (MREQ), and an output (Q) to both the DMA acknowledge and write signal line (DACK; WRCRT) as well as to a clock input (C) of a controlled memory flip-flop (FF4) for switching through the data (D0 ... D7).