DD288261A5 - MULTILAYER CONNECTING CONTACT FOR THIN AND THICK-WATER RESISTIVES - Google Patents

Abstract

With the invention a Mehrschichtanschluszkontaktierung for Duennschicht- and Dickschichtchipwiderstaende including lateral and Fuszkontakt is presented. The multilayer system consists of a high rate sputtered adhesive layer of known layers Cr, CrNi or Ti, also a high-rate sputtered seed layer of a Fe alloy of 5-1000 nm, preferably FeNi, FeCo or FeSi, which subsequent chemical-reductive deposition of NixPy- or NixBy layers of 3-5 mm catalyzed as a diffusion barrier with high deposition rate. The conclusion is a dip-coated PbSn layer of 20 mm or an electroless deposited Sn layer of 0.1-1 mm. The properties of the multi-layer contact connection meet the highest requirements for SMD components. {Thin-film and thick-film chip resistors; Mehrschichtanschluszkontaktierung; Side and foot contact; Adhesive layer; Seed layer; Fe alloy; Diffusion barrier; SMD components}

Description

For this 1 page drawings

Field of application of the invention

The invention relates to a multilayer arrangement for contacting thin-film or thick-film resistor layers, including the side and bottom contacts. The invention is applicable in the field of electrical engineering / electronics.

Characteristic of bekannton state of the art Multi-layer arrangements for contacting chip resistors are known. The type of layers used is included

related to the manufacturing process of the chip resistor. Precious metal alloy pastes, e.g. For example, AgPd will be added

Chip resistor producers (B.MURATA ERIE, NORTH AMERICA) only for low demands on the Ableglerfestigkeit

or low soldering working temperature and low soldering times used; for higher demands are galvanically deposited

Ni diffusion barrier layers with final PbSn plating layers required. Preferably, in the chip components manufactured in thin-film technology are Anschlußkontaktierung with side and Made foot contact with the high pitch sputtering process. In DD 23883A1, binary or ternary Cu alloys, e.g. CuSn, CuNiSn of 50ηην-200μΓη described. To one To ensure SMD-compliant reliable soldering of the components, the contact layer must still be soldered. Thin layers

alloy off. With thick layers there is a risk that cracks occur at the corners and edges of the components, which leads to the reduction of the adhesive strength of the contact layers and to the reduction of the reliability or rejects.

The soldered components often do not meet the high geometric tolerance requirements for the automatic Assembly. For the mentioned special ternary Cu alloys, the target costs are very high, so that a rational Manufacturing of the components is not possible. If as described also a galvanic process for the Cu alloy

should be used on the ceramic edge and for the base still selectively a conductive layer must be applied. No galvanic electrolysis is available for the special Cu alloys.

The sputtered CuNi layer of 0.5-2μηι also described in DD 214963 can not be processed by soldering. in the EP 0191538, the multilayer arrangement 200ACr, 1 to NiV by high pigtails and then 2μιτι galvanic Ni and

6μπι galvanic PbSn or Sn set forth. The etching step with concentrated HNO ₃ + 5% HCl required for the NiV is not environmentally friendly, expensive and can reduce the reliability of the chip resistors. Galvanically applied Ni is often used as a diffusion barrier on noble metal paste layers. The used layer thicknesses of 2-5 pm do not ensure the corrosion resistance and electromigration of the multilayer system used at the side edge (Turn, JC;

Owen, E.L .; Plating 1974 11, pp. 1015-1018). For the galvanic deposition process, a contact is needed, what

is expensive.

In DE 3705279A1 a 3-layer film for chip resistors is presented, which is produced by thin-film technology. He

consists of known adhesive metals, such as. B. Cr, CrNi, Ti, from a braze of Ni, NiCr, AgNi or SnNi and a:

solderable layer of Ag, PbSn or Sn, wherein the terminal electrodes are to have a C-shape.

The disadvantage is that the terminal contacts are made to dio resistance layer in etching, resulting in the reduction of Reliability of the components can lead. Although Ag as a solderable layer is the only one of the listed layers

high specific electrical conductivity, but dissolves in many commercially available brazing materials, eg. B. LSn 60, so that the

Danger of Ablegierens exists. By Ag ₂ S-foreign layer formation, the shelf life of the abdominal elements is limited. With complicated procedures, Dickschichtpastendruck, formerly reductive deposition and electrodeposition are the Multi-layer arrangements AgPd seed layer Ni _x Py-Ni-PbSn or AgPd palladium seed layer - Ni _x Py - PbSn or AgPd Paadium seed layer Ni _x P _y immersion-coated PbSn deposited (eg DD 224993).

The AgPd paste Schlcht is used only as a terminal contact to the resistive layer. The Pd seed layer catalyzes the onset of NI _X P _Y deposition. The use of the chemical-reductive process requires the additional coverage of the isolated parts of the device. The Abdecklack is also germinated with Pd, mitmetallisiert also partly, but is not adherent and must be peeled off again. This means a complex production.

Object of the invention

The aim of the invention is a multilayer arrangement which ensures the rational contacting of thin-film or thick-film resistors in chip form, including the side and bottom contacts.

Explanation of the essence of the invention The object of the invention is to provide a Mehrschichianordnung of adhesive layer, diffusion barrier and solderable layer, the

adheres to the thin film resistor layer or the thick film resistor pad layers and the substrate ceramic, which ensures reliability and corrosion resistance of the chip resistor whose solderability is the highest

Requirements of the SMD technology is sufficient and when soldering or Beloten no Ablegieren or a reduction in the Adhesive strength of the layers occurs. · According to the invention the object is achieved in that to secure the deposition of a Ni _x Py or Ni _x B _y layer as Diffusion barrier on a known prepared by high sputtering adhesive layer of Cr, CrNi or Ti a seed layer

which catalyzes the subsequent deposition of Ni _x Py or Ni _x B _y layers. 5nm-1 000nm of a Fe alloy layer are sputtered, preferably of FeNi, FeCo or FeSi

Deposition rate catalyze the beginning of the chemical-reductive deposition. The composition of the iron alloy

is 70% Fe and 30% alloy metal.

A splintered Pd seed layer would also be suitable, but the use of precious metal is due to the losses in the Sputtering system and not rational on the racks. Ni _x Py or Ni "B _y layers are excellent diffusion barriers already

at layer thicknesses of 3-5 pm. They can reliably work with PbSn solders using an organic flux

Layer thicknesses up to 20μ be soldered. When soldering the chip resistor occurs even at 260 ° C and 10s none Ablegierungserscheinung or reduction of the adhesive strength. The Mehrfachlötbarkeit is secured. In the case of high demands on the geometrical tolerances of the Chipwidersiandes can instead of Tauchlot- or Schwallotschicht of a PbSn alloy and an electroless Sn layer of 0.1-1 μιτι on the chemical-reductive Ni layer

be deposited, which is solderable without additional Beloten.

Due to the low temperatures in the deposition of the layers, the reliability of the resistive layer does not

negatively influenced.

By using the drum or bell method after the chip separation also the side edges of the chip

with the initially exposed metallic Meh'schichtsystem with the 3-5Mm strong Nl _x P _y - or Ni _x Py or Ni _x By

Layers are covered and thus protected against corrosion and, in the case of chip resistance, against electromigration. Exemplary embodiments

The solution according to the invention is set forth on the basis of the proven multi-layer terminal contacts for thick-film and thin-film chip resistors. Figure 1 shows the arrangement for the thick-film, Figure 2 for the thin-film resistor.

Embodiment 1 The Al ₂ O ₃ substrate 1 carries the RuO ₂ 2 based resistor layer and the AgPd contact layers 4, which are in the Großsubstratverband be screen printed. After covering 5 of the resistive layer and the back insulating Surfaces becomes in the stripe bandage the ceramic edge with embrace on the AgPd surface and to the base with a ca. 20nm thick CrNi adhesive layer 6 and then a 150nm thick FeNi seed layer 7 covered by sputtering high. The

The following lift process takes place in the stripe bandage. The stripes are separated into chips. The adhesion of the

Mehrcchichtanschlußkontaktierung is S 900 N / cm ² . A reliability test over 500 operating hours shows no failures. The corrosion resistance and the Electromigration resistance is detected. With the wetting balance, wetting forces> 200 10 ~ ^s N / cm ^{2 are added} Termination times of 0.7 s measured. A three-time Ablegierungstest to determine the repair soldering resistance at 235 ⁰ C (1-3min) gave a good Able greed strength. The wetting forces could still> 2G0 · 10 " ⁶ N / cm ² at wetting times between 0.5 and 0.8s

be measured.

Embodiment 2 The structure of the chip resistor corresponds to the embodiment 1 except for the resistive layer 3, the Diffusion barrier 8 and the Tauchbelotungsschicht. 9 Layer 2 in Figure 2 represents a high rate sputtered Ni-Cr-Al based alloy resistive layer. After coating a Ni _x B _y layer 8 of about 4 pm as a diffusion barrier, the coating takes place at about 0.6 pm Sn 9 Properties of the multi-layer terminal contacting correspond to the properties of the multi-layer terminal contacting

of the embodiment 1, except for the adhesive strength, which was measured at> 800 10 ~ ⁶ N / cm. The geometric ones

Tolerances of chip resistance ensure automatic assembly.

Claims (3)

1. Mehrschichtanschlußkontaktierung for thin and thick-film chip resistors on Koramikträgern, characterized in that on the hochrate sputtered 10-100 nm thick adhesive layer of chromium or a chromium alloy also applied by means of high sputtered 5-1 000nm thick catalytically active seed layer of an iron alloy and thereon chemically reductively deposited 9-5pm thick diffusion barrier layer of a Ni _x Py or Ni _x By alloy rests, in turn, followed by a weichlötbare 0.1-20pm thick electroless or galvanic or dip-deposited Sn or PbSn layer. 2. Mehrschichtanschlußkontaktierung for thin and thick-film chip resistors on ceramic substrates according to claim 1, characterized in that the iron alloy is a FeNi, FeCo or FeSi alloy z. With the compositions 70% Fe, 30% alloying metal. 3. Mehrschichtanschlußkontaktierung for thin and thick-film chip resistors on ceramic substrates according to claim 1, characterized in that the Ni _x Py or Ni _x B _y layer, the alloy contents 1-12% P and 0.1 to 5% B have.