DD282553A5 - ELECTRICALLY PROGRAMMABLE LOGICAL CIRCUIT ARRANGEMENT - Google Patents

Abstract

The invention relates to an electrically programmable logic circuit, PLA, for binary signals, which is particularly suitable for highly integrated components and is intended for use, for example, in controls with high operating speed and veraenderbaren logical functions. Considering the structure of known PLA, a dual programming point is described, consisting essentially of a memory cell with three logic state combinations and two programming transistors, which are individually activated or both ineffective as required for the PLA. By simple control the Betriebszustaende the circuit arrangement "programming" and "logical connection" can be realized. In the "Programming" operating state, the programming points are reprogrammed via the input line pairs or via an output line and an auxiliary control line. Fig. 2 {PLA; programmable logic circuitry; Control; Programming point; Double programming point; Programming transistor; Programming; Input line; Output line; Operating condition; Memory cell; State combination}

Description

Exploitation efficiency of the surface of such a large scale integrated circuit down. The special circuit complexity is therefore associated with special testing in manufacturing. With the solution described, it is possible to control each programming point independently by the control lines, so that quite nonsensical programming in PLA input fields and PLA Ausganosfeldern can occur.

A reduction of the required lines is achieved in a solution in which in an associative access memory on the same line the information to be stored and the information to be compared with it is transmitted, cf. DE-OS 31 05503, G 11 C-15/04.

Furthermore, it is known to provide a memory cell associative RAM to G ^; e provided for programming control line also to transmit the information to be processed. In addition to the controlling and controlled lines, an address for selecting the memory cell is required, cf. DE-PS 3138993, G 11 C-15/04. In the latter two solutions, one of the two controlling lines is always switched through to the programming transistors. This corresponds to a PLA programming in which one of the two programming points, which act on the same controlled term line, is active and ineffective on a controlling input line pair with mutually inverse control signals. Often, however, in a PLA, the case arises that the two programming points leading to a pair of controlling input lines and the same term line should be ineffective. However, this configuration is excluded using associative access stores.

Object of the invention

It is the object of the invention to provide a programmable logic circuit, PLA, which is freely reprogrammable with little effort, wherein the circuit structure of the PLA is substantially maintained, so that with conventional manufacturing technologies a highly integrated circuit arrangement with high yield can be realized inexpensively.

Explanation of the essence of the invention

The invention has for its object to provide a circuit arrangement with which a PLA is under the utilization of the usual lines in the input field and output field of the PLA at any time electrically programmable, with only meaningful logical functions should always be feasible.

According to the invention, this object is achieved in that in the input field, the input lines are connected via a controlled by an address line pass transistor each with an input of a three different logic state combinations accepting memory cell and that the outputs of the memory cell via a switching transistor to a Eingangsleifng the term line linking Programming transistor are connected. In the same way, in the output field, the output line and the auxiliary control line are connected via a pass transistor controlled by the address line to an input of a memory cell assuming three different logic state combinations. The outputs of the memory cell are each connected via a switching transistor to a first programming transistor which connects the term line to the output line and to a second programming transistor which connects the term line to the auxiliary control line. Via a control line, the operating states "programming" and "logic operation" are defined in the PLA, for this purpose the control line is connected via a combination of switching transistor and "riil-up" device to the term line, so that during the programming process a defined state on the term line and on the other hand, the control line is connected to a programmer which, in contrast to the logic state operating state, which requires inverse signals on the input line pairs, may, during programming, accept the input lines as independent signal levels.

With the circuit arrangement according to the invention, a double programming point is specified which consists of a memory cell with three different output signal combinations and two programming transistors. These programming transistors may both be ineffective, depending on the content of the memory cell, or only one of them may be effective. The theoretically possible but nonsensical state that both are effective is excluded by the defined control of the memory cell. Dia dual programming gives a high density of programming points per unit area. The addressing is carried out for input field and output field together by an addressing device, otherwise the known line structure of a PLA is advantageously used, cf. For example, DD-WP 216365, H03K-19/177, so that a total of a clearly structured, highly integrated, arbitrarily electrically programmable logic circuitry arises, which is particularly advantageous for use when variable controls are required, due to the high operating speed only insufficient Processors can be implemented or if special circuits are used for hardware support of fast logic simulations.

Ausführungsbeisplei

The invention and its mode of action will be explained in more detail with reference to a Ausführungsjbeispiels. Show in the accompanying drawing

1 shows an overview circuit diagram of an electrically programmable logic circuit arrangement according to the invention, FIG. 2 shows a circuit arrangement for a dual programming point in an input field, and FIG. 3 shows a circuit arrangement for a dual programming point in an output field.

1, an electrically programmable logic circuit, PLA, essentially consists of an input field with the paired input lines 21, 22, the term lines 23 arranged at right angles thereto and the dual programming points 2 and 2 provided at the crossing points between input lines 21, 22 and term lines 23 an output field with the term lines 23, arranged at right angles to the output line 25 and the auxiliary control line 26 according to DD-WP 216365, H03K-19/177, as well as provided at the crossing points between the term line 23 and output line 25 and auxiliary control line 26 dual programming points 3. Furthermore belongs to of the electrically programmable logic circuit arrangement, an input device 1 for the input line pairs 21, 22, a programming device 8 and an addressing device 9.

In the following the operation of the PLA according to the invention will be described. The two operating states "logical connection" are controlled in accordance with signal state "L" and "programming" according to signal state "H" via a first control line 20. The operating state "logical connection" marks the usual mode of operation as PLA, the operating state "programming" permitted An inverter 10 supplies a second control line 27 with a control signal inverse to the first control line 20. This control signal, in the "logic operation" state, causes the input device l to be actively connected to an input line pair 21, 22 coming from the input device 1 is supplied with mutually inverse logical signals. In order to increase the noise immunity, so-called "pul-up" devices are connected to the term lines 23, d6n output lines 25 and the auxiliary control lines, in the present example deplation transistors which generate the signal symbol "H" on these lines until through Furthermore, it is ensured that only in the operating state "logical connection" signals from the output line 25 to the auxiliary control line 26 can pass. For this purpose, the signal of the auxiliary control line 26 is fed to the gate of a first switching transistor 5, which is connected via a second switching transistor 6 to the output line 25, if the second control line 27 at the gate of the second Schs! 'Ransistors 6 the signal state "H" Has.

With the addressing device 9, all of a term line 23 associated with dual programming points for input fields and output fields 2, 3 via the address line 24, which is arranged parallel to the term line 23 and also reaches all dual programming points 2,3 selected. This is done by putting an address line 24 into the signal state "H" according to address information from the addressing device 9. The programming devices 8 are active on conductor pairs consisting of first and second input line 21, 22 or of an output line 25 and an auxiliary control line 26 is switched on as soon as the first control line 20 is in signal state "H" in accordance with the operating state "programming." Since the second control line 27 then has the signal state "L", the input devices 1 are not actively connected to the input line pairs and the first switching transistor 5 is on the auxiliary control line 26 can not influence the output line 25. In order to prevent malfunctions in the programming of the dual programming points for output fields 3, a third switching transistor 7 is provided on each term line 23, which forces the signal state ".L" on it as soon as the first control line 20 reaches the signal state "H", the operation; Fig. 2 shows the double programming point for emoongue 2, consisting essentially of the programming transistors 37,38 and the memory cell of three NOR gates 32,33,34 and from pass transistors 30,31 and switching transistors 35th In the "programming" operating state, activation of the address lines 24, which are each connected to a gate of a first and second pass transistor 30, 31, makes a connection between the first input line 21 and the output of the first via these pass transistors 30, 31 Gatters 32 and between the second input line 22 and the output of the third gate 34 made. In this state, a change in the contents of the memory cell can be made by the programming device 8 via each input line 21, 22, with the following possibilities:

First input Second input state at the output

line 21 line 22 I. gate 2. gate 3. gate

32 33 34

L L L H L

LHLLH HLHLL H »H». -

* State combination in the operating state. Programming "prohibited because after the blocking of pass transistors 30,31 Undefined states occur at the outputs of the gates 32,33,34.

As soon as the address line is set to the signal level "L", the pass transistors 30, 31 are closed and the memory cell stores the last written-in information.

In the "logic operation" operating state, the control signals which are generally inverse to each other on the input line pair 21, 22 are sent by the input device 1. Switching of the term line 23 into the signal state "L" occurs only if the programming transistor 37 at the gate of the ei the first input line 21 and at the gate of the second programming transistor 38 through the second input line 22 and at the output of the third gate 34, the signal state "H" is applied - In summary it follows that the first programming transistor 37 is effective only when the output of the first The second programming transistor 38 is only active if the output of the third gate 34 has assumed the signal state "L." If only the output of the second gate 33 has assumed the signal state "H" , is both the first and the second programming string sistors 37, 38 ineffective.

3 shows the dual programming point for output fields 3, consisting essentially of the programming transistors 47, 48 and the memory cell of three NOR gates 42, 43, 44 and of pass transistors 40, 41 and switching transistors 45, 46. The programming is carried out in the same way as in the case of the double programming point for input fields 2. After the above-described opening of the pass transistors 40, 41, the programmer 8 can change the contents of the memory cell via the output line 25 and the auxiliary control line 26, the following possibilities exist:

Auxiliary Condition at the exit 2nd gate 3.Gatter output tax I.Gatter 43 44 line 25 line 26 42 H L L L L L H L H L L L H L H - - H" H" -

"State combination in the operating state" programming "prohibited because 40.41 Undefined states occur at the outputs of the gates 42,43,44 after the blocking of the pass transistors.

As soon as the address line 24 is set in the signal state "L", the pass transistors 40, 41 are closed, and the memory cell stores the last written-in information.

In the operating state "logic operation" switching of the output line 23 in the signal state "L" only possible when a 'gate of the first programming transistor 47 through the term line 23 and at the gate of the first switching transistor 45 through the output of the first gate 42, the signal state A switching of the auxiliary control line 26 in the signal state "L" is only possible if at the gate of the second programming transistor 48 through the term line 23 and at the gate of the second switching transistor 46 through the output of the third gate 44, the signal state. H "is created.

In summary, it follows that the first programming transistor 47 is only effective when the output of the first gate 42 has the signal state "H" assumed, or the second programming transistor 48 is only effective when the output of the third gate 44, the signal state "L "has accepted. If only the output of the second gate 43 has assumed the signal state "H", both the first and the second programming transistor are inoperative.

Claims (3)

1. An electrically programmable logic circuit for binary signals with a matrix-formed input field of paired input lines and a demurrage and a matrix-shaped output field of an output line and a term line and a Hilfssteuerleitunvj, wherein the crossing points of the lines in the input field and the crossing points of the lines in the output field programming points form, characterized in that in the input field, the input lines (21, 22) via one of an address line (24) controlled pass transistor (30,31) in each case with an input of a three different logical state combinations accepting memory cell (32, 33, 34) are connected and in that the outputs of the memory cell (32,33,34) in each case via a switching transistor (35,36) to a the input line (21,22) with the term line (23) linking programming transistor (37,38) are connected and that in the same Way i In the output field, the output line (25) and the auxiliary control line (26) are each connected to an input of one of three differently via a pass transistor (40, 41) controlled by the address line (24). Logical combination of state receiving memory cells (42,43,44) are connected and that the outputs of the memory cell (42,43, 44) in each case via a switching transistor (45,46) to a the term line (23) with the output line (25) ve » knotting first programming transistor (47) and connected to a the second term (23) to the auxiliary control line (26) second programming transistor (48). 2. Electrically programmable logic circuit arrangement according to claim 1, characterized in that for the operating state "programming" a connection of a required for the differentiation of the operating states "programming" and "logic operation" first control line (20) on the one hand via a combination of Schalttra.isistor (7) and "pul-up" device to the term line (23) and on the other hand via a programming device (8) to the input line pairs (21, 22) is provided, and that a second control line (27) each having an output line ( 25) in the operating state "programming" blocking switching transistor (6) is connected. For this 3 pages drawings Field of application of the invention The invention relates to an electrically programmable logic circuit with which in the digital circuit technology logical operations between a plurality of input variables and a plurality of output variables are performed. The way in which the input variables are linked to the output variables can be prevented at any time by electrical programming. Such arrangements are known from the literature as PLA, English programmable logic array. A Pl A essentially consists of at least one input field, which is constructed in a matrix-like manner from controlled input lines and controlled term lines arranged at right angles to it, and from at least one output field that is matrix-shaped: tide term lines and ¹ ) controlled output lines arranged at right angles thereto. The input fields and output fields are interconnected by the term lines. In hard-programmed logic circuits semiconductor devices are arranged only at selected crossing points of steviernden and controlled lines depending on the logic function to be realized. However, there is a need to change the logic operations in highly integrated devices to accommodate, for example, the operation of control circuits according to the required conditions. Characteristic of the known state of the art It is well known, every crossing point of controlling unr! controlled line, referred to below as the programming point to assign a programming transistor whose working state can be influenced by the controlling line. So the programming of the PLA is realized by Φ · Λ programming transistor is either made effective and • nwirksam. This is done in the simplest case as described above by omitting the transistor in the design dtr PLA or by uninterrupting the connection of controlling to controlled line, see. DE-PS 3520003, H03K-19/177. In order to be able to reprogram a PLA at will at any time, it is known to provide a switching element at each programming point other than the required programming transistor which makes the programming transistor effective or ineffective depending on stored information, cf. EP 0116287, H 03K -19/177 and EP 0122363, H03K-19/177. In these solutions, however, it is necessary that in addition to the information memory and said switching element further additional control lines for changing the memory contents must be present. These lines are to be integrated into the matrix-like arrangements of the PLA fields and thus set the