DE19860390A1 - Programmable logic device uses logic arrays providing programmable AND plane and programmable OR plane in combination with memory or shift register cells - Google Patents

Abstract

The programmable logic device has programmable logic arrays used in combination with random-access memory or shift register cells for providing a binary Boolean function. A first array provides a programmable AND plane, a second array providing a programmable OR plane, with the line connections each containing a switch (8) and a memory element (9) for storing the switch condition. An Independent claim for a data decoding method is also included.

Description

Technical field

The invention relates to a programmable logic device (PLD) for realizing binary Boolean mappings according to the preamble of claim 1. The invention further relates to a method for decoding data which is characterized by a Boolean mapping y = f (x) with x = (x ₀ , _... , x _k-1 ) and y = (y ₀ ,..., y _n-1 ) are represented by means of a programmable logic module according to the preamble of claim 10.

State of the art

In a number of information technology systems such as the digital television, video and audio on demand or access to Databases are currently millions of times the number of decoding processes larger than the number of encoding processes. In such applications it is economical to reduce the hardware effort from decoding to Shift coding. Here procedures from logic minimization can be used advantageously for source coding.

Data from a source that is to be transmitted or stored is initially available in the form of a data string of a certain length. For the purpose of coding, this can be broken down into a series of short "words", e.g. B. with a length of a few bits, which as part of a table of values of a multidimensional binary Boolean function y = f (x) with y = (y ₀ ,..., Y _n-1 ) and x = (x ₀ ,.. ., x _k-1 ), where x _i , y _j ∈ {0.1}; 0 ≦ i ≦ k-1; 0 ≦ j ≦ n-1 can be understood and treated. An example is the following table of values with k = 4 and n = 4, which could have arisen from a 64-bit piece of data that was divided into sixteen 4-bit words. The left part of the table represents only a numbering of the words of the right part of the table in binary form.

By methods of logic minimization, which are described, for example, in DL Dietmeyer, Logic Design of Digital Systems, Allyn and Bacon, Boston 1978, e.g. For example, methods based on generalized consensus can convert such a table of values into a reduced table of values, in the example above:

The number of lines 1 can be considerably less than in the original table. But the left part of the table is indispensable become. Such a reduced table of values ideally contains the same information but less data than the original Table of values and is therefore faster to transfer or requires less Storage space. However, the data are encoded on the receiving end Form before and must be decoded before further use will. In order to be able to process a high data flow, too  thus decoders are needed that are able to turn off in the shortest possible time a large number of such reduced value tables the original Boolean functions or the relevant original data reconstruct.

This reduced value table describes the Boolean subfunctions y _j in an AND / OR representation and represents a two-stage AND / OR logic in terms of circuitry. In the example above, the following applies:

y ₂ = (x ₃ x ₂ x ₁ ) + (x₁x₀) + (x ₂ x₀)

The product / sum notation was chosen as the notation, whereby a product is implemented in terms of circuitry by an AND gate and a sum is implemented in terms of circuitry by an OR gate. In the table lines s _g = (S _{g (k-1) ..} S _g0 ); (1 ≦ g ≦ l) in the left half of the table, those input variables are marked with "1" that go directly into the AND tuples of the subfunctions as x _i . The variables marked with "0" must be negated and the sign "-"(don't care) means that this input variable is not to be taken into account in the corresponding tuple, which is also called implicit. In the right half of the table, in the column z _j = (z _ij ... Z _ij ) ^T, the implicants s _{g are marked} with "1", which are linked with OR operations to form a subfunction y _j . If a column does not contain the value "1" at any point, the corresponding function always has the value "0". In general:

The task of logic minimization is to select from the total of 3 ^k implicants those which can be used to form as many subfunctions y _j as possible with the aim of obtaining a reduced table of values of minimal length. In terms of circuitry, this means that the Boolean function can be implemented with a circuit with minimal component complexity, ie a minimum number of basic logic functional elements, such as AND and OR gates.

A further shortening of the table can often be achieved if, in addition to the subfunctions y _j , the associated negated functions y _j may also be considered. During the minimization process it is decided whether y _j or y _j is used. In the corresponding circuits, only one inverter has to be added for each negated minimized function.

Each logical function can be selected by the choice of the basic logical elements AND (AND), OR (OR), NOT (INVERT). To Boolean mappings become integrated circuits used, which from logical basic functional elements, such as AND and OR gate, in a suitable spatial arrangement or signal routing consist. The basic structure of such a circuit is therefore for everyone Similar images: The input signals are, if necessary, after a Inversion, linked in a first stage via AND gates. These product signals are in a second stage via OR gates linked with each other, if necessary the output signal is inverted.

For this reason, it is advantageous to implement more logical Functions to use a logic circuit whose principal Hardware basic structure is fixed, with the individual logical Links, however, can be selected by the user. To do this programmable logic devices (PLD) known, which is an integrated circuit consisting of matrix-like arranged basic logic functional elements, which are function-defining through application-based programming can be connected to each other. A universal basic structure for PLDs consists of a sequence of AND and OR gates, which in Form a first matrix, the AND level, and one of these downstream matrix, the OR level, are arranged. links the AND and / or the OR level are kept programmable, whereby the developer can implement any desired function. The programmable are decisive for the functionality Connections or separation points in the AND matrix (to form the Product terms) and in the OR matrix (to form the sum of the Products). Through programming, the connection of a Signal line to the respective basic functional element activated or  deactivated. The Great Electronics Workbook gives an overview of PLDs, D. Nührmann, 6th edition, 1994, Franzis-Verlag, p. 3251ff.

The currently known PLDs are used to implement a specific one logical mapping designed, e.g. B. for decoding data according to a fixed function. Using an external programming device the programmable connections are made once, e.g. B. by applying an activation / release voltage once, and thus a certain AND-OR combination of input signals implemented. This link is usually not straightforward changeable again.

In particular for fast decoding of data in the form of a Numerous reduced value tables or transferred in a comparable manner programmable logic modules are not suitable. Also not suitable are logic modules which are compared to the Readout speed can only be programmed slowly, or are designed to be rare compared to the frequency of reading to be programmed. Here is a greater flexibility of the Logic module required.

Technical task

The invention is therefore based on the object of being programmable To create a logic module for the implementation of Boolean maps, where programming is done quickly and easily and can be changed and which one in particular for fast Decoding of data in the form of reduced value tables can be used. It a logic module is to be made available in which the Programming with a reduced value table is not essential takes longer than the complete reading of the programmed Function, preferably even shorter. The logic module is intended for cyclical programming and full readout may be suitable. The The invention is also based on the object of a method for fast decoding of data using a programmable To specify logic module.  

Disclosure of the invention

The problem is solved with a programmable logic module for the realization of binary Boolean maps, consisting of a Sequence of logical basic functional elements, in particular AND and OR gates, which are in the form of a first matrix, the AND level, and one of these downstream matrix, the OR level, are arranged, where connections of signal lines to basic functional elements are programmable within the AND and / or the OR level, in that each of the possible connections of a signal line to a Basic functional element within the AND level and / or the OR Level is created through a line connection and that each of these Line connections a switch and at least one memory cell in is uniquely assigned, the switching state of the switch (open / closed) depends on the entry in the memory cell and where the Memory cells are repeatedly writable.

The basic functional elements are usually AND and OR gates technically in accordance with de Morgan's rules can be realized, for. B. in MOS technology as two-stage logic from NOR Gates with upstream and downstream inverters. The following will be AND and OR gates described, which also the hardware Realization is meant in an equivalent way.

The PLD according to the invention is a PLD which can be programmed on the AND and / or on the OR side by the combination with memory-based activated switches. The programmability of both matrices can be advantageous. According to the invention, all line connections of the input signals of the respective programmable level to the respective basic function elements are present or created. If the AND level is programmable as the first matrix, the input register of the PLD for all input signals x _i and possibly also the inverted input signals x _{i is} connected to a number of AND gates by signal lines, or this connection is possible in principle. These signal lines and thus the logical AND combination of the x _i and possibly x _i can, however, be reversibly interrupted or established individually by opening or closing the assigned switches. The latter is possible by writing a binary value ("0", "1") into the assigned memory cell. When the entry is overwritten in the memory cell, the signal linkage and the respective representation represented change even on the shortest time scales, which enables fast decoding of data.

The same applies to the programmability of the OR level. Here are preferably the basic functional elements and signal lines of the OR Level arranged in such a way that basically every logical sum Output signals of the AND level by programming Connections can be formed.

The invention has the particular advantage that the PLD designed in this way is light can be (re) programmed and used to decode data, which encodes using logic minimization techniques were.

In a preferred embodiment of the PLD according to the invention the basic functional elements transistors, e.g. B. in MOS technology or Precharge technology. The two-stage AND / OR logic can be advantageous realize as a NOT-NOR-NOR-NOT link, in particular Transistors in pseudo NMOS technology as elements of a NOR gate are suitable. The one to a basic functional element or a transistor associated switch is in this version by another Transistor formed, which with the transistor of the basic functional element in Is connected in series and the gate of which is driven by the memory cell. These control or switching transistors can be used in the manufacture of the PLDs in the same operation as the transistors of the basic function manufacture elements, which is particularly easy. The memory cells too can be easily and inexpensively inserted into the integrated circuit will.

If the left and right half of the reduced table of values in the The AND cells are loaded into the OR level, the memory cells preferably those of a shift register, because otherwise they are omitted here possible speed problems with addressing. The required entries in the memory cells are simply in the Shift register clocked. If the AND and OR levels in each case are programmable, is preferably the AND and OR levels in each case  assigned a shift register. This offers the best conditions for the use of the PLD for fast decoding. The usage dynamic shift register cells is possible if the for the complete programming takes less than the storage time.

Depending on the decoding or coding method, a PLD can also be used in which only the OR level is designed to be programmable. The The AND level should then be hard-wired so that all possible or encoded products from input signals and inverted input signals can be produced, to turn any left To be able to form table halves of reduced value tables. In this In this case, the memory cells assigned to the OR level are preferred static RAM cells.

The problem is further solved in a method for decoding data, which is represented by a Boolean mapping y = f (x) with x = (x ₀ , _... , X _k-1 ) and y = (y _0,. ., y _n-1 ) are shown, the output data to be decoded in the form of a reduced table of values (s _{g, 0} ,..., s _{g, k-1} , z _{g, 0} , _..., z _{g, n-1} ) of the Boolean function, by means of a programmable logic module, in that a re-programmable logic module is used in which the connections of signal lines within the OR level are controlled by a programmable matrix of memory cells, and that for decoding the reduced value table is loaded by entering the line entries (z _{g, 0} ,..., z _{g, n-1} ) into that line of the memory cell matrix of the OR level which corresponds to the corresponding fixed line entries (implicants) (s _{g , 0} ,..., S _{g, k-1} ) is assigned to the AND level. Implicants that do not appear in the reduced value table remain unconnected due to a RESET cycle of the memory matrix.

According to the invention, the logical sum of output signals AND level in the OR level according to the respective value table or coded data formed by the gate inputs of the OR gates controlled by means of the entries in the assigned memory cells, in particular opened or closed. After the procedure output signals of the OR level are therefore generated, which the match original data when the input signals of the PLD  are a sequence of numbers in binary form. These are, for example generated with a counter.

In order to carry out the method, the programmable logic module according to the invention advantageously use. It functions as part of a decoder base circuit, which consists of the coded or by means of logic minimization of redundancy-reduced data Original data reconstructed.

The row entries (z _{g, 0} ,..., Z _{g, n-1} ) are either assigned directly to a row of the memory cell matrix of the OR level by reading the entire right half of the table of the value table row by row into the memory cell array . This variant is advantageous for the case in which the AND level is also designed to be programmable. The memory cells of the AND level are then written line by line with the corresponding entries in the left half of the table, the implicants (s _{g, 0} ,..., S _{g, k-1} ).

Alternatively, each possible implicant (s _{g, 0} ,..., S _{g, k-1} ) is provided with an order number which, if necessary after repeated coding, is used to address the corresponding row of the memory cell matrix at the OR level. In this case, the AND level should supply all possible logical products from input signals or those that have been negated in the coding process. The PLD, in which only the OR level can be programmed, must then be used.

Examples of the invention are shown in the drawings and in described below.

Brief description of the drawings

Figure 1 is a decoder base circuit with a PLD with programmable OR level.

Figure 2 shows a decoder base circuit with a PLD with programmable AND and OR level.

FIG. 3 is an architecture reduced to decode value tables.

Fig. 1 shows a decoder base circuit with a re-programmable logic module, in which only the OR level is designed to be variable. The OR level is in the right part of the display.

The decoder base circuit essentially consists of a programmable logic module 1 , which here consists of a series of perpendicular and parallel line connections 2 , 3 , which are linked with transistors 4 , 5 to form logic basic function elements 6 , 7 . The PLD is constructed in MOS technology as two-stage logic from NOR gates 6 , 7 with upstream and downstream inverters. According to de Morgan:

Therefore, a link chain NOT - NOR - NOR - NOT to be executed from left to right corresponds to an AND / OR structure. The first gate stage of the PLD is therefore referred to as the AND level and the second as the OR level. Fig. 1 shows a CMOS PLD in pseudo-NMOS technology.

In normal PLDs, a certain reduced table of values is fixed in the circuit design, and according to this table, the transistors 4 , 5 are set in the levels and permanently installed in the IC production. According to the invention, this is the case in the circuit shown only for the AND level in the left part of the drawing; here all or combinations of input signals permitted in the coding process have been implemented and are now present at the output of the AND level, e.g. B. on the signal wire 2 . To program the OR level, the transistors 5 to be placed are connected in series with a further transistor 8 , the gate of which is driven by a memory cell 9 and which thus serves as a switch for establishing a line connection with the basic functional element 7 , ie for switching on a signal, that is applied to the corresponding signal wire 2 , to an input of the gate 7 .

Static RAM cells are used as memory cells 9 . Since the outputs of the RAM cells are permanently connected to a transistor 8 of the reprogrammable PLD, no read port and the associated circuit parts are necessary.

All permitted implicants are implemented in the AND level. For decoding, a counter generates a sequence of numbers, starting at zero, which represent the AND level in binary form as signals x ₀ ,. . ., x _k-1 can be supplied via an input register. A series of inverters 10 is provided to provide the inverted signals x _i .

A reduced table of values is loaded into the memory cells 9 for decoding. Before loading, all "memory cells" are set to "0" with a "CLEAR" signal and thus all gate connections of the OR level are deactivated. According to the order in the table, the memory cells 9 'can first be loaded on the multiplexers MUX with the information as to which outputs of the OR level are to be inverted. These memory cells 9 'are to be provided with a special address (eg "0"). The implicants appearing in the reduced value table are now addressed with their numbers p _g and the associated line z _{g (n-1)} . . . z _{g0 of} the right part of the table is registered. A line decoder is used for this purpose, which enables a line of the memory to be written to for a specific address p _g . All rows of the memory matrix that do not appear in the reduced tables contain only zeros due to the reset, these product signals therefore do not contribute to the output signal y _j . The decoded signals are read out via a counter and the right side of the complete table is generated at the outputs y _j .

The following coding method is advantageous for decoding with such a decoder: The implicants s _p permitted for the formation of the value tables are brought into an ordered order and numbered. For the coding of the reduced value table, the numbers p _{g of} the implicants and the associated second line part are used: p _g z _{g (n-1)} . . ., z _g0 . The number p _g has the binary representation p _g = (p P-1 | g.. P 0 | g). With one-dimensional functions (n = 1) it is sufficient to code the numbers. If you order the numbers of the implicants when coding the size, the start of a new table is marked by a jump in the larger-smaller relationship. The information as to which functions are subsequently to be inverted is assigned to a special number or a special number interval (preferably 0 for the subsequent circuit implementation). This special number can also be used to separate the tables and contain additional information such as the table length.

Fig. 2 shows another decoder base circuit with a re-programmable logic module, in which both the AND and the OR level are variable. This is advantageous if a method based on the following principle was used to encode the data:
The data are stored in completely reduced value tables, which were generated, for example, using a logic minimization program. Since in the left part of the table each table _element s _gi can assume three values, namely "0", "1" and "-", it makes sense to combine 3 or 5 table _elements s _{gi of} a table row into a word w | g and this word with To encode 5 or 8 bits again. Then let 1 ≦ w ≦ W, where W is the smallest whole number not less than k / 3 or k / 5. The unused words of the value set can be used for the purpose of separation or synchronization. Switching to unreduced coding is also possible and useful if no reduction in the amount of data can be achieved.

The basic decoder circuit of FIG. 2 is particularly suitable for decoding data encoded by this method. The basic principle corresponds to that from FIG. 1. Both the AND level and the OR level were made variably programmable with shift register cells 11 , 11 'and 12, respectively. First, the lines s _{g of} the left half of the reduced value table are generated from the terms w | g in a decoder, which can be implemented as an easily programmable standard PLD. These are _clocked line by line together with the elements of the right half of the table z _gj in the shift register, which here is a common shift register for the AND and OR levels. The sliding direction is characterized in FIG. 2 by the gable tip on the storage cells 11 , 11 ', 12 .

Two memory cells are logically combined into a pair in the AND level. This pair contains the information of an element s _gi and thus determines whether the input signal x _i or the inverted xi or neither of them is connected to the NOR gate in position g of the AND level. The value "0/1" in a cell pair thus corresponds to s _gi = "1" and "1/0" corresponds to s _gi = "0 '. The value" 0/0 "means s _gi =" - "(don't care) The combination "1/1" must not occur in any pair.

The shift register cells at the multiplexers below the OR level receive the information as to which partial functions have already been minimized inverted and therefore can no longer be inverted after the NOR gates of the OR level. In the arrangement of FIG. 2, this partial line is saved as the last one, and it is therefore to be placed at the end of the right half of the reduced value table. The associated separating word could, among other things, also contain the type information for the next table, since the use of unreduced data also makes sense if it is not possible to reduce the amount of data with reduced value tables.

After the reduced table of values has been inserted, the PLD now programmed is read out using a counter. This creates the right side of the complete table at the outputs y _j . The number of lines in the reprogrammable logical array must be as large as the maximum expected length of a reduced value table. If the incoming tables are shorter, the remaining rows provided on both levels remain unused. To ensure this, the contents of the shift register cells are set to "0" with a "CLEAR" signal before reading in a new table. At the AND level, the CLEAR process is primarily used to save performance. If the shift register is implemented with the opposite shift direction, the table must be shifted until the multiplexer is occupied and the excess lines must be filled with zeros. A CLEAR device can then be dispensed with.

An architecture for decoding reduced value tables is shown in FIG. 3. A parallel input data stream with a system-typical word width (e.g. n or k + n) is already assumed. A synchronization signal indicates the start of a data record at certain intervals. The type recognition in the first left block determines whether the incoming data is a reduced value table or unreduced data. The associated word widths, n for unreduced data and (k + n) for reduced value tables, are then generated when the format is created. A first demultiplexer feeds the reduced value tables to the upper path and unreduced data to the lower path, where they are initially written into FIFOs. Since the memory-based reprogrammable logical arrays cannot be written and read out at the same time, a further division using a demultiplexer is necessary for decoding the reduced value tables. A decoder base circuit using the same method (abbreviated to DBS in FIG. 3) is inserted in each of these two sub-paths. The DBS thus represents a circuit according to FIG. 1 or 2. While a decoder base circuit is read out with the aid of its counter, the memory cells of the other can be written with a reduced value table. Since reduced value tables are always shorter than the complete tables, reading out takes longer than writing. This means that after reading out one DBS element, the other DBS element can be read out immediately. Unreduced data can be found in the FIFO of the lower path. A multiplexer combines the three paths created into a data stream of word length n.

Industrial applicability

The invention can be used in many areas of data storage and High-speed data transmission in the field of data comm use pression and decompression advantageously, for example in the Source coding of the luminance and chrominance values of a pixel matrix of a possibly motion-compensated and quantized difference border picture. For k = 8 and n = 6 with a relation with a 0.25 µm CMOS technology decoding rates of over 1 Gbit / s can be expected. Will the Methods used for data transmission, it should be noted that they do not lead to a constant flow of data and therefore they especially seem suitable for asynchronous transfer modes. Except for data comm pression and decompression could use the proposed techniques and Circuits also used in encryption and decryption systems will.

Claims (19)

1. Programmable logic device (programmable logic device, PLD) for realizing binary Boolean mappings, consisting of a sequence of basic logic function elements, in particular AND and OR gates, which are in the form of a first matrix, the AND level, and a matrix connected downstream , the OR level, are arranged, connections of signal lines to the basic functional elements being programmable within the AND and / or the OR level, characterized in that each of the possible connections of a signal line to a basic functional element within the AND level and / or the OR level is created by a line connection and that each of these line connections is uniquely assigned to a switch and at least one memory cell, the switching state of the switch (open / closed) depending on the entry in the memory cell and the memory cells being repeatedly writable . 2. Programmable logic module according to claim 1, characterized, that the basic functional elements include transistors and the switch is formed by a transistor which is connected to the transistor of the Basic functional elements is connected in series and its base or gate is controlled by the memory cell. 3. Programmable logic device according to claim 2, characterized featured, that the switch is a MOS transistor. 4. Programmable logic module according to one of claims 1 to 3, characterized, that the memory cells are those of a shift register.   5. Programmable logic device according to claim 4, characterized featured, that the AND and OR levels are each programmable and the AND and OR level a shift register or a common one Shift register is assigned. 6. Programmable logic module according to one of claims 1 to 3, characterized, that the memory cells assigned to the OR level are static RAM cells are. 7. Programmable logic module according to one of the preceding claims, characterized in that the basic functional elements of the AND level are arranged and connected such that basically any logical product of input signals x _i and / or inverted input signals x _{i of} the logic module can be formed by programming the corresponding connections is. 8. Programmable logic module according to one of the preceding Claims, characterized, that the basic functional elements and signal lines of the OR level are arranged in such a way that basically every logical sum consists of Output signals of the AND level by programming Connections can be formed. 9. Programmable logic module according to one of the preceding claims, characterized in that an input register for input of input signals x _i and an inverter assigned to each input for generating the inverted signal x _{i is} provided. 10. A method for decoding data by means of a Boolean mapping y = f (x) with x = (x ₀ , _... , X _k-1 ) and y = (y ₀ ,..., Y _n-1 ) are shown, the output data to be decoded in the form of a reduced table of values (s _{g, 0} ,..., s _{g, k-1} , z _{g, 0...} , z _{g, n-1} ) with g = 1 ,. . ., l (l number of lines) of the Boolean function are present, by means of a programmable logic module, characterized in that a re-programmable logic module is used in which the connections of signal lines within the OR level are controlled by a programmable matrix of memory cells, and that the reduced value table is loaded for decoding by entering the line entries (z _{g, 0} ..., z _{g, n-1} ) into that line of the memory cell matrix of the OR level which corresponds to the corresponding line entries (implicants) ( s _{g, 0} ,..., s _{g, k-1} ). 11. The method according to claim 10, characterized in that in the AND level all or all of the logical products permitted in the generation of the reduced value tables from input signals x; and / or inverted input signals x _{i are} realized and a sequence of numbers x = (x ₀ ,..., x _k-1 ) is generated by means of a counter and fed to the inputs of the AND level as binary input signals, the resulting product signals be fed to the OR level. 12. The method according to claim 11, characterized in that each possible implicant is assigned an order number p _g , which is present instead of the implicant in the reduced value table and which is used to address a line of the memory cell matrix of the OR level assigned to the implicant. 13. The method according to claim 10, 11 or 12, characterized in that that the memory cells of the OR level with a reduced value table to the value "0" and thus all Gate connections of the OR level can be deactivated.   14. The method according to claim 10, characterized in that formation of the logical products from the input signals x _i and / or x _i in the AND level is controlled by a programmable matrix of memory cells and that the reduced value table is loaded by values that result clearly from the row entries (implicants) (s _{g, 0} ,..., s _{g, k-1} ), are entered into a row of the memory cell matrix at the AND level and the row entries (z _{g, 0} . ., z _{g, n-1} ) are entered in a row of the memory cell matrix of the OR level assigned to them. 15. The method according to claim 14, characterized in that a sequence of numbers x = (x ₀ ,..., X _k-1 ) is generated by means of a counter and is supplied to the inputs of the AND level as binary input signals. 16. The method according to claim 14 or 15, characterized in that the memory cells of the AND level and the OR level before loading with a reduced table of values to the value "0" and thus all gate connections of the AND level and OR level deactivated will. 17. The method according to claim 14, characterized in that three or five elements of the implicants (s _{g, 0} ,..., S _{g, k-1} ) are combined and binary coded and the entries in the memory cells of the AND level themselves can be determined from this coding using a decoder. 18. Method for fast decoding of redundancy-reduced data, which are in the form of reduced value tables, according to one of the Claims 10 to 17, characterized in that at least two programmable logic modules according to one of the Claims 1 to 9 are used, alternately in one of the Logic blocks a reduced value table is read in while the others are read out completely via a counter. 19. The method according to claim 18, characterized in that there is another data path for transporting unreduced data is.