DD262101A1 - CIRCUIT ARRANGEMENT FOR CLOCK MONITORING - Google Patents

Abstract

The invention relates to a circuit arrangement for monitoring a clock signal with respect to Frequenzueber- undunterschreitung and failure. The object of the invention is achieved with a retriggerable monoflop in that the clock signal to be monitored passes via the first input of a logic gate to the trigger input of the monoflop and the second input is connected via a comparator to the timer of the monoflop. With this circuit arrangement, a time window is created in which the clock pulses must each lie, so that no clock failure is signaled. Fig. 1

Description

For this 2 pages drawings

Field of application of the invention

The invention relates to a circuit arrangement for monitoring clock signals. The invention can be applied in a clock generator, wherein z. B. should be switched to a second on failure of a clock.

Characteristic of the known state of the art.

In the known state of the art, clock monitoring circuits are usually constructed so that only a failure of the clock is detected. For clock monitoring circuits that are to signal whether the clock signal to be monitored is in a certain frequency interval, a relatively high circuit complexity has hitherto been necessary. In DD-PS 241 516 a circuit is described in which the clock signal is compared with a time constant of a monoflop and a falling below a certain clock frequency is displayed. There is the disadvantage that only falls below the target frequency is displayed.

In DD-PS 243158 a circuit arrangement for monitoring the frequency of electrical pulses is presented in which the number of pulses of an additional pulse generator, which are between two pulses of the clock to be monitored, is compared with a target number. A deviation is displayed as an error. The disadvantage of this circuit is the high cost and the fact that higher frequency clocks can be difficult to monitor, because the additional pulse generator must be higher in frequency than the clock frequency.

Object of the invention

The aim of the invention is to monitor a clock signal with little circuit complexity.

Explanation of the essence of the invention

The object of the invention is to provide a circuit arrangement with which a clock signal can be monitored with regard to frequency overshoot and undershoot as well as failure, wherein the period of the clock signal is compared with a lower and an upper time constant.

According to the invention, the object of a circuit arrangement for clock monitoring with a retriggerable monoflop is achieved in that the input of a threshold voltage switch is connected to the time-determining components of the monoflop, the output of the threshold voltage switch at the first input of a logic gate is to be monitored clock at the second input of logical gate is applied and the output of the logic gate is connected to the clock input of the monoflop. In the clock monitoring circuit, the threshold voltage switch and the logic gate can advantageously be realized in a gate whose operating voltage is reduced compared to the operating voltage of the monoflop. The monoflop and the gate are advantageously circuits in CMOS technology.

The clock signal passes through the logic gate, which acts as a gate to the trigger input of the monoflop and brings this in the unstable state. The voltage at the timer thereby falls below the threshold voltage of the threshold voltage switch, and the gate formed by the logic gate closes. The voltage on the timer increases and exceeds the threshold voltage of the threshold voltage switch, whereby the gate is opened again. Clock pulses that reach the input of the logic gate before - they correspond to one too high

Clock frequency, these can not happen and thus do not trigger the monoflop. If no clock pulse arrives at the input of the logic gate until the time constant of the monoflop, the monoflop tilts into the stable state and generates at its output the signal for the loss of the clock.

embodiment

The invention will be explained below with reference to an exemplary embodiment. In the accompanying drawings shows:

Fig. 1: the schematic diagram of the circuit according to the invention for clock monitoring and Figure 2: the circuit of a fail-safe quartz clock generator.

The invention is used in the Ausführungsberspiel for the realization of a fail-safe quartz clock generator.

The circuit for clock monitoring shown in Fig. 1 consists of a grid 1, which is composed of a threshold voltage switch 11 and a logic gate 12, and the monoflop 68, whose trigger input is connected to the output of the gate 1. The operating voltage of the gate 1 is reduced against the monoflop 68. The clock pulses can only reach the trigger input of the monoflop 68 if they lie in the time interval which begins when the voltage at the connection point of the time-determining components 66 and 67 of the monoflop 68 has exceeded the threshold voltage of the threshold voltage switch 11 and ends when the monoflop 68 in FIG its steady state tilts.

Get in this time interval no clock pulses to the clock input of the clock monitoring circuit, the monostable 68 tilts to the steady state and signals at its output the failure of the clock.

The quartz clock generator according to FIG. 2 consists of a first quartz clock generator 3 and a second quartz clock generator 4, the clock monitoring circuit 6 according to the invention and a gate circuit 5. The two quartz clocks 3 and 4 serving for clock generation directly control the gates 51 and 52 of the gate circuit 5. The outputs of these gates are each connected to an input of the third gate 53 of the gate circuit 5, at whose output the generated clock signal can be picked up. The second input of the first gate 51 of the gate circuit 5 is connected to the non-inverted output and the second input of the second gate 52 of the gate circuit 5 is connected to the inverted output of the monoflop 68 of the clock monitoring circuit 6. From the non-inverted output of the monoflop 68, the first quartz clock 3 is also controlled. When the non-inverted output of the monoflop passes 68L level, the first quartz clock 3 and the first gate 51 of the gate circuit 5 are turned off, and no signal from the first quartz clock 3 can turn on

get the output of the gate circuit. .

In this case, due to the coupling of the outputs in the monoflop 68, the inverted output of the monoflop 68 applies a Η level to the second gate 52 of the gate circuit 5, and the signals of the second quartz clock 4 reach the output of the gate circuit 5.

The set input of the monoflop 68 is located in the center tap of the first RC element with a capacitor 61 and a resistor

62. The trigger input of the monoflop 68 is driven by the gate 1, whose one input is driven by the output of the first quartz clock generator 3, while the other input is applied to the connection point of the two time-determining components 66 and 67 of the monoflop 68. The operating voltage for the gate 1 is defined via a voltage divider relative to the operating voltage of the monoflop 68 is reduced. The voltage divider consists of a grounded fixed resistor 63, an adjustment controller 64, at the center tap of which the operating voltage terminal of the gate 1 is applied, and a reference element 65 which is connected in parallel to the adjustment controller 64 and between the operating voltage and the connection point of the fixed resistor 63 with the Adjustment controller 64 is located.

After switching on the operating voltage, the monoflop 68 is set across the capacitor 61 of the first RC element, and the first gate 51 of the gate circuit 5 and the first quartz clock 3 are enabled. The next H-L flank of the first quartz clock 3 trigger! via the gate 1 whose other input is in the steady state of the monoflop 68 to Η level, the monoflop 68, and the state of the outputs does not change after the transition of the set input of the monoflop 68 to Η level. The triggering of the monoflop 68 also causes the center tap of the timer of the monoflop 68 is briefly switched to L level and the voltage rises again with the time constant of this timer.

The gate 1 is thereby blocked until the level at the center tap of the timer of the monoflop 68 has reached the switching point of the gate 1. Only now can the next H-L edge of the first quartz clock 3 retrigger the monoflop 68. But this must be done before the level at the center tap of the timer of the monoflop 68 has reached the value at which the monoflop 68 tilts into the stable state, because otherwise its outputs are switched. By Nachtriggern the center tap of the timer of the monoflop 68 is pulled back to L level, and the process is repeated.

As long as the first quartz clock 3 oscillates at its nominal frequency and the switching points of the gate 1 and the monoflop 68 are set so that the HL edge of the first quartz clock 3 always in the period after the switching of the gate 1 and before tilting the monoflop 68 falls , the state of the outputs of the monoflop 68 is maintained.

The setting of the switching points is done on the one hand by changing the time constant of the timer of the monoflop 68 and on the other hand by reducing the operating voltage of the gate 1 relative to the monoflop 68. If the frequency of the first quartz clock 3, the switching of the outputs of the monoflop 68 occurs before the first quartz clock 3 can retrigger the monoflop 68. By switching over the outputs of the Moncflops 68 of the first quartz clock 3 is disabled and through the enabled second gate 52 of the gate 5 of the second Quarztäktgeber 4 to the output of the gate circuit 5 through, so that the quartz generator at the nominal frequency to the outside weiterhiningt. If the frequency of the first quartz clock generator 3 increases, the effect of the HL edge of the first quartz clock generator 3 is suppressed by the still locked gate 1, whereby the level at the center grip of the timer of the monoflop 68 continues to increase until the outputs of the monoflop 68 are switched over. which leads to switching off the first quartz clock generator 3 and to connecting the second quartz clock generator 4.

Since the first quartz clock 3 is disabled when the monoflop 68 is in its steady state, the monoflop 68 can no longer be triggered and remains in this state until a renewed L pulse is applied to the set input of the monoflop 68.

Claims (3)

-1 - ZbZ IUI claims: 1. Circuit arrangement for clock monitoring with a retriggerable monoflop, characterized by - That the input of a threshold voltage switch (11) with the time-determining components (66, 67) of the monoflop (68) is connected, - That the output of the threshold voltage switch (11) at the first input of a logic gate (12), - That the clock to be monitored at the second input of the logic gate (12) is applied and - That the output of the logic gate (12) is connected to the clock input of the monoflop (68). 2. A circuit arrangement according to claim 1, characterized in that the threshold voltage switch (H) and the logic gate (12) in a gate (1) are realized, the operating voltage relative to the operating voltage of the monoflop (68) is reduced. 3. Circuit arrangement according to claim 1 and 2, characterized in that the monoflop (68) and the gate (1) circuits in CMOS technology.