DD243600A1 - METHOD AND ARRANGEMENT FOR ADJUSTING DATA ENDING DEVICES TO DIGITAL MULTIPLEXERS - Google Patents

Abstract

The aim and object of the invention is a method and an arrangement for adapting data terminal equipment (DTE) to digital multiplexers with interfaces for codirectional, plesiochronous and / or synchronously multiplexed data channels without envelope repetition, without reception-side statistical recognition of repeated envelopes with the possibility of phase-synchronous Bytes clock output to the DEE at both ends of a data channel to create, in which there are no restrictions on the bit sequence of the data stream and the cost of the arrangement should be lower compared to the known prior art. To solve this problem, a method and an arrangement is given. The method employs multiple sampling of the 48 kHz payload data, transmission of step clock, byte clock and error correction synchronization control signals between the payload data, formation of a clocking and clock loop matching device, and phase adjustment of step and byte clocks in the clocking matching device. figure

Description

Field of application of the invention

The invention relates to a method and an arrangement for adapting data terminal devices to digital multiplexers having interfaces for codirectional, plesiochronous and / or synchronously multiplexed data channels with a bit rate of 64 kbit / s, preferably in low-channel digital radio links, with envelope formation, multiple transmission of the useful signal and error correction.

Characteristic of the known technical solutions

Data terminal equipment (DEE) to be connected to digital transmission paths must have a corresponding interface consisting of connection points for at least the following circuits of outgoing and incoming signals:

Outgoing: Transmit data and in some cases control signals for auxiliary purposes.

Incoming: Receive data, common step act for send and receive data and in some cases control signals for auxiliary purposes and common byte clock for send and receive data.

The data bit rate at this interface is usually 0.6; 1.2; 2.4; 4.8 or 9.6 kbit / s and the bit rate of the control signals always Vs the data bit rate. If the data stream is to be subdivided into successive groups of 8 bits each, then the boundaries of these groups can be marked by the mentioned byte clock, whose frequency corresponds to the data bit rates 0.075; 0.15; 0.3; 0.6 or 1.2 kHz.

For digital multiplexers, for example, for 30 channels of 64 kbit / s each, a connection for one of these channels consists of connection points for a data input, a data output, a bit clock input and output (64 kHz) and an octet clock input and output ( 8kHz).

The octet clock allows the 64 kbit / s bit stream to be divided into consecutive 8-bit groups and indicates their boundaries at the beginning and at the end of the transmission path.

For synchronous multiplexing, these 8-bit groups are identical to the bit groups of the channels in the multiplex frame, but not for plesiochronous multiplexing.

Because of the common step action for transmit and receive data at the DEE interface, the bit clocks must be 64kHz (within their tolerance limits) at the input and output of the channel at the multiplexer frequency synchronous. The frequency of the step to be delivered to the DEE is derived from this common bit clock 64kHz. Two DEE's can be interconnected via one channel of a digital multiplexing system, with an interface adaptation between the DEE and the multiplexer required at both ends.

In order to adapt DEE to digital multiplexers with the described interfaces, the following procedure is used in the known manner: On the transmission side, the user data is taken over by the DE in an adaptation arrangement, this data stream is subdivided into successive groups of 6 bits, for example, and these are formed into consecutively formed envelopes with, for example, 6 + 2) bit inserted. The two remaining bits are provided here for auxiliary purposes. Each envelope is repeated several times and given at 64kbit / s to the multiplexer. The number of repetitions depends on the user data bit rate, for example 5 times at 9.6 kbit / s.

The phase of the resulting groups with successive envelopes of the same content is independent of the transmission side, while the bit clock frequency and phase and the envelope clock phase are determined by the multiplexer at the transmitter and at the receiver end.

At the receiving end, the envelopes emitted by the multiplexer with 64kbit / s are resolved and the boundaries of the groups with successive envelopes are determined at the transmitting end of the same content. This is done by payload content comparison of envelopes at selected time intervals and evaluation thereof according to statistical principles. This is followed by an error correction within each group of consecutive envelopes having the same contents on the transmission side by payload comparison of all or a part of the associated envelopes and majority decision. Finally, the transmit-side payload data stream is retrieved by stringing together the results of the error correction and delivered to the DEE. The same procedure is followed in the opposite direction.

A disadvantage of this method, the required at both ends of a data channel effort for the realization, d. H. for the associated arrangement, for the multiple-sided delivery of each envelope to the multiplex channel on the transmission side, for the reception-side determination of the boundaries of the groups with successive envelopes of the same content by user data content comparison of envelopes and statistical evaluation and for bit group error correction. A further disadvantage is that this method with the arrangement required for its implementation is not suitable for DEE · interfaces with byte clock connection.

A further disadvantage is that this method, with the arrangement required for its implementation, is also unsuitable for plesiochron multiplexed channels.

Finally, it is disadvantageous in this method with the associated arrangement that exist because of the way the reception-side determination of the boundaries of the groups with successive Envelopen sendeseitig same content restrictions on the bit sequence of Nutzdatenstromes.

Object of the invention

The object of the invention is to provide a method for adapting data terminal devices to digital multiplexers and an arrangement for carrying out the same, in which the effort for implementation is reduced compared to that in known arrangements, which are multiplexed for DEE interfaces with byte clock connection and for plesiochron Channels is suitable and in which there are no restrictions on the bit sequence of the user data stream.

Explanation of the essence of the invention

The invention has for its object to provide a method and an arrangement for adapting data terminal equipment to digital multiplexers with interfaces for codirectionale, plesiochronous and / or synchronously multiplexed data channels without envelope repetition, without reception-side statistical recognition of repeated envelopes with the possibility of phase-synchronous byte clock output to create the DEE at both ends of a data channel.

According to the invention, this object is achieved in that each bit of the user data taken over by the DEE is repeatedly scanned at 48 kHz on the transmitting side and envelopes with (6 + 2) bits are formed. Each of these envelopes contains 6 bits of the result of said multisampling, one bit for control signals and another bit of information about the step clock and byte clock phase of the payload.

At the receiving end, the envelopes inherited from the multiplexer are resolved and the information contained therein is evaluated via the step clock phase and the byte clock phase in order to recognize the limits of the user data bits and bytes. An error correction by comparison of the contents of belonging to a payload bit, resulting by transmitting-side multiple sampling, consecutive bits from the resolved envelope and by majority decision. Takes place subsequently. In the opposite direction of transmission is proceeded in the same way.

The transmit-side bit clock frequency and phase, as well as the envelope clock phase at the first end of a data channel, are thereby optionally determined independently or by the receiver-side channel connection at the multiplexer and at the second end of this data channel by the latter.

Furthermore, the sender and DEE side step clock and byte clock phase at the first end of this data channel is determined independently, at the second end of the same on the receiving side at the Envelopen resolution information retrieved.

According to the invention, it is further provided that, in the case of plesiochronous multiplexing, the transmission-side bit clock frequency and phase and the envelope clock phase at the first end of a data channel are determined independently.

In this case, it is provided for the perfection of the method according to the invention that at the first end of a data channel, the reception-side bit clock and envelope clock phase at the channel output of the multiplexer is synchronized with the corresponding transmission-side phases.

For further perfection of the method according to the invention, it is provided that at the first end of a data channel, the step clock and byte clock phase recovered on the receiving side are synchronized with the corresponding send and at the same time DEE side phases.

In addition, it is advantageous to transmit the information about the Schrittakt- and byte clock phase between the two ends of a data channel protected against bit errors.

It is also advantageous to obtain the frequency 48 kHz by dividing a higher frequency f _A , for example, 1 536 kHz, and to periodically reset the frequency divider used for this purpose by transmission-side envelope clock signals. This makes it possible to obtain the required higher frequency f _A from a local, freely oscillating oscillator; also in the case of multiplexer-side loopback of the bit clock frequency and phase as well as the envelope clock phase.

Finally, it is advantageous to derive the clock frequency 64 kHz required at one end of a data channel and the higher frequency fα for one or jointly for several channels from a fundamental frequency generated by a freely oscillating oscillator.

An expedient arrangement for carrying out the method according to the invention for adapting data terminal devices to digital multiplexers is described in detail in the patent claims 8 to 11 and in the exemplary embodiment.

embodiment

With an embodiment shown in the drawing of an arrangement for carrying out the method described above, the invention will be explained in more detail.

An adaptation arrangement 1 connects a data terminal device (DEE) via a DEE interface 2 to a channel connection of a digital multiplexer via a channel interface 3. The adaptation arrangement 1 receives clocks 1 536 kHz, 64 kHz and 8 kHz from an external clock generator 4 oscillating, quartz-controlled oscillator. If necessary, the clock generator 4 can simultaneously supply a plurality of adaptation arrangements 1. The connected DEE can with the bit rates 0.6; 1.2; 2.4; Working at 4.8 or 9.6kbps. The channel connection of the multiplexer always uses a bit rate of 64kbit / s. The replenishment of the DEE to the channel bit rate occurs in two stages: firstly by multiple sampling of each payload bit to 48kbit / s and secondly by inserting 2 bits with overhead information between every 6 multiple sampling bits from 48kbit / s to 64kbit / s. Envelopes with (6 + 2) bits are transmitted at the channel interface whose boundaries are marked by pulse edges of an 8 kHz clock.

At the channel interface 3, a data output D1 is a 64 kHz clock output T1 for the bit clock and an 8 kHz clock output T2 for the envelope clock, a clock input DT a 64 kHz clock input TT for the bit clock and an 8 kHz clock input T2 'assigned to the envelope clock.

The input clocks are always frequency synchronized with the output clocks, but can have any phase deviations from each other.

At the DTE interface 2, the adaptation device 1 transmits a step clock S and a byte clock B to the DTE, both of which are assigned both to the transmission data T and to the reception data R. These send and receive data T, R are also referred to below as "payload data." In addition, the DTE interface 2 also contains connections for an auxiliary channel with Vs of the user data bit rate: the input "Control" C and the output "Log "I.

The byte clock frequency is always Vs of the step clock frequency. For each of the 6 circuits of the DEE interface 2, a line amplifier 5 is present in the matching arrangement 1. The circuits mentioned in the adaptation arrangement also pass through a loop circuit 6 which differs in the formation of local and remote test loops on the frontend of the data channel.

The step clock S and the byte clock B are obtained and provided by a clock center 7 in a central part Z by frequency division from 48 kHz, in which the clock frequencies can be switched according to the user data bit rate. On the transmission side S _s , the transmission data T passes through an envelope formation 8, in which each user data bit is scanned η times:

User data bit rate in kbit / s: 0.6 1.2 2.4 4.8 9.6 ·

η '80 40 20 10 5

The sampling frequency is 48kHz. The resulting 48 kbit / s bitstream is divided into groups of 6 consecutive bits and two auxiliary bits are added to each group. The resulting envelopes with (6 + 2) bits are strung together and given to the data output D1 at 64kbit / s. The first of the two bits for auxiliary purposes contains information about the state at the input "control" C, the second information about the Schrittakt- and the Bytesakt phase at the outputs "Schrittakt" S and "Bytesakt" B.

This latter information is generated at the first end of a data channel in the clock center 7 and supplied to the envelope formation 8 via a first switch S1. At the second end of a data channel, this information is supplied from an envelope resolution 9 via the appropriately set first switch S1 of the envelope formation 8. In plesiochronous multiplexing, at the first end of a data channel, the outputs of clock generator 64 for clocks 64kHz and 8kHz are connected via a second switch S2 to corresponding clock inputs of envelope formation 8, envelope resolution 9, envelope matching 10 and clock center 7. At the second end of such a data channel, said clock inputs are connected via the correspondingly set second switch S2 to the 64 kHz clock input T1 'and the 8 kHz clock input T2' of the channel interface 3.

With synchronous multiplexing exist at both ends of a data channel, the latter clock connections. At corresponding inputs of the clock center 7, the Envelopenbildung 8 and Envelopenauflösung 9 is a clock 48 kHz, which is derived in a frequency divider 11 from the output from the clock generator 4 clock at the higher frequency f _A = 1 536kHz. The frequency divider 11 is reset at 8kHz at each envelope limit. On the receiving side E ₃ , the data input DT is connected to the envelope resolution 9 via the envelope phase matching 10. In this, the incoming envelopes with (6 + 2) bits are broken down into their components and the strung together 6 bit groups with 48 kbit / s delivered to a subsequent payload data bit phase matching 12. This outputs the received data stream to a subsequent error correction 13 such that the boundaries of the groups of successive bits formed by transmission-side multiple sampling coincide in phase with the interval limits of the step act S. The error correction 13 extracts five elements from each of the now named groups, recovers a user data bit by majority decision ^ 3 from FIG. 5 and forwards it to a subsequent byte phase adaptation 14.

This possibly delays the successive Nutzdatenbits received on the input side so that at the connection "Empfahgsdaten" R, which is connected via the loop circuit 6 and the line amplifier 5 to the output of the byte phase matching 12, the byte boundaries of the user data the interval limits of the byte clock B. The payload bit phase matching 12, error correction 13 and byte phase matching 14 are connected via a control bus 15 to the clock center 7, through which they receive all the necessary clocks and control information, payload bit phase matching 12 and byte phase matching 14 obtained from shift registers settable delay elements whose setting data from the time difference between the information received on the receiving side recovered via the Schrittakt- or Bytesakt phase and the following interval boundary of the Schrittaktes S and the byte clock B are obtained.

The Envelopenauflösung 9 wins in addition to the said 6-bit groups this information introduced on the side of the state at the input "control" C and outputs this conditioned as a permanent during a byte via the loop circuit 6 and the line amplifier 5 to the terminal "Report" I from.

In addition, the envelope resolution 9 recovers the information about the step clock and byte clock phase also present at the other end of the data channel at the outputs "step clock" S and "byte clock" B located there and outputs the switch S1 to the clock center 7 urfd ,

The latter information is transmitted independently of the user data bit rate periodically at intervals of 40ms twice in succession with 0.125ms distance and evaluated in the clock center 7 only when both information and these arrive at the correct distance.

A variant of the matching arrangement 1 envisages replacing the envelope phase matching 10 by a first bridge 16 when the clocks 64 kHz and 8 kHz are looped back via the switch S2 from the receiving side E ₅ to the transmitting side S ₃ . A further variant of the adaptation arrangement 1 envisages replacing the payload phase adaptation 12 by a second bridge 17 and the byte phase adaptation by a third bridge 18 when the information about the step clock and the byte clock phase is received via the switch S1 from the receiving side E _{5 is} looped back to the transmitting side S ₈ .

Claims (11)

claims: 1. A method for adapting data terminal equipment (DTE) to digital multiplexers having interfaces for codirectional, plesiochronous and / or synchronously multiplexed data channels with a bit rate of 64 kbit / s, preferably in low-channel digital radio links, with envelope formation, multiple transmission of user data and error correction, characterized in that on the transmit side each bit of the payload data taken over by the DEE is repeatedly scanned at 48 kHz, envelopes are formed with (6 + 2) bits and delivered at 64 kbit / s to the multiplexer, each envelope 6 bits of the result of said multiple sampling Bit for control signals and another bit of information about the Schrittakt- and the Byaktakt phase of the payload contains that the receiving end, the multiplexer inherited Envelopen dissolved, the information contained therein about the Schrittakt- and the Bytesakt phase to recognize the boundaries of the payload Bits and bytes evaluated et al., an error correction is made by comparing the contents of the payload-side belonging multisampled transmission-side consecutive bits from the resolved envelopes and by majority vote that the same goes in the opposite transmission direction, and that the transmit-side bit clock frequency and phase and the envelope clock phase at the first end of a data channel optionally independent or from the receiving end channel terminal at the multiplexer and at the second end of this data channel always determined by the latter and the send and DEE side Schrittakt- and Bytesakt phase at the first end This data channel is determined independently at the second end of the same information received in the Envelope resolution on the receiving side. 2. The method according to claim 1, characterized in that in the case of plesiochronous multiplexing the transmission-side bit clock frequency and phase and the envelope clock phase at the first end of a data channel is determined independently. 3. The method according to claim 1 or 2, characterized in that at the first end of a data channel, the receiving side bit clock and envelope clock phase at the channel output of the multiplexer is synchronized with the corresponding transmitting side phases when the transmitting side bit clock frequency and phase and the envelope clock phase is independently determined. 4. The method according to any one of claims 1 to 3, characterized in that at the first end of a data channel, the receiving side recovered Schrittakt- and Bytetakt phase is synchronized with the corresponding send and at the same time DEE-sided phases. 5. The method according to any one of claims 1 to 4, characterized in that the information about the Schrittakt- and byte clock phase are transmitted protected against bit errors. 6. The method according to any one of claims 1 to 5, characterized in that the frequency 48 kHz by dividing a higher frequency f _A , for example, 1 536 kHz, won and the frequency divider used for this periodically reset by Envelopen clock edges. 7. The method according to claim 6, characterized in that the required at one end of a data channel clock frequency 64kHz and the higher frequency f _{A are derived} for one or together for several channels from a fundamental frequency generated by a free-running oscillator. 8. Arrangement for carrying out the method according to one of claims 1 to 7, characterized in that an adaptation arrangement (1) with the transmitting side (S _s ), the receiving side (E _s ), a central part (Z), a DEE interface ( 2) and a channel interface (3) and a clock generator (4) are provided, wherein the transmitting side (S ₅ ) of a series connection of a line amplifier (5), a loop circuit (6) and an envelope formation (8) between the DEE Interface (2) with the inputs "transmit data" (T) and "control" (C) on the one hand and the channel interface (3) with a 64 kHz clock output (T1), a data output (D1) and an 8 kHz clock output (T2 On the other hand, the receiving side (E _s ) of a series connection of an envelope phase matching (10), an envelope resolution (9), a Nutzdatenbit phase adjustment (12), an error correction (13), a byte phase adjustment (14), the loop circuit (6) and the line amplifier s (5) between the channel interface (3) with a 64 kHz clock input (TT), a data input (DT) and an 8 kHz clock input (T2 ') on the one hand and the DTE interface (2) with the outputs "receive data" (R) and "Report" (I) on the other hand, the central part (Z) consists of a clock center (7), a frequency divider (11), a first and a second switch (S 1, S 2), and wherein the clock generator ( 4) via the frequency divider (11) with the clock center (7), the Envelopenbildung (8) and the Envelopenauflösung (9), the clock generator (4) also or the 64kHz and 8kHz clock input (TT, T2 ') on the second switch (S2) with the clock center (7), the Envelopenbildung (8), the Envelope phase adjustment (10) and the Envelopenauflösung (9), the latter with the clock center (7), the Envelopenauflösung (9) or the clock center (7 ) via the first switch (S 1) with the Envelopenbildung (8), the clock center (7) further via a control bus (15) with the Envelopenaufl solution (9), the payload data bit phase matching (12), the error correction (13) and the byte phase matching (14), the clock center (7) also via the loop circuit (6) and the line amplifier (5) with the outputs, " Step Clock "(S) and" Byte Clock "(B) is connected. 9. Arrangement for carrying out the method according to one of claims 1 to 8, characterized in that instead of the Envelopen phase adaptation (10), a first bridge (16) is present. 10. Arrangement for carrying out the method according to one of claims 1 to 9, characterized in that instead of the useful data bit phase matching (12), a second bridge (17) is present. 11. Arrangement for carrying out the method according to one of claims 1 to 10, characterized in that instead of the byte phase adjustment (14), a third bridge (18) is present. For this 1 page drawing