DD238865A1 - ARRANGEMENT FOR ERROR DETECTION IN CABLES AND WIRING - Google Patents

Abstract

The invention finds application in all fields of electrical engineering in which cables and wiring are examined for wiring faults. With the solution according to the invention it is achieved that the checking of the wiring takes place without interruption. The errors are clear and shown only once. The arrangement not only checks the connections for correctness, but also determines the separations between the connections. All possible connections are checked and compared by means of nominal and actual wiring diagrams. By arranging the target and actual wiring in the Euler-Vennschen diagram, the missing and inadmissible connections are determined. Possible fields of application include cable and wiring testing for faults in cables, control cabinet wiring and computer feedback wiring of all kinds.

Description

Field of application of the invention

The invention relates to an arrangement for fault detection in cables and wiring. The cables or wiring to be tested consist of numerous wires that connect the contact points in accordance with the construction manual. It is possible to check back wiring of computer systems, wiring of control cabinets and the like. All occurring wiring errors are determined with this arrangement.

Characteristic of the well-known technical solutions

Known technical solutions are constructed so that during the query after each step, the cable or the wiring either with an equivalent structure, z. B. a functional wiring or a program on the states "connection" or "no connection" is compared.

If an error occurs, the tester will stop, the error will be displayed or printed and must be specified or eliminated by hand. Only after the fault has been eliminated can the test be continued. This has the disadvantage that at fault stop the test arrangement is blocked during the repair of the specimen. If all errors are printed without error stop with such a test arrangement, the same error appears in a multiple connection several times in different representation. A known arrangement, which is shown in WP-DD 127 873 stores the errors occurring when testing a connection point against all other connection points. This has the disadvantage that in this test per section only a ge wrt part of the error is detected and errors in multiple connections are shown repeatedly and each time differently.

In DE-AS 1665708 one suppression of multiple Fehiausdrucken with complete execution of all test steps is described, but without capturing all possibilities.

This has the disadvantage, if in a multiple connection, z. For example, if there is an unauthorized separation at the beginning of the test, all subsequent compounds will be printed out as missing. In the following test cycle, the missing link appears to be broken.

Known technical solutions use for the purpose of query for applying the voltage or current source to the contact points of the cable or the wiring and for sensing by means of an indicator rotary or Hebdrehwähler.

These mechanical devices have in addition to the lower reliability nor the disadvantage of extremely low switching speed.

Furthermore, MOS devices are used for interrogation, but with the disadvantage that a defined test current is not possible.

Furthermore, a known interrogation unit is constructed with bipolar complementary transistors. This arrangement, shown in WP-DD 130424, has the great disadvantage that two mutually insulated controls are necessary, which operate with different polarity of the operating voltages. In WP-DD 120302, to eliminate this drawback, a circuit has been shown that does not operate with complementary transistors and has a zero reference point for the logic. The major disadvantage of this circuit is that in the case of blocking both transistors, the base of the one transistor receives opposite potential to the operating voltage. If you want to work with higher operating voltages, additional measures (Zener diode) must be taken so that there is no breakdown of said transistor.

Object of the invention

With the solution according to the invention, the goal is achieved that all wiring errors in cables, rewiring, etc. in a complete test run unambiguously, thus each error are detected once, and are available by a corresponding log pressure for repair.

All arbitrarily occurring errors in multiple connections are thus clear and shown only once.

Furthermore, it is detected in which resistance region of a type of resistance connections exist, whether loose contacts are present and whether semiconductors (diode character) occur in connections.

The query is carried out with little circuit complexity and can be carried out with relatively high Prüfspanriungen

become. :

Explanation of the essence of the invention

The invention has the object of an arrangement for the complete testing of cables and wiring

- Wiring error (too much or too few connections)

- high-impedance and complex errors (intentional or unwanted high-resistance connections)

- loose contacts (temporary connections)

- compounds with semiconductor properties (diode character)

to develop, which is able to clearly and accurately list all errors occurring in a test run once and / or to create an actual wiring list. All connections are checked for correctness and all disconnections between the connections. Known technical solutions perform the error evaluation immediately after each query step or after small sections and are thus unable to decide whether an error in the previous step or in the section has already been issued or not. So it comes to multiple printings and unfavorable]

Representations. According to the invention, these deficiencies are eliminated in that all possible connections within a cable or

a wiring is queried and stored and only then a comparison between target and actual takes place. The error representation thus obtained gives each and every such complicated error exactly once clearly and unequivocally.

, For this purpose, the test voltage is applied to the measuring points individually using the control device either the measuring points individually turned on in an indicator circuit and reported the result of the test of the controller, or if each measuring point is assigned at least one indicator, this information is the Control supplied. The indicators act as threshold switches.

During the query of the DUT, the actual wiring is transferred as a schematic representation of the controller in a memory (actual wiring representation). Since the message "connection" must always be made by the corresponding indicator when checking the measuring point at which voltage is currently being applied, this can be used to self-test the test arrangement during the interrogation.

-3- 238 885

The schematic representation of the wiring (wiring representation) for both setpoint and actual is entered in an addressable random access memory. At least two memory areas are defined, in which each memory cell or each memory location is assigned a measuring point. All memory cells or memory locations whose associated measuring points are or should be connected via the cable or the wiring receive the same information (connection number). For this purpose, two counters are present, wherein a counter, which receives its counting clock from a clock generator, passes its count via a data port to the decoder for the control device. A data selector forwards either this counter reading or the content of the memory cell of the actual area addressed by this counter reading to a data buffer. By transferring the counter, another counter is incremented. This returns its count to both the parallel input of the aforementioned counter, as well as via another data port to the decoder for the voltage application device. If an indicator reports "connection" during the counting, the content of the data buffer is written to the currently addressed memory cell via an actual data gate.The target wiring representation can be entered into the desired range by means of a pattern or by means of the wiring list. If both memory areas agree, there is no error, and the match is checked by means of a comparator.

In the event of disagreement, during the re-counting of both counters with the aid of another comparator, a comparison of the contents of the addressed memory cells of an area with the count of the counter counting by carry out is carried out, and if coincident, the currently applied low-order address portion is placed in a circulation register and the content of the even addressed memory cell of the other area registered in another circulation register. Each transmission pulse sets a separator in both circulating registers.

Thus, after a pass in a circulation register, the actual connections and on the corresponding locations of the other circulation register the associated target connection numbers, in the subsequent passage is Soll and 1st interchanged using a cross data.

In each run, a serial compare, ·· matches the join number within a block (between two separators) to match. In the event of disagreement, the corresponding addresses stored in the circular register are sent in order of size of the numbers of the block in the other circulating register by releasing a trigger. The size comparison is done by another comparator. If there is a match, there is no output. Within the desired connection blocks and target individual connections, missing connections and interruptions occur, unwanted connections and inadmissible connections are to be determined within the actual connection blocks and actual individual connections

 The pictorial representation of the facts is possible with the help of the Euler-Vennschen diagram.

embodiment

Fig. 1: a test arrangement

Fig.2a: an actual wiring diagram

Fig.2b: a desired wiring representation

3 shows an Euler-Vennsches diagram with plotted nominal and actual wiring representation 4 shows a circuit of the controller

From the controller 1 (FIG. 1), binary signals are sent to the decoder 4 on eight lines 15, where they are decoded. With the help of the resulting 1 of 256-code on the lines 25 voltage is applied to each of the "255" measuring points 13 by the voltage application device 2 or by decoding the zero on all eight lines 15 (voltage applied measuring point) Leads 15 to zero, a transistor 16 receives a voltage via a line 25 connected to its base from the decoder 4. The transistor 16 supplies the transistor 8 via a voltage divider consisting of the resistors 9 and 10, a base current which Thus, the test voltage is applied to a measuring point 13 through the resistor 11, which serves for the test current limit.Further, binary signals are sent from the controller 1 via the lines 14 to the decoder 5 and into a 1 of 256 code With the aid of this code, a measuring point 13 is grounded via the lines 26, in the case of decoding of N ull on all eight lines 14 no measuring point 13 is connected to ground. A transistor 17 receives, if not all lines 14 Nullbeinhalten, via a connected to its base line 26 from the decoder 5, a voltage that controls it and thus turns on the connected measuring point 13 in the indicator circuit (controlling measuring point).

The indicator circuit includes one or more indicators 6,7, which are designed here as a threshold value and respond to different voltage or current values. In the example, two indicators 6, 7 are used, the threshold value of the indicator 6 being set so that only low-resistance connections are detected (low-impedance indicator). The indicator 7 has a low threshold and detects connections down to the kilo-ohm range (high-impedance indicator).

The indicators 6, 7 used in the example report to the controller 1 the flow of a specific current. For this purpose, in the indicator circuit between the test voltage source 18 and the voltage application device 2, a resistor 30 -geschaltetrXiessen voltage drop is applied to the low-impedance indicator 6 via a series resistor 31 to the Luminiszensdiode 32 of an optocoupler 33. In the high-impedance indicator 7, the voltage drop of the resistor 30 is amplified by means of a transistor 34. The resistor 37 serves the base current limit. In the collector circuit of the transistor 34, a luminance diode 32 of the optocoupler 33 is connected in series with the resistor 36. The photoelements 38 of the opto-couplers 33 are connected to the threshold switches 39 which indicate to the controller 1 "connection" or "not connection" via the signaling lines 27, 28.

The indicator circuit runs from the test voltage source via the voltage-applied measuring point, via the test object 12 and via the controlling measuring point to the test voltage source 18.

The result of the test "connection" or "not connection" shows the low-impedance indicator 6 of the controller 1 to the

Signal lines 27 and the high impedance indicator 7 on the reporting line 28 at.

In the example, the measuring points 13 are numbered decimal. The connected contact points of the test piece 12 have the same numbers. The test object can also be inspected during assembly.

Connected to the controller 1 is an addressable memory 19 with random access. The memory 19 is addressed

by means of the lines 23 for the low-order address part and the lines 24 for the high-order address part.

For error detection, the desired wiring is recorded in the memory 19 in the reserved area. This is done

by querying a pattern z. As a cable or a back wiring. It will all single connections and

Multiple connections (connection blocks) are stored. The storage can also be based on a Wiring list done. The actual wiring is in the memory by querying the device under test in the intended actual area

19 recorded.

The query begins with the first measuring point 13 in ascending order. At each measuring point 13 is individually voltage

applied (voltage-based measuring point). During the interrogation, all measuring points 13 with the same and higher numbers are switched into the indicator circuit for checking for connection (checking measuring point). The query is terminated when voltage was applied at all measuring points 13 and the last one was checked. When Äbfrage it is not necessary to control the voltage applied measuring points, since there must always be connection. In this case, the error-free work of the test arrangement is checked at the same time. During the query, the wiring representation (FIGS. 2a, 2b) is created.

Each memory cell of a designated memory area is assigned a measuring point 13, it contains eight bits and the low-order address part is equal to the number of the associated measuring point thirteenth

In all memory cells whose associated measuring points 13 have connection 12 via the test piece 12, the same information is entered, the smallest measuring point number occurring per connection (the connection number) (FIGS. 2 a, 2 b).

For individual contacts, the assigned memory cell receives its own low-order address part as information. From the wiring diagrams it can be seen which measuring points have the same information and thus a connection exists.

To realize the query is within the controller 1 of the cycle counter 61 (Figure 4) after the start with the aid of

1 (Fig. 1), which causes the counter 41 (Fig. 4) to be set to "zero" and the counter 42 to its final value. Subsequently, the cycle counter 61 releases the data ports 43, 44 and the clock of the clock generator 46 for the counter 42. Upon arrival of the first clock pulse, the counter 42 jumps to the count zero and generates a carry pulse. The pulse reaches the counter input of the counter 41 and sets there the count "one".

This information is at the parallel input of the counter 42 and simultaneously passes through the data port 43 on the lines 15th By a pulse delay stage 45, the transmission pulse is delayed to the clock input for parallel takeover

of the counter 42, which is thereby loaded with the value of the counter 41. Via the data gate 44, the count of the counter 42 reaches the lines 14 and the lines 23 and thus provides the low-order address part for the connected memory 19. The further clock pulses increase the counter 42 to the final value "255" on the

Value "2" increases and counter 42 counts from two again to the final value. After each increase of the counter 41 is after reloading this count in the counter 42 either this count or

the content of the addressed by this count memory cell of the actual memory area with the delayed carry of

Counter 42 entered into a data buffer 48. The selection takes place in the data selector 47. Is the memory cell addressed in this way

still blank, the counter reading is entered. Furthermore, after each clock pulse, the contents of the data buffer 48 are then written into the memory cell of the actual memory area just addressed by the counter 42 when "connection" is signaled by the associated indicator 6, 7 (Figure 1) this way like memory

Write lines. The query is terminated with the arrival of the carry pulse from the counter 41 to the cycle counter 61. The The test object can be removed. j If smaller test objects 12 (Fig. 1) not all measuring points 13 occupied, can shorten the test time to the free Measuring points 13 are dispensed with the voltage application and control. The controller 1 will be the unoccupied Measured points 13 communicated by in the corresponding desired wiring representation in the these measuring points 13th

associated memory cells every eight bits carry a zero as information. When the query is finished, a comparison of the SoII and actual wiring representation takes place. ~~.;

This comparison is not absolutely necessary because with a faultless test object in the subsequent evaluation no Error is found. By bypassing the evaluation can be a shortening of the test time in the case of freedom from errors

achieve. :

During the comparison, the data ports 43, 44 (FIG. 4) are blocked. By the preceding query, the counters 41,42

the counter values "zero" are counted up, counter 42 being counted up to its final value and the contents of the two being counted up by this counter

Counter 42 addressed memory locations dös target and the actual range per count by means of the comparator 49 Checked match. The comparison is with the arrival of the transmission pulse of the counter 42 on the cycle counter 61

completed. Was the comparison always positive; During the following in case of error Off

there is a faultless wiring.

Rating are the data gates 43,44 locked. A pulse "basic position" sets the counters

41.42 as described. A comparator 51 and the clock for counter 42 are enabled. The counting up takes place until the arrival of a carry pulse on the Aiksgaagjieszähler JllJisj ^ with the content of

the counter 42 addressed memory cell of the actual and later of the desired range in each case compared. For this purpose, in the first pass, the cross-data switch 50 is switched so that the data of the currently addressed memory cell of the desired range are switched through to the serial comparator 51. If the count of the counter 41 coincides with the data word applied to the comparator 51, the comparator 51 outputs a pulse representing a write command for the circulating registers 53, 54. In the circulation register 53 is the low-order address part of the memory cells currently addressed and in the

Circulation Register 54 entered the data passed through the serial comparator 52 ·,.

With the carry pulse of the counter 42 is the delimiter in the circulation register 53, the currently pending there "zero" and in the circulation register 54, the result of the serial comparator 52 via the comparison to match all data, which were switched through during a count of the counter 41 This process is also with the

-5- 233 885

Arrival of the carry pulse of the counter 41 at the cycle counter 61 is completed. Thus, in the circulation register 53 is the actual connection list and in the circulation register 54, the associated connection numbers of the desired connection blocks, individual connections and individual contacts.

The read-out of the circulating registers 53,54 is performed by a clock from the clock generator 46. In the comparator 60, it is determined whether the comparison characters preceding the data blocks signal coincidence or non-coincidence of the block numbers within the following block.

If there is a match, read and the comparator 60 disables the output gate 59. If the disagreement is announced, the block is read until the next compare sign and the smallest number is detected by the comparator 60. The comparator 60 then issues a command through its second output to the direction control inputs of the circulating registers 53, 54. This causes the data block to be read again in reverse order.

When a connection number identical to the most recently detected number occurs, the comparator 60 enables the output gate 59 and the corresponding f-point number is sent from the circulation register 53 to the output device 20 via the line 40 (Fig (Fig. 1).

Upon detection of the comparison character, a delimiter is sent to the output device 20 and the reading direction is changed again. Subsequently, the search for the next larger number takes place and the associated data is output from the reorder register 53. This is repeated until the entire block has been sent. It follows block by block and between these blocks two separators are sent. In the second pass, the data switch 50 is switched over and the process of writing to the circulation registers 53, 54 and the transmission of the data is repeated. The data output during the first pass represents the links to be dropped, the data output during the second pass represents the missing links.

Since permutations of connections within an actual multiple connection can not be determined, there is a recognizable error if actual individual connections are not identical to desired individual connections and / or each actual multiple connection is not the same reference point numbers as the corresponding desired multiple connection includes. To determine the failing connections, the desired individual and multiple connections are examined individually for the occurrence of a plurality of actual individual contacts, individual connections and / or multiple connections.

To determine the impermissible connections, the actual single and multiple connections are examined individually for the occurrence of a plurality of desired individual contacts, individual connections and / or multiple connections. In order to determine only high-resistance connections, the actual single and multiple connections obtained by high-resistance interrogation are examined individually for the occurrence of several actual single contacts, single connections and multiple connections obtained by low-resistance interrogation.

To determine the temporary connections (Wackelkontakte), the actual single and multiple connections, which had at least once during multiple queries had a connection to the occurrence of several actual single contacts, individual connections and / or multiple connections, which always had connection during several of the queries , examined. For this purpose, the examinee is shaken.

In order to determine the connections with diode character, the actual single or multiple connections are checked individually for the occurrence of several actual single contacts, individual connections and / or multiple connections obtained by oppositely polarized interrogation and vice versa. :

A pictorial representation of this fact is possible with the help of the Euler-Vennschen diagram (Figure 3). In the diagram shown here, the target connection blocks and the target individual connections are continuously surrounded, the actual connections are enclosed by dotted lines. The individual areas are identified by the respective lowest measuring point numbers equal to the information in the assigned memory cells. All target areas are checked individually, if several actual areas occur in a target area. The considered target areas are divided into partial area. If several partial areas occur, the connections to the measuring points 13 (FIG. 1) which lie in the different partial areas are missing. By checking the actual areas, the invalid connections are determined; To clarify the missing connections in connection blocks can be determined by comparing the faces with the desired connections according to the wiring list, which specific connection is missing. It is the compound whose measurement point numbers occur in different subareas. The determination of the high-impedance connections, connections with diode character and only temporary connections are analogous. ;

The faults thus described are detected by means of an output device 20 (Fig. of a printer. Furthermore, it is possible to print a wiring list by means of output device 20 from an unknown cable after being interrogated by the test arrangement

 The selection of the desired wiring and the starting of the test arrangement is carried out with the aid of an operating device 21.

Claims (5)

Invention claim: 1. Arrangement for error detection in cables and wirings consisting of digital counters, decoders, registers, a memory, a control device, an output device and one or more indicators, characterized in that a controller (1) exists within the outputs of a counter (41 ) with an input channel of a comparator (51), the parallel inputs of a counter (42) and the inputs of a data port (43) and whose outputs are connected to the lines (15), the outputs of the counter (42) with an input channel of a data selector ( 47), the input channel of a circulation register (53), the lines (23), the inputs of a data port (44) and whose outputs are connected to the lines (14), also the carry output of the counter (42) at the counter input of the counter ( 41), an input of a cycle counter (61), a control input of a serial comparator (52) and a pulse-delay stage (45) whose Output has a connection to the input of the counter (42) and that of a data buffer (48), an output of a clock generator (46) with the clock input of the counter (42) and the cycle counter (61) and this further connects to the data ports (43 , 44), the counters (41, 42), the clock generator (46), the cross-data divider (50), the comparator (51), the on-data gate (55), the actual data buffer (57), the target Data buffer (58) and to the lines (62,24), and an actual data port (55) with its output channel, an actual data buffer (57) and a target data buffer (58) with the input channels in common on the lines (22) and the input channel of the actual data port (55) to the output channel of the data buffer (48) and its input channel to the output channel of the data selector (47) and the output channel of the actual data buffer (57) with the input channel of the data selector (47), an input channel of the crossover diverter (50) and the output channel of the target data buffer s (58) is connected to another input channel of the cross-data divider (50) and connected to the input channel of the serial comparator (52), the other output channel of the cross-data divider (50) is connected to another input channel of the comparator (51) and the output channel of the serial comparator (52) is connected to the input channel of the circulating register (54) and the output channel of the circulating register (53) is connected to the input channel of an output gate (59) at whose output channel the lines (40) are connected, the output channel of the circulating register (54) is connected to the input channel of a comparator (60) whose comparison output to the control input of the output gate (59) and whose other output to the direction control input of the circulation register (53,54) are connected, further comprising an output of the clock generator (46) the read clock input of the circulation register (53,54) has connection and the output of the comparator (51) and the carry output d the counter (42) are connected to the write inputs of the circulating registers (53, 54) and the lines (27 or 28) lead to the write input of the memory (19), this control (1) via lines (14) and decoders (14). 5) with a control device (3) and via lines (15) and decoder (4) with a voltage application device (2) via lines (22,23,24) with a memory (19) and via the lines (40) with a Output devices is connected and one or more selective indicators (6,7) reporting to the controller (1) are connected. 2. Arrangement for error detection in Kabein and wiring according to item 1, characterized in that within the controller (1) of the output channel of the actual data buffer (57) is additionally connected to the input channel of the target data port (56). 3. Arrangement for fault detection in cables and wiring according to item 1, characterized in that within the control (1) of the input channel of the target data port (56) z. B. with an operating device (21) is connected as a peripheral input device. 4. Arrangement for fault detection in cables and wiring according to item 1, characterized in that within the controller (1) a comparator (49) with an input channel also on the output channel of the actual data buffer (57) and with the other input channel on the output channel of the target Data buffer (58) is connected and has a message line to the cycle counter (61). 5. Arrangement for fault detection in cables and wiring according to item 1, characterized in that the voltage application device (2) per measuring point (13) to a corresponding transistor (17) of the control device (3) complementary transistor (8), by means of which the base via a resistor (9) to the collector of a transistor (8) complementary transistor (16) is connected and that the transistor (16) is connected with its emitter at the zero potential. For this 3 pages drawings