DE4340144A1 - Copying machine copy detection and charging arrangement - Google Patents

Abstract

The arrangement for copying and charging for copies produced by a copying machine includes a meter box connected to the copying machines. The meter box contains an electromechanical counting mechanism for detecting impulses coming from the copying machines. An on/off switch for each copying machine detects the state of the machine. A PC containing a counter card and an input/output card is connected to the meter box. The count impulses detected by the counting mechanism are input to the counter card of the PC. The states of switches in the meter box are read into the PC via the input/output card.

Description

The invention relates to an arrangement for detection and Billing of copies made by copy machines.

Copy machines, or simply called copiers, included usually a continuous counter, so that each generated copies by forming the difference of an initial number, which the copier displays, and the final number after creation of the Copies on the counter of the copier can be determined. This method proves to be very confusing and time consuming for example, in copying machines set up in shops, especially when a plurality of copying machines exist are.

The invention is based, the detection of Simplify copies and their billing and at the same time the scope of services of the individual copy machines in order to be used in particular for commercial purposes Copy machines in stores monitoring and billing too secure and economical.

According to the invention for this purpose an arrangement for detecting and Billing of copies produced by copy machines and for statistical coverage of the scope of services of at least one in particular a plurality of copying machines according to the features of  Proposed claim 1.

For the realization of the invention for recording and billing produced copies is inventively a counter box with Used on the one hand to the copying machines is connected and the other with a Data processing system, in particular PC, is connected, wherein this data processing system with screen in addition with a circuit that has a counter card and a Commercially available input / output card with 48 inputs / outputs contains. According to the invention it is provided that both cards in the standard extension ports of a PC are plugged (ISA slot). For the functional use of these two Maps is a program designed as interface software referred to as. The interaction of counter box, PC with Circuit and software allows the capture of generated Copies to multiple copy machines and their settlement too simplify and enable a statistical recording of the Scope of services of one or more copy machines. The Circuit is mainly in the area of slow counting can be used, wherein the maximum limit of the count rate at about 10000 pulses per second. The efficiency However, the circuit developed according to the invention is not only limited to the field of use in copy machines. Also other applications in which, starting from several plants, products to be counted are to be counted conceivable.

Further embodiments of the invention are the characterizing Removable features of the dependent claims. Below is the Invention illustrated with reference to an embodiment and explained. This shows

Fig. 1 is a system for detecting and billing of copies produced with 6 copiers in a schematic representation;

Fig. 2 shows the schematic construction of the circuit within the PC,

Fig. 3 is a block diagram of the counter card.

First, the structure of the hardware for the system and the Functions described.

Based on the example of a possible configuration shown in Fig. 1, the basic function and structure of the invention will be explained. In the example, 6 copy machines - copiers 1 to 6 - are connected to a counter box via the impulse lines. The counter box contains switches 1 to 6 so that each copier is assigned a switch. The counter box also contains electromechanical counters, wherein also each copier is associated with an electromechanical counter. In the counter box, the pulses coming from the copiers are detected on the electromechanical counters. From this Zählerbox the counts are then fed via a suitable cable - impulse lines - in the data processing system, here PC with screen, in the connected to the PC counter card. In addition to the counter card, the PC also contains the commercially available input / output card with 48 inputs / outputs. The switching states of the switches contained in the counter box are read in via the I / O card, also located in the PC. The states of all switches are routed via the so-called enable lines from the counter box to the I / O card in the PC. Also, the copiers 1 to 6 are connected via enable lines to the switch of the counter box.

FIG. 2 schematically shows the structure of the PC with hardware and software. The PC contains the counter card, which is designed as a 24-channel counter card with 24 channels, as well as the I / O card. The two cards are linked via the interface software. This is addressed by the user via the user interface, for example, the user inputs the counter / copier number. The correct transfer to the PC and via the counter box to the copying machine takes place within the interface software.

If, for example, the switch of the copier No. 5 has the status "on", then the copying machine is unlocked and thus able to produce copies. This condition is also recognized by the I / O card in the PC. The mentioned in Fig. 2 interface software is responsible for ensuring that a readout of the corresponding electronic counter on the 24-channel counter card is avoided, as long as the switch no. 5 is in the switching state "on". Only when the switch No. 5 changes its state from "on" to "off", the associated electronic counter can be evaluated. After evaluation, the interface software will reset the electronic counter. However, the user of the circuit sees only the count result of these initialization and evaluation steps. On the screen B of the PC, he sees the user interface created by the software, which optionally provides the billing and related functions. The supplied interface software allows various user interfaces to use the 24-channel counter system.

As can be seen from the block diagram of the counter card according to FIG. 3, the counter card consists of 3 functional groups. These are the optocoupler block, the counter block - counters - and the interface to the PC electronics (decoder and data driver).

The task of the optocoupler block is to provide a galvanic Separation of the copiers and their electronics from the To enable PC electronics. To achieve this, one becomes Optocoupler module, for example, a PC849 used. Here are the counts of up to four copiers per block converted into light pulses (IR diode) in the infrared range and on a photosensitive transistor (IR transistor) directed. The transistor converts and amplifies the light signal into an electrical impulse. Through this transfer of Counting over a light range becomes the electric one (galvanic) separation of PC and copier electronics reached. Another effect is the so-called  Level adjustment of the signals by the optocouplers. This means that the pulses of the copier with, for example, 24 volts fed into the counter card and thus into the optocouplers However, the output side of the optocoupler, the Counts with a level of 5 volts to the counter blocks pass on. These are the in the input side the Optocouplers provided upstream resistors, they serve the current adjustment and current limitation for the IR diode. The The resistance to be connected is calculated as follows:

Optimal current through IR diode I _opt = 10 mA (according to manufacturer)
Pulse level of the copier U _imp = 24 volts
Voltage drop across IR diode U _{IR diode} = 5 volts
Series resistor R _before = (24-5) /0.01 (V / A) = 1900 ohms.

On the output side of the opto-couplers are the transistors via a pull-up resistor to a level of 5 volts brought. If one of the output transistors by a Counting pulse on the input side activated and thus turned on, the voltage drops across the transistor (5V) to a voltage of about 0.2-0.3 volts. This Voltage change leads to the connected counter that it decrements its internal value by the value 1.

The optocoupler outputs are connected to the 24 clock inputs (CLK) led the counter blocks.

Structure of the counter block:
On the 24-channel counter card there are 8 counter blocks of the type 82C54 (from AMD, -CMOS Programmable Interval Timer). It is a low-power CMOS device. Each of these 8 counter blocks contains three 16-bit counters and a control register for these counters. The control register is used for programming and determining the type of access to the counters. The counters are triggered by external clock pulses applied to the clock inputs (CLK). Counting occurs when the input pulses at the clock input (CLK) drop from 5 volts to less than 0.7 volts. This is called a negative edge of a signal. Since the counter modules are so-called TTL-compatible circuits, one can also speak of a change of the input signal from logic "1" to logical "0". After receipt of the negative edge, the counter decrements its current value by 1.

The count must be known before and after the count. For this purpose, an appropriate counter is provided by addressing logic of the counting block activated. Is a starting value of the Example counter no. 5 of the interface software after the Reading out saved, so can after completion of the Copying the end value are read out and over Difference of start value minus end value the sum of received impulses and thus the number of copies made be calculated. It is important to note that the counters count backwards towards 0

The counters are programmed by the interface software that they work as a 16-bit counter. This means that theirs maximum difference between the start and the end value of a Count at 2¹⁶- 1 = 65535 is. To get a 16-bit value To be able to read out must have two read accesses to this counter respectively. This is due to the 8-bit architecture of the device 82C54. Likewise, the interface software must be the building block program that, for a read access, both 8-bit registers, which together produce a 16-bit counter, in the right one Order to be read out. It represents one of the Both 8-bit counters have the Most Significant Byte (MSB) and the other 8-bit registers the Least Significant Byte (LSB) of the 16-bit counter. For a read access to a 16-bit counter First, the least significant 8-bit part (LSB) is the higher value part (MSB) read out. The count results off counter reading = 256 * MSB + LSB. This calculation is done within the interface software.

However, the read-out process is only possible if a faultless addressing of the block 82C54.  

First, the CE input of the block must be set to logical "0" (U <= 0.7 volts) are. Thus the internal registers of the Blocks addressable. The read / write access to one of three counters are initiated by address lines A0 and A1.

Only one of the 3 counters can be addressed. In the The following table shows the four possible states of the address lines connected to the counters are listed, as well as the registers thus addressed within the Counter module.

Table 1

However, since there are 8 counter modules on the counter card, must be in addition to that in the blocks Addressing logic addressing one of 3 internal counters, an external addressing and decoding logic to be installed, the addresses one of the 8 possible counter blocks.

The counter module can be connected via control connections / RD and / WR detect if it is a read or write is. When inactive, both lines are in the logical "1" state. Is it a write access, the / WR line drops to logical "0". Accordingly falls with a read access the line / RD to logical "0" level. Activation by level change from logic "1" to logical "0" is called "active low" addressing, as a Activation by the low voltage level (low level) is initiated. After completion of a write or Read access will return both lines to the state logical "1" over.  

Structure of the decoder and driver logic with a DIP switch, an address logic module, a data driver module and a decoding module:
The addressing and driver logic fulfills two tasks. One is the separation of the PC internal data bus from the data on the 24-channel counter card, the other task is to address one of the eighth counter blocks.

The decoding proceeds as follows. Through the DIP switches (DIP-SW 1-8), an address can be set under which the 24-channel counter card can be addressed. This first stage of the Comparison of created address by the PC and by the DIP switch specified address, in the further base address called, takes place in the address logic module 74LS688 (Texas Instruments). Are the PC address and the specified address identical, the output line of the 74LS688 (P = Q) is noticeable logical "0". If this state is reached, then on the one hand the data driver 74LS245 (Texas Instruments) (PIN 19) and on the other hand, the decoder module 74HCT138 (Texas Instruments) (PIN 4 + 5) activated. This building block is capable with 3 Address lines 8 outputs to decode (2³ = 8). The 8th Outputs (Y0-Y7) of the 74HCT138 are applied to the CS inputs (Chip Select PIN 21) of the counter modules 82C54 passed. It only one of the eight outputs ever drops to logic "0" (1) 8 decoding).

So to decode one of the 8 counter blocks, so must the following conditions are fulfilled:

• 1. The base address is located at the address comparator 74LS688 both 8-bit inputs. (Output / P = Q of 74LS688 = logical "0"),
• 2. The 74HCT138 device decodes one of the 8 outputs.

Example for setting the base address at the DIP switches:  

Table 2

The address comparator now requires the address lines A6-A12 represent the same value as that provided by the DIP switches generated address. The order of the address lines is due to technical reasons, but it corresponds to that in Table 2 listed switches, d. H. SW1 corresponds to the comparator 74LS688 of address line A6; the SW2 of the address line A7 etc.

Table 3

Address = 320 (2⁸ + 2⁶) = 256 + 64

This results in the following table for addressing the 8 counter blocks:
The address lines A3-A5 are connected to the 74HCT138.

Table 4

To decode a counter within a counter block, the procedure must be as follows:

• 1. Determining the counter module in which the to decoding counter is located.
• 2. Determine which of the three counters within the Counting blocks should be addressed.

example 1

Wanted: address of counter 7.
Counter 7 is the first counter in block no. 3. This results according to Table 4 and Table 1: Address = 336 + 0 = 336.

Example 2

Wanted: address of counter 21:
Counter 21 is the third counter in counter module 7. Table 4 and Table 1 show: Address = 368 + 2 = 370.

The user enters only the counter / copier number (User interface). The address calculation happens within the interface software, which then responds to the decoding logic.

The second task of the decoding and driver logic is in the Separation of the data bus of the PC from the data lines of the Counter modules. This is done by the module 74LS245. This is a bidirectional data driver. He is capable 8 Data lines either in the direction A → B or from B → A to float. The data direction is controlled by the control line / IOR (Input-Output Read). Requests the computer data from the Counter card, the control line falls to logical "0" and the data driver switches in the direction of the PC data bus.

Correspondingly reversed, ie in the direction of Counter module data lines, the 74LS245 switches when data written to the counter blocks. However to be fully activated, the input must simultaneously / G (PIN1) to logic "0". This only happens when Base address is the same address, by the switching states the DIP switch is generated.  

The I / O card is the second assembly within the 24-channel counter system (see FIG. 2). The I / O card is a commercially available parallel I / O card. This card is based on the building blocks 82C55. With this block it is possible to use the 24 digital channels, each with three groups of 8, as inputs or outputs. Since there are two such devices on the card, it is possible to use 48 channels in total. In the case of the 24-channel counter system, the task of the I / O card is to read the switches present on the meter box (see Figure 1). To realize this, the digital channels of the I / O modules 82C55 must be programmed as digital inputs. This in turn realizes the interface software. The states of the switches are then passed as logical "1" for ON position and clear "0" for the OFF position to the interface software. These states then signal the switching on and off of the counting channels. This is necessary, inter alia, to prevent premature readout of the counter modules.

The link between the hardware described above with counter box and PC as well as the user software is provided by the Interface software formed, which has multiple functions Provides.

The interface software allows both a Basic initialization of the counter card as well as the digital one Entrance and exit ticket, i.w. Called I / O card, perform. Other functions are used to query the individual meter readings and the switching states at the I / O card connected switch. Likewise, functions become provided a simulation of the counter card and the Effect I / O card.

As additional functions are routines for coding and Decoding of texts available. Not hardware related Procedures are mentioned at the end of the description and their Function explained.  

In the following described routines is first the Name of the program section specified. Following this an explanation of the transfer parameters appears. Only follows the presentation of the operation of the routine.

1. INITIAL

Syntax: int INITALL (int P1)
Transfer parameter: P1 = 0 basic initialization
P1 << 0 reinitialization
Return value: no meaning.

Initall performs a basic initialization of the entire Counter system through. This initialization extends over the counter card and the I / O card. The user has the Possibility between a reinitialization and a Default initialization. If P1 equals 0, then performed a standard initialization. It is from a Record the last saved total state of the Counting system restored. It should be prevented that a broken computer system also leads to a "crash" of the meter system leads. The reinitialization will always be performed when P1 with one of 0 different Integer value is passed. This is always necessary when the meter system / computer system has been switched off electrically. After a reinitialization all counters are set to 0.

2. INITONE2

Syntax: int INITONE2 (int P1, unsigned P2)
Transfer parameter: P1 Copier number
P2 Integer with initialization offset of the copies
Return value: no meaning.

Initone 2 performs an initialization of the designated P1 Counter by. With P2, the starting value of the counter can be set. If P1 is outside the range 0-23, the  Procedure immediately ended.

Example:
Initone2. (4,0) sets the counter with the serial number 4 to 0.
Initone2 (6.248) sets counter number 6 to the starting value 248.

3. COUNTERREAD

Syntax: unsigned COUNTERREAD (int P1, unsigned * P2)
Transfer parameter: P1 Copier number
P2 pointer to unsigned integer (reference transfer)
Return value: unsigned counter reading / -1 if readout is not possible.

Counterread reads out the counter labeled P1. there the function writes the meter reading both to the meter Pointer P2 addressed variable, as well as on the stack, so that the procedure Counterread has the character of a function.

example

Unsigned Var1, Var2; // both variables of type unsigned Var1 = Counterread (3, & Var2).

After a successful call, Var1 and Var2 contain the count of counter 3 . If a counter still in operation is queried, Counterread returns the value 1. If the simulation is running, a random value is returned as counter value if the simulated counter has the same status. This value is between 2 and 502.

4. GETSTATUS

Syntax: int GETSTATUS (int P1)
Transfer parameter: P1 Copier number
Return value: int Counter status.

With the help of the function Getstatus the current status of the Counter P1 are detected. The following values can be used as Return values occur:

Status start counting -1 Status Readable 0 Status-not-yet-Initializes 1 Status Incorrect counter number 2 Status-in operation 3 Status Unknown 5

The status "status start counting" is reached when the counter for the counter from "off" to "on" changed and this condition was recognized for the first time. For subsequent status requests, as long as the switch is on "On" is the status "Status in operation" returned.

If the status is "status-readable", the counter P1 can be used once be read out. Each further status query would indicate the status Return Status Not-Initialized, if not Initone 2 is called for the counter labeled P1.

5. READPIOBIT

Syntax: int READPIOBIT (int P1)
Transfer parameter: P1 Copier number
Return value: int Switch state (On = 1, Off = 0)

The Readpiobit function determines the switch state of the Switch P1, which belongs to the counter P1. This switch P1 is connected to the I / O card. The return value can be the Take value 0 for "Off" and value 1 for "On".

The routines described below enable a simulation of the hardware. By calling a procedure, the switches and also the counters are simulated by simulation. Once this has been done, the functions and procedures described in the hardware of Figs. 1-3 may be used without having connected the corresponding counter and I / O card. The functions and procedures described there automatically detect the simulation state.

SETSIMULFLAG

Syntax: int SETSIMULFLAG (int P1)
Transfer parameters: P1 (0 = Simul. Off; << 0 Simulation On)
Return value: without meaning.

Setsimulflag receives the task, the simulation on or off. If P1 equals 0, the simulation becomes switched off, according to P1 << 0 the simulation becomes switched on. This can be done at any time even if a corresponding counter and I / O hardware exists in the computer.

SETPIOBIT

Syntax: int SEPPIOBIT (int P1, int P2)
Transfer parameter: P1 Switch number
P2 switch state (0 = off; << 0 switch = on)
Return value: without meaning

Setpiobit enables the simulation of the max. 24 switches connected to the I / O card. The states of the switches turn the simulated copiers on and off. If a copier P1 described in the copier CFG file is switched on via the Setpiobit procedure and then switched off again, a value between 2 and 502 can be returned after calling the Counterread function.
Example:
Setpiobit (12, 1): turn on copier 12
Setpiobit (12, 0): disable copier 12
Counterread (12, & Var 1): read count (reference transfer from Var 1)
Initone (12, 0): set counter 12 to counter reading = 0

The interface software may contain additional procedures but they have no influence on the hardware or their Have simulation.

Claims (13)

1. Arrangement for the collection and settlement of means Copy machines generated copies and for statistical purposes Recording the scope of services of at least one especially several copying machines with a to the Copy machines connected counter box, containing for each copying machine an electromechanical counter to Detecting the coming of the copying machines pulses and for each copying machine, an on / off switch for detecting the switching state of the copying machine and with a Data processing equipment, especially personal computers (PC), containing a counter card with x channels and one Input / output card (I / O card) with 2 x Inputs / outputs, where x is the number of connectable quantities of copy machines and where the counter box with connected to the PC by means of a cable and that of the Counter detected counts via the cable into the Counter card of PC can be fed and the counter box with the PC is connected via enable lines and the Switching states of the counter of the counter box on the Enable line can be read to the I / O card of the PC, so that on the screen of the PC the user interface and associated functions are provided. 2. Arrangement according to claim 1, characterized in that the counter card a Optocoupler block for galvanic isolation of the Copy machines and their electronics from the PC and its Electronics, a counter block (counters) with Counter blocks containing counters as well as a Control register for this counter, which is the programming of the Determining the type of access to the counters serves, and an interface to the PC electronics in the form of a  Decoder and data driver logic which performs the function of Separation of the PC-internal data bus from the data bus the counter card and one of the counter blocks has to address. 3. Arrangement according to claim 1 or 2, characterized in that the I / O card with digital Channels containing modules is equipped, the digital channels of these blocks as digital inputs are programmed so that they are on the counter box existing switches are capable of reading and over these states switch the counting channels on and off Counter card is signaled. 4. Arrangement according to claim 2, characterized in that the input side of Optocouplers resistors for current adjustment and Stromlimitierung are connected upstream. 5. Arrangement according to claim 2, characterized in that the outputs of the optocoupler on the x inputs of the counter modules of the counter card are guided. 6. Arrangement according to claim 2, characterized in that the on the counter card existing meter blocks energy-saving CMOS blocks are. 7. Arrangement according to claim 2, characterized in that the counters as 16 bit counter are programmed. 8. Arrangement according to claim 2, characterized in that only one of the several meters of a counting block by means of a Adressierlogik is activated and each one of the several counter components of the counter card by means of a  external addressing and decoding logic is addressed. 9. Arrangement according to claim 2, characterized in that the decoding and Data driver logic DIP switch, by means of which a Address under which the counter card can be addressed, is adjustable and an address created by the PC and address determined by the DIP switch by means of a as an address comparator functioning logic device are comparable, such that address lines, the form a base address, with the switch positions of DIP switches are compared. 10. Arrangement according to claim 9, characterized in that the decoding and Data driver logic includes a decoding module, the one the number of counter blocks corresponding number of Outputs has, with the outputs of the decoder on the chip select inputs of the counter modules are guided, and a bidirectional data driver block containing a number corresponding to the number of counter modules capable of bidirectionally driving data lines is. 11. Arrangement according to one of claims 1 to 10, characterized in that the initial initialization of Counter card and the digital I / O card by means of a Interface software is feasible. 12. Arrangement according to claim 11, characterized in that the query of the individual Counter readings and the switching states to the I / O card connected switch via the interface software is possible. 13. Arrangement according to claim 11, characterized in that the simulation of the counter card and the I / O card via the interface software is.