DD235763A1 - CIRCUIT ARRANGEMENT FOR THE DYNAMIC COMPRESSION OF A DIGITALLY-CODED ANALOG SIGNAL - Google Patents

Abstract

The invention relates to a circuit arrangement for dynamic compression of a digitally encoded analog signal and can be used in digital signal processing equipment, as well as signal transmission systems of radio and television signals. The aim is to improve the circuit efficiency and the associated quality of the further digital signal processing, in particular of LF signals. The invention has for its object to provide a circuit arrangement which completely replaces the analog dynamic compression of analogue low-frequency signals. According to the invention, this object is achieved in that the dynamic compression takes place following the analog / digital conversion of the analog signal in a completely digital manner. The digital dynamic compressor is either a digital filter at the output to the one digital data and the other via a digital / analog converter, the analog signal appears, or immediately associated with a digital / analog converter with downstream analog filter.

Description

For this 2 pages drawings

Field of application of the invention

The invention relates to a circuit arrangement for dynamic compression of a digitally encoded analog signal and can be used in particular in digital signal processing systems and signal transmission systems of radio and television signals.

Characteristic of the known technical solutions

Solutions for dynamic compression of a digitally encoded analogue signal are known. Such dynamic compression circuits typically operate via an intermediate stage by means of analog dynamic compressors, as shown in FIG. 1. In this case, the digital data stream is first reconverted via a digital / analogue converter and fed to an analog dynamic compressor. Subsequently, the digitization is again carried out via an analog / digital converter with optionally upstream sample & hold stage.

With the DD-PS 207796 a solution is known, which includes such a digital feedback, among other things. In this case, the output of an analog / digital converter, the digital data stream is sampled by means of a digital amplitude detector. A further downstream digital / analog converter then acts on the analog signal source and controls the gain. Since various techniques are used, such as analog technology and one or more digital standard techniques, there is the disadvantage of larger circuitry.

Furthermore, it is known to regulate the dynamic range of a digital analog signal by gain control so that its level is within a given range, since the analog / digital converter delivers inaccurate samples when exceeding this range. From DE-OS 3047447 a compression arrangement for digitally modulated signals is known, wherein the supplied analog signal is passed through a low-pass filter to a sample and hold circuit in which the signal is latched. The single sample signal occurring at the output of the sample and hold circuit is passed to the analog to digital converter. When the absolute value of the input voltage becomes large and becomes a voltage reaching the minimum or maximum voltage that can be processed by the analog-to-digital converter, the gain is changed. The result is that the absolute value of the output voltage of the amplifier circuit is reduced or changed. The output voltage of the amplifier circuit is therefore always within a predetermined voltage range, which is determined by the number of bits in the analog / digital converter. A disadvantage of this solution is the additional circuit complexity to eliminate occurring over- or under-voltages.

From DE-OS 3240175 finally an analog / digital converter is known, in which the amplitude of the input signal is measured in certain level limits, consisting of 4 counters, 4 peak detectors, a logic, a counter and an operational amplifier. About the peak detectors, the signal is detected in terms of amplitude and evaluated by the logic and the counter. In the operational amplifier then the modulation of the amplitude and the DC voltage level, according to the determined result. This circuit is relatively complex and associated difficult integration.

Purely digital and thus large-scale integrated circuit arrangements for the purpose of dynamic compression are not known.

Object of the invention

The aim of the invention is to improve the circuit efficiency and the associated quality of further digital signal processing, in particular of LF signals. Furthermore, a well integrable circuit variant to be proposed.

Explanation of the essence of the invention

The invention has for its object to provide a circuit arrangement which replaces the analog dynamic compression, in particular of analogue low-frequency signals.

According to the invention, this object is achieved in that the dynamic compression takes place in the conclusion to the analog / digital conversion of the analog signal in a completely digital manner. The digital dynamic compressor is either a digital filter at the output to the one digital data and the other via a digital / analog converter, the analog signal appears, or immediately associated with a digital / analog converter with downstream analog filter. The digital dynamic compression is carried out such that the input data on the one hand directly on the one hand and on the other hand via an inverter to a digital folding unit, and a subtractor are performed. On the output side, the digital folding unit is connected to a peak detector, consisting of a comparison circuit with a downstream counter, and a control logic. The output of the counter is fed to an input of the comparison circuit, as well as a downstream differential former and the control logic. The difference former is furthermore connected on the output side to a multiplexer. The multiplexer is assigned the control logic. The control logic is further connected to the output of the comparator, the clock divider and the counter. Counters and subtractors are clocked.

The basic principle of dynamic compression is to compress the input data in the form of k parallel bits to q bits at the output, where k is greater than q. For this purpose, the input data are initially passed on the one hand via an inverter and on the other hand directly to a digital convolution unit, with the aim of negating the data in a branch, d. H. the lower (or upper) peak values are thereby included in the evaluation. The output data of the convolution unit are fed to the first to a comparison logic, the second to a counter and the third to a control logic. The comparison logic is further connected to the output data of the counter and determines in a greater (or less) comparison the ratio of the output data of the convolution unit and that of the counter and supplies corresponding set pulses to the counter. Comparison logic and counters represent an amplitude or peak detector.

While it is important in analog dynamic compression to quickly correct the analog voltage spikes and to recharge slowly after the voltage spikes, in the digital dynamic compression solution according to the invention, a counter is set to the maximum value (or minimum value) for voltage spikes that exceed the previous value , d. H. the peak value is taken directly into the counter and counted downwards (or upwards). The type of counting depends on the previously defined state of the data. The counter always counts down in a given direction in one direction (or upwards) and can be reset to the initial state by the result of the comparison logic, whenever the output data of the convolution unit is larger (or smaller) than the output data of the counter ,

The output data of the counter are further passed to a subtractor, which determines the difference between these data and the input data of the dynamic compressor and supplies to a multiplexer. The multiplexer then switches in detail the corresponding bit on the digital output, which were previously determined by the control logic. The control logic also sets the counter and clock generation. The clock generation in turn controls the counter and the subtractor. The multiplexer consists of a plurality of AND gates, to which the data to be interconnected are always associated on the input side, but which fall from AND gate to AND gate in the order of significance of the bit (eg, 1.MSB ... 8.MSB, ..). .9.MSBusw.).

The control logic then decides in detail in evaluating the output data of the counter and the convolution unit and the set pulses, which supplies the comparison logic, which of the input data of the multiplexer are switched to the output. With each set pulse of the comparison logic, the area of the multiplexer is redefined. If the output data of the counter falls below (or exceed) a certain value by counting down (or counting up), the control logic is used to increment the multiplexer and to divide the clock, and to set the counter. The multiplexer thus selects q data lines from the r data lines (where q s r) and provides them to the output. The fully digital operation of the dynamic compressor results in a very reliable operation and a good integration possibility of the entire circuit.

version Example

The invention will be explained in more detail in the following embodiment. The accompanying drawings show:

Fig. 1: Analog dynamic compression to the prior art

Fig. 2: Complete circuit order for digital dynamic compression (variants a and b) Fig. 3: Digital dynamic compression with subtractor

Fig.4: Digital dynamic compression with divider

-3- 744 82

According to Fig. 2 a or 2 b, the solution according to the invention provides to carry out the dynamic compression completely digital. The data is first passed to the digital dynamic compressor 1. Thereafter, it is possible, according to FIG. 2a, to lead out the data via a digital filter 2 on the one hand and to convert it into an analog signal via a digital / analog converter 3, on the other hand. An integrator can be connected downstream. According to FIG. 2 b, the digital / analog conversion 3 is carried out immediately after the digital dynamic compression and subsequently the analog signal is obtained via an analog filter 4. For the actual dynamic compression according to FIG. 3, the parallel data bits D1 coming from the analog / digital converter are firstly fed, on the one hand, via an inverter 5 and, on the other hand, directly to a digital folding unit 6. This is necessary to include the lower peak values in the evaluation. The values with MSB = Low are folded into the range MSB = High around the switching point of the MSB. It comes to the negation of the data (D 1 in D1) in a branch, so that the absolute deviations from the switching point of the MSB are also detected for negative deviations. The output data D3 of the digital convolution unit 6 are firstly fed to an amplitude or peak detector, consisting of a comparison logic 8 and a counter 10, and to the control logic 12. By means of the comparison logic 8, a continuous evaluation of the output data D 3 of the folding unit 6 and of the counter 10 takes place in the result of which set pulses are delivered to the counter 10. The counter 10 is thereby always set to the current peak value and starts to count down in the clock. If the output value D2 of the counter 10 falls below the peak value, it is set to the new peak value. The output data of the counter 10 are further connected to a difference 11 and a control logic 12. The difference formation 11 serves to compare the input data D1 of the circuit arrangement with the internally generated data and to evaluate it accordingly. Since the data D2 are prepared accordingly, a simple difference formation D2-D1 (or D1 -D2) is sufficient. There is a representation of the current data in k-bit word width, which are then supplied to the multiplexer 13. The multiplexer 13 selects which data area appears at the output of the multiplexer. For this the counter output data and the folded actual data are necessary. The peak generator thus regulates what data should appear at the output by selecting the range of the multiplexer 13 by means of the control logic 12. Depending on the state of the counter 10, the multiplexer 13 is defined according to two principles:

1. Count down of counter 10 (control range of the dynamic compressor)

2. Increase the counter 10 to the new value by the control logic 12 when the multiplexer 13 switches to the next byte.

The multiplexer 13 selects q data lines from the incoming r data lines and provides them to the output. With the data D3, the area of the multiplexer 13 to be switched through is selected by the control logic 12. With each set pulse of the comparison logic 8, the area of the multiplexer 13 is reset. If the comparison data D2 falls below (or exceeds) a specific value by counting down (or counting up), the control logic 12 advances the multiplexer 13 and the clock division 9, as well as setting the counter 10.

The multiplexer 13 can be advantageously constructed of AN D-gates, which are assigned in the order of the significance of the incoming data lines corresponding bytes. The clock line also serves to clock the counter 10 according to the work area of the data D2. Accordingly, the difference former 11 is clocked by the clock processing 7.

According to Figure 4 it is possible, instead of the difference formation 11 to arrange a divider 16. The control logic 12 and the multiplexer 13 are taken over in a similar manner. The divider 16 is therefore also supplied with the input data D1 and the output data D2 of the counter 10. Furthermore, it receives the data D4 from the control logic 14 and the set bus via a code converter 15. The control logic 14 is also connected to the input data D1 and the output data D2 of the counter 10. The divider 16 forms quotients of (D2-D1) and D4 (or [D1-D2] and D4) with roundings on q. At the output of the divider 16, the data appears in q-bit word length, i. H. the multiplexer is included in this arrangement.

With the dynamic compression according to the invention can be z. For example, from 12 to 8 bit width, a compression range of approximately 24 dB and from 14 to 8 bit width will achieve a compression range of approximately 36 dB.

Claims (6)

-1- 744 82 Invention claim: 1. A circuit arrangement for dynamic compression, in particular of digitally coded low-frequency signals, characterized in that a digital dynamic compressor (1) is arranged on the output side, a digital filter (2) is associated and that the output of the digital filter (2) on the one hand with the digital output and on the other hand connected to a digital / analog converter (3). 2. A circuit arrangement for dynamic compression according to item 1, characterized in that the digital dynamic compressor (1) on the output side with a digital / analog converter (3) is connected, which in turn is connected via an analog filter (4) to the signal output. 3. circuitry for dynamic compression according to item 1 or 2, characterized in that in the digital dynamic compressor (1) the input data on the one hand directly and on the other hand via an inverter (5) to a digital folding unit (6) and a difference former (11) are guided the digital folding unit (6) is connected on the output side to a peak detector and a control logic (12), that the output of the counter (10) to an input of the comparison circuit (8) and a downstream difference former (11) and the control logic (12) is performed in that the difference former is connected on the output side to a multiplexer (13), that the multiplexer (13) is furthermore assigned the control logic (12), that the control logic (12) belongs to the clock divider (9) and the counter (10) and to the output of the Comparison circuit (8) is assigned and that the counter (10) and the subtractor (11) are clocked. 4. circuit arrangement for dynamic compression according to item 3, characterized in that the peak detector consists of a comparison circuit (8) with downstream counter (10). 5. A circuit arrangement for dynamic compression according to item 3, characterized in that instead of the difference former (11) a divider (16) is arranged, which on the input side with the input data (D 1) and the output data (D2) of the counter (10) and further via a code converter (15) is connected to the control logic (14) and the set bus, that the input of the control logic (14) with the input data (D 1) and the output data (D2) of the counter (10) is occupied and that the output of the Divider (16) is led to the digital output. 6. A dynamic compression circuit according to item 5, characterized in that the divider (16) divides the quotient of the difference between the input data (D 1) and the output data (D 2) of the counter (10) and the data (D4) from the code converter (16). 15).