DD217947B1 - CIRCUIT ARRANGEMENT FOR EVALUATING DIGITAL SIGNALS IN HALF-DIGITAL DYNAMIC COMPRESSION - Google Patents

Description

For this 2 pages drawings

Field of application of the invention

The invention relates to a circuit arrangement for evaluating digital signals in semi-digital dynamic compression using an analog / digital converter. It is used to bring analogue useful signals to the same level and replaces the analog dynamic compression. The proposed circuit arrangement can be used both for studio purposes, as well as for digital transmission links of telecommunications.

Characteristic of the known state of the art

Circuit arrangements for selective dynamic compression and dynamic expansion for digitally modulated signals are known. For this purpose, EP 0053303 describes a compander with a controlled useful signal path and a controlled branch path, in which the useful signal passes through a transmission element with a logarithmic characteristic before the division. Any dB-linear compression levels are obtained, with relatively little effort for the construction of actuators. When using an analog / digital converter, however, this technical solution brings no advantage. Without analog-to-digital conversion, the solution is equivalent to dynamic compression.

Furthermore, it is known to regulate the dynamic range of a digitized analog signal by gain control so that its level is within a given range, since the analog / digital converter delivers inaccurate samples when exceeding this range. From C E-OS 3047447 a compression arrangement for digitally modulated signals is known, in which the supplied analog signal is fed via a low-pass filter to a sample and hold circuit in which the signal is latched. The single sample signal occurring at the output of the sample and hold circuit is passed to the analog to digital converter. When the absolute value of the input voltage becomes large and becomes a voltage reaching the minimum or maximum voltage that can be processed by the analog-to-digital converter, the gain is changed. The result is that the absolute value of the output voltage of the amplification circuit is reduced or changed. The output voltage of the amplification circuit is therefore always within a predetermined voltage range, which is determined by the number of bits in the analog / digital converter. A disadvantage of this solution is the additional circuit complexity to eliminate occurring over- or under-voltages.

DE-OS 3240175 describes an analog-to-digital converter in which the amplitude of the input signal is measured in certain level limits, consisting of 4 counters, 4 peak detectors, a logic, a counter and an operational amplifier. About the peak detectors, the signal is detected in terms of amplitude and evaluated by the logic and the counter. In the operational amplifier then the modulation of the amplitude and the DC voltage level, according to the determined result. This circuit is relatively complex and associated difficult integration.

Object of the invention

The aim of the invention is to reduce the circuitry complexity in the analog / digital conversion of LF signals with constant transmission quality and to improve the circuit efficiency and the associated quality of the analog / digital conversion of LF signals.

Explanation of the essence of the invention

The invention has for its object to provide a semi-digital dynamic compression circuitry that evaluates the digitally encoded analog signals and realized at very different input levels a wide modulation range of Anaiog / digital converter.

According to the invention, this object is achieved in that the analog audio signals are first fed via an operational amplifier to an analog / digital converter. The digital outputs of this analog / digital converter are routed from the 1st MSB to the nth LSB on an AND gate, whereby the output of this AND gate is connected in parallel with one input of each downstream AND gate. The second input of these AND gates is with the 1st LSB to (n - 1). LSB occupied. The outputs of all AND gates are finally assigned to a digital / analog converter, which is connected on the output side to the operational amplifier.

In order to improve the transmission quality with a given number of quantization stages of an analog / digital converter, it is necessary to fully control this analog-to-digital converter over its entire range. For this purpose, the analog / digital converter is preceded by a dynamic compressor. The AF signal passes through an operational amplifier and a sample and hold stage on the analog / digital converter. On the one hand, the digital outputs of the Anaiog / digital converter are routed from the 1st MSB to the 1st LSB to a parallel-to-serial converter and, on the other hand, connected to an evaluation logic. The evaluation logic can be executed according to the principle of using the upper or lower analog voltage peaks. When using the upper analog voltage spikes, the digital outputs of the analog / digital converter are routed from the 1st MSB to the nth LSB on each input of an AND gate. The output of the AND gate is fed to the input of another AND gate whose second input through the (n - 1). LSB is busy. In this way, the staggering continues until the 1 .LSB. The outputs of the individual AND gates are each routed to a digital / analog converter. Depending on the assignment of the digital outputs of the Anaiog / Digital converter with High-Pepf from the 1st MSB beginning to the 1st LSB, a high level is also generated at the individual AND gates at the outputs and via the digital / analogue Weighted converter and used to control the operational amplifier. Thus, the evaluation is done digitally, but the setting itself in an analogous way. The number of variants for the control is dependent on the number of AND gates.

embodiment

The invention will be explained in more detail in the following embodiment. The accompanying drawings show:

Fig. 1: Block diagram for evaluating digital signals in semi-digital dynamic compression Fig. 2: Evaluation logic according to the first principle using the upper analog voltage peaks Fig.3: Evaluation logic according to the first principle using the lower analog voltage peaks Fig. 4: Evaluation logic after the second Principle using the upper analogue voltage spikes Fig. 5: Evaluation logic according to the second principle using the lower analogue voltage spikes Fig.6: Resistance network a) linear

b) square

According to Fig. 1, the low-frequency signal is fed to a low pass with a steep edge and a controlled operational amplifier, the output of which is externally led out for control purposes and is assigned to the other via a capacitor of a sample and hold circuit (S & H). The output of the regulated operational amplifier can also be used as the analog output of the semi-digital dynamic compressor. The low pass filter removes the nonessential high frequency components from the signal. The arrangement of a sample and hold circuit before the analog / digital converter is dependent on certain conditions and not always a requirement. Furthermore, the LF signal after the capacitor is assigned a DC level generation for improving the drive behavior of the analog / digital converter. The sample and hold circuit is subsequently connected to the analog / digital converter whose digital outputs are guided on the one hand to a parallel-to-serial converter and on the other hand to an evaluation logic. If the analog-to-digital converter is clocked, the parallel-to-serial converter is clocked at a Vk-fold frequency. When the absolute value of the input voltage becomes large and becomes a voltage reaching the minimum or maximum voltage that can be processed by the analog-to-digital converter, the gain is changed. The result is that the absolute value of the output voltage is reduced or attenuated. The output voltage of the amplifier circuit is therefore always within a predetermined voltage range, which is determined by the number of bits in the analog / digital converter. The output voltage supplied to the analog-to-digital converter undergoes quantization and encoding in the analog-to-digital converter and is converted into a digitally-modulated signal.

The evaluation logic can be realized according to two basic principles, with each principle again including two variants. The first principle is based on the series connection of either AND gates, when using the upper analog voltage peaks according to FIG. 2, or OR gates when using the lower analog voltage peaks according to Rg.3. According to FIG. 2, when the upper analog voltage spikes are used, the digital outputs of the analog / digital converter are routed from the 1st MSB to the nth LSB onto an AND gate which continues to be connected to the DATA READY output of the analog / digital input side Converter is connected. Parallel conversion of the analog / digital converter, ie an analog / digital converter without DATA READY output, eliminates this input. The output of the AND gate is connected on the one hand to a resistor network and on the other hand to the input of another AND gate whose second input to the (n - 1). LSB is busy. The output of the AND gate is in turn led on the one hand to the resistor network and on the other hand to the input of a subsequent AND gate. This arrangement is continued until the 1st LSB and allows η + 1 variants for regulation. In an analogous manner, when OR gates are used, the lower analog voltage peaks according to FIG. 3 are used. In this variant, the AND gates described with reference to FIG. 2 are replaced by OR gates, with each OR gate on the output side being connected via an inverter to the resistor network. However, the DATA READY operation must be inverted in this case or, depending on the mode of operation of the analog / digital converter. The negation of the outputs is required as work is done over the resistor network with positive voltages.

The second basic principle is based on the parallel connection of either AND gates, when using the upper analog voltage spikes according to FIG. 4, or OR gates, when using the lower analog voltage spikes according to FIG. 5. The combination of both variants of the same principle is possible, but is associated with greater effort. Referring to Fig. 4, using the upper voltage peaks, the digital outputs of the analog-to-digital converter are from 1 MSB to (n + 1). LSB is routed to an AND gate, which on the input side is still connected to the DATA READY output depending on the mode of operation of the analog / digital converter or the input is omitted when using an analog / digital converter without DATA READY output. The output of the AND gate is routed in parallel to one input each of the following AND gates whose second input is occupied by the 1.LSB to the n.LSB. This also defines the number of AND gates, but with this variant there are 2 "possibilities for realization The outputs of the AND gates, occupied from the 1st LSB to the nth LSB, are each connected to a digital / analog converter When using the lower analog voltage spikes for the evaluation according to FIG. 5, analogous to FIG. 4, the first AND gate, which runs from the 1.MSB to the (n + D .LSB is replaced by an OR-gate and all subsequent AND-gates, animated from n.LSB to 1. LSB, by NOR-gates.The DATA-READY-links must in turn be inverted and all outputs of the NOR-gate. Both basic principles are equivalent, but the second principle allows a greater variation of the regulation and, consequently, a better utilization of the analogue-to-digital converter or weighting is influenced by the digital / analog converter. This can be designed as a resistor network according to FIG. 6 linear or square, but also graded according to an e-function. The output of the digital / analog converter is fed to an integrator as a time constant. The signal is thereby shaped accordingly and used to control the operational amplifier. The solution according to the invention thus makes it possible to evaluate digital signals in the case of semi-digital dynamic compression d. h., The evaluation is done in a digital manner, while the control itself is carried out analogously. The solution is further characterized by the logic used by a good integration ability.

Claims (4)

1. Circuit arrangement for evaluating digital signals in a semi-digital dynamic compression of LF signals, the analog audio signals are fed via an operational amplifier to an analog / digital converter whose digital outputs assigned on the one hand the further digital processing and on the other hand, a digital / analog converter are, which is connected on the output side via an integrator to the second input of the operational amplifier and between the analog / digital converter an evaluation circuit is arranged, characterized in that the digital outputs of the analog / digital converter from the 1st MSB to n. LSB are led to an AND gate, that the output of the AND gate is performed in parallel on each one input of an input AND gate whose second input each with the 1st LSB to (n - 1). LSB is occupied and that the outputs of all AND gates are assigned to the digital / analog converter. 2. A circuit arrangement for evaluating digital signals in a semi-digital dynamic compression according to claim 1, characterized in that instead of the AND gate OR gates are arranged, wherein all outputs in each case an inverter is connected upstream. 3. A circuit arrangement for evaluating digital signals in a semi-digital dynamic compression according to claim 1, characterized in that the digital outputs of the analog / digital converter from the 1st MSB to (n + 1). LSB are passed to the AND gate and the second inputs of the downstream AND gate are each occupied by the n.LSB to 1.LSB. 4. A circuit arrangement for evaluating digital signals in a semi-digital dynamic compression according to claim 1 and 3, characterized in that instead of the AND gate OR gates are arranged, wherein the downstream OR gates have negated outputs.