DD217346A2 - SEMICONDUCTOR MEMORY ELEMENT WITH TWO FIELD EFFECT TRANSISTORS - Google Patents

Abstract

The invention relates to a semiconductor memory element with two field effect transistors according to patent 160 601, whose use is particularly in the field of integrated semiconductor memory for electronic computers and data processing systems. The object of the invention is to increase the reading voltage and the reading speed of the semiconductor memory element by modifying the arrangement. According to the invention, the object is achieved in that in the semiconductor memory element with two field effect transistors according to patent 160 601, the gate of the transfer transistor Tt acts as a floating gate, the source and drain electrodes of the transfer transistor on the one hand to the bit line and the other on a read control line leads and further the gate of the charging transistor TL is connected directly to the word line (corresponds to capacitance C2x) or the gate of the charging transistor TL is connected directly to the word line and, in addition, the capacitance C2 at the gate of the transfer transistor Tt is omitted (corresponds to capacitance C2x, capacitance C2 0). Fig. 2

Description

Semiconductor fuse element with two field effect transistors

Field of application of the invention

The invention relates to a semiconductor memory element with two field effect transistors according to patent 1 0 0 6Oi ',, whose use is particularly in the field of integrated semiconductor memory for electronic computers and data processing systems.

Characteristic of the known technical solutions

The semiconductor memory element with two field effect transistors described in the patent WO0416 has been described in one embodiment such that the reading of information occurs by first discharging the bit line to a low voltage level, eg (OV). After activation of the memory cell with a word line pulse in the memory state "H", the bit line is charged via the transfer transistor T, to a fraction of the operating voltage. Even with optimum dimensioning of the semiconductor memory element, reading voltages greater than 1 V can not be achieved.

Object of the invention · ..

The improvement of the semiconductor memory elements with two field effect transistors according to the patent 160 601 is directed to increase the read voltage and the read speed of the semiconductor memory element.

Explanation of the essence of the invention

The object of the invention is to increase the reading voltage and the reading speed of the semiconductor memory element by modifying the arrangement. According to the invention, the object is achieved in that, in the semiconductor memory element having two field effect transistors according to the patent, the gate of the transfer transistor T acts as a floating gate, the source and drain electrodes of the. / Transfertransistors on the one hand to the bit line and on the other hand on a read control line and continue the gate of the charging transistor T, directly to the IVortleitung (corresponds capacitance C2 ^A - »00 ~) is connected or the gate of the charging, transistor T. directly to the word line is connected and in addition the capacitance C2 at the gate of the transfer transistor T. is omitted (corresponds to capacitance C2 ^X - * * oc / capacitance C2 - O)

Working Example

The invention is intended to be closer to exemplary embodiments

be explained. - '.

The accompanying drawings show: -

Fig. 1: memory element with 2 field effect transistors and 2 capacitances ;.

Fig. 2: memory element with 2 field effect transistors and 1 capacity

Fig. 3: memory element with 2 field effect transistors

The writing takes place in the variants in Fig. 1,2,3 by a high level on the word line W, whereby the charging transistor T is turned on and the floating gate of the transfer transistor according to the level of the bit line B more or less charged (CL = " H "; Q =" L ").

The reading takes place in the solutions according to FIG. 1, 2, after the bit line B is switched to the operating voltage, Cz. IL = 5V), discharging the read control line LS (eg, U _{1 Q} = OV), and not turning on the charging transistor T by a mean voltage level on the word line W, but turning on the transfer transistor, T, if open the Floatinggate a charge CL. = "H" was saved. In this case, the bit line is discharged via the transfer transistor T to OV. Was no or just a small charge CQ =. "L") stored on the floating gate, so the bit line remains charged to the operating voltage, since then the transfer transistor T can not be turned on.

The reading takes place in the variant according to type 3, after the bit line has been pre-charged to the operating voltage (eg LL = 5V) and the read control line from a certain mean voltage level Cz-B. U = 1.5V), which is not selected. State prevents current flow through the transfer transistor T, in any case, is switched to OV. If the charge on the floating gate was large enough, CQ ₁ = "H"), so that the transfer transistor T. is turned on, the bit line is discharged. If, contrary to the charge on the floating gate small (Q '= "L"), so that the transfer transistor T, remains off, the bit line is not discharged.

Claims (1)

Erfindunqsanspruch Semiconductor memory element with two field effect transistors after
Patent 160 pounds 01 that the gates of the transfer and the
Charging transistor via the capacitors C2 ' ^v and C2 are connected to the word line, that the resulting threshold voltage
of the charging transistor between the resulting Schwellsoannunaen the transfer transistor in the "1" or "0" - is state, and that. the first drain / source electrode of the transfer transistor is connected directly to the bit line, characterized in that
the gate of the transfer transistor (T,) acts as a floating gate, the source and drain electrodes of the transfer transistor on the one hand
lead to the bit line (8) and the other on a read control line (LS) and further, the gate of the charging transistor (T.) is connected directly to the word line (corresponds capacitance C2- * oe)
or the gate of the charging transistor (T.) is connected directly to d'i, e word line (W) and in addition the capacitance (C2) at the gate of the transfer transistor (T.) is omitted (corresponds capacitance C2 ~ - * - oo, capacitance C2 - * · 0). , _ For this a sheet Zeichnunaen