DE102009053977B3 - Memory cell for use in non-volatile static random access memory circuit, comprises static random access memory storage cell for storage of information bits and non-volatile storage area - Google Patents

Abstract

The memory cell (1) comprises a static random access memory (SRAM) storage cell (2) for storage of information bits and a non-volatile storage area. Two transistors (9,10) are arranged between the SRAM storage cell and a bit line (7), where a third transistor and a fourth transistor (11,12) is arranged between the SRAM storage cell and another bit line (8). The SRAM storage cell is executed as a flip-flop storage cell.

Description

The The invention relates to a memory cell in an NV-SRAM memory circuit, consisting of an SRAM memory cell for the volatile storage of information bits and a nonvolatile memory area, which non-volatile Memory cells includes wherein the nonvolatile memory area with Control lines for storing and reading information bits (STORE, RECALL) and to delete the memory cells (ERASE) is connected, wherein the SRAM memory cell connected to a first bit line BL and a second bit line BLQ is.

storage subsystems According to the prior art usually consist of a volatile and a non-volatile one Memory area or memory block, these areas both different memory sizes than also own control and / or peripheral circuits in different voltage domains exhibit.

Both Areas communicate with each other via serial or parallel Interfaces with a bus width of up to 16 or 32 bit.

A relatively fast non-volatile Storage of the data within such a storage subsystem leads to a high power consumption and long writing times. The same applies for the process of the writeback.

Farther There is a huge amount of overhead the necessary control of the storage subsystems for the various Operating conditions, such as For example, reorganization or deletion of memory cells or Memory areas, saving information bits from the volatile in the non-volatile Memory area and restore of information bits from the nonvolatile to the volatile memory area.

For a backup fast volatile memories in non-volatile Memory according to the prior art memory such as FLASH, BBSRAM, EEPROM, MRAM, nvSRAM, or BBDRAM.

to Organization of data communication between the different memories are additional Hardware and software is required, which controls the operations "Selection", "Data transfer", "Reorganization", "Transfer" and "Reaload".

• – Geschwindigkeit für • Nichtflüchtiges Schreiben und • Nichtflüchtiges Lesen/Rücksichern • Speicher sind auf Kosten/Bit optimiert
• – Lange Bootzeiten
• – Kein automatisches Datenspeichern bei Spannungsverlust
• – Kein sofortiger Restart möglich
• – Abbruchzustand nur mit Zusatzaufwand feststellbar
• – Hoher Stromverbrauch

The previous solutions have the following disadvantages:

• - Speed for • Non-volatile write and • Non-volatile read / restore • Memory are optimized for cost / bit
• - Long boat times
• - No automatic data storage in case of power loss
• - No immediate restart possible
• - Abbruchzustand only with additional effort detectable
• - High power consumption

From the US 5,065,362 For example, an NV-SRAM memory cell is known which consists of a volatile memory area and a nonvolatile memory area. In this case, the volatile memory area is implemented in the form of an SRAM cell, wherein each SRAM cell is assigned a nonvolatile memory area consisting of 6 field effect transistors.

• • nur der Inhalt der SRAM-Zelle nicht-flüchtig gespeichert werden kann,
• • kein direkter Zugriff auf den nicht-flüchtigen Speicherbereich möglich ist,
• • beim Lesen der nicht-flüchtigen Informationen der SRAM-Inhalt überschrieben werden muss,
• • nur eine nichtflüchtige Information in die SRAM-Zelle rückgeschrieben werden kann.

The disadvantages of this prior art are that exactly one SRAM cell is assigned an nv cell pair (nv ... non volatile) and thus

• • only the content of the SRAM cell can be stored non-volatile,
• • no direct access to the non-volatile memory area is possible,
• • when reading the non-volatile information, the SRAM content needs to be overwritten,
• • only a non-volatile information can be written back to the SRAM cell.

All Accesses are made to the information about the SRAM cell itself, thus there is no direct access via a bit line on the non-volatile Storage area. This means that the information is made first the non-volatile Memory area must be transferred to the SRAM cells and can be issued subsequently.

each nv-cell pair needed 2 store and 2 recall transistors each, so there is a nv cell from 6 transistors.

additional nv cells are only over the bitlines or data buses are addressable, causing a limitation on page access leads. Block-parallel reading or writing is not possible.

additional Need nv cells its own additional Interface, wherein the corresponding access via the bit lines to a increased Power consumption and delay times leads.

The Data transfer rate is reduced because of page limitation.

From the US 6,512,694 is another non-volatile memory cell is known, which also has a non-volatile memory area, which consists of several non-volatile Speicherzel len, wherein the memory area of drive transistors is included.

• 1. V_SE2 = +High Voltage z. B. 10 V
• 2. V_SE1 = 0 V (Reduzierung Leckstrom)
• 3. V_SE3-VSE8 > V_th (programmiert, U_BS) + V_high (18A) > 4 ... 5 V
• 4. Zwischenknoten T28A1/T28A2 und T28A3 werden kapazitiv mit V_SE2 angehoben
• 5. T28A3 hat wegen 3. hohe Leckströme
• 6. T28A2 wird nicht optimal programmiert, wegen 5.
• 7. T28B3 hat wegen 3. hohe Gate-Source Spannung (18B = 0 V)
• 8. T28B3–T28B8 werden anprogrammiert
• 9. T28A1 wird wegen 2. angelöscht

Disadvantages of this solution are shown below:
Since the nonvolatile transistors 28A1, 28A2 ... 28A8 are connected directly in series, in the case of "nonprogramming" - the cell includes a logical 0 - cells of, for example, the following drive conditions are required by the cell on the page of V _SE2 :

• 1. V _SE2 = + high voltage z. B. 10V
• 2. V _SE1 = 0 V (reducing leakage current)
• 3. V _SE3-VSE8 > V _th (programmed, U _BS ) + V _high (18A)> 4 ... 5V
• 4. Intermediate nodes T28A1 / T28A2 and T28A3 are capacitively boosted with V _SE2
• 5. T28A3 has due to 3. high leakage currents
• 6. T28A2 is not optimally programmed because of 5.
• 7. T28B3 has due to 3. high gate-source voltage (18B = 0V)
• 8. T28B3-T28B8 are programmed
• 9. T28A1 is canceled because of 2nd

It During each programming process, parasitic programming takes place as well as a lightning. The resulting shifts and tolerances of the threshold voltage reduce both the Endurance parameter and the parameter Data Retention.

Farther It is disadvantageous that all VSE voltages must be inflated via pumps, which leads to an increase of power consumption leads. Furthermore have to High voltage decoder can be used in the circuit arrangement and there is a limitation of scalability.

From the US 6,414,873 is another NV-SRAM memory cell is known, which also consists of a volatile memory area and a non-volatile memory area.

On this arrangement, the meet in the US 6,512,694 described disadvantages equally.

Furthermore, in the event that, for example, the transistor T38A is a depletion transistor (depletion-type transistor, self-conducting) and T42A is not to be programmed, a control voltage of 4 V-5 V applied to V _SE1 (analogous to 3). Thus, the intermediate nodes T38A / T42A and T38A / T44A are raised. In addition, since the gate capacitances of T42A and T38A are identical, the capacitive voltage swing is <50% of the V _SE2 voltage increase, thus T42A is programmed.

Of the Invention is therefore the object of a memory cell in specify a NV-SRAM memory circuit, with which the disadvantages of Overcome the prior art become.

This object is achieved in that between the SRAM memory cell and the bit line BL a first transistor and a second transistor and between the SRAM memory cell and the bit line BLQ a third transistor and a fourth transistor is arranged, that a first center tap between the first and the second transistor and a second center tap are arranged between the third and fourth transistors, the first center tap having a plurality of first information memory bits arranged in a first information storage first nonvolatile memory cells and the second center tap with a plurality of arranged in a second series circuit negatively true bits of information storing second nonvolatile Memory cells is connected, that the last nonvolatile memory cell of the first series circuit via a first termination transistor and the last nonvolatile memory cell of the second series circuit via a second termination transistor are each connected to a potential V _recall and V _ccrecall .

The nonvolatile Memory cells of the SRAM memory cell serve to protect the stored Information bits from the SRAM memory cell in the non-volatile Memory area and for restoring the information bits from the nonvolatile memory area in the SRAM memory cell NV-SRAM memory circuit.

According to the invention each between the bit lines BL and BLQ and the SRAM cell two Field effect transistors arranged. One between these two transistors located center tap is associated with several respective non-volatile Memory cells connected to the nonvolatile memory cells in one Series connection are arranged.

Thus, it is possible to transmit information from outside the inventive arrangement via the bit lines in the SRAM cell or to transmit out of the SRAM cell via the bit lines to the outside. In these cases, both field-effect transistors are switched through (V _WLF = V _WLS = H).

Another possibility is to transmit within the arrangement information from the SRAM cell into a cell pair of the nonvolatile memory device (V _WLF = 0, V _WLS = H) or vice versa from a cell pair of the nonvolatile memory device into the SRAM memory cell array. In these cases, only the one between the SRAM memory cell array and the non-volatile memory array is angeord Nete field effect transistor controlled by.

A third possibility is to change information from the nonvolatile memory device via a bit line and a negated bit line to the outside without changing the bits stored in the SRAM memory cell array, and vice versa. In this case, the field effect transistor (V _WLF = H) respectively arranged between the bit line and the nonvolatile memory arrangement is controlled by. In these three ways of data transfer more control nodes are involved.

In a further embodiment of the invention, it is provided that a third series circuit with nonvolatile memory cells is arranged parallel to the first series connection of nonvolatile memory cells, that a fourth series circuit with nonvolatile memory cells is arranged parallel to the second series circuit of nonvolatile memory cells, that parallel to the first termination transistor, a third termination transistor and a fourth termination _transistor is arranged parallel to the second termination _transistor , wherein the third and fourth termination _transistors are each connected to a potential V _recall2 and _Vccrecall .

Next the arrangement of the third series connection parallel to the first series circuit and the arrangement of the fourth series connection parallel to the second Series connection are a third to the first termination transistor and the fourth termination transistor is assigned a fourth in parallel as specified in the claim.

In addition, the transistors TS1 and TS1Q are each connected to their gate terminals for selection by the line V _storesel1 and the transistors TS5 and TS5Q are also connected to their respective gate terminals to the line V _storesel2 .

through This arrangement ensures better chip area utilization the access times for Memory and reading are reduced and improved immunity to interference is reached.

The Invention will be explained below in several embodiments. In the associated Drawings shows

1 a memory cell according to the invention in an NV-SRAM memory circuit, wherein each SRAM cell is associated with four pairs of nonvolatile memory cells,

2 a further arrangement according to the invention with further explanations of the invention,

3 a memory cell according to the invention in an NV-SRAM memory circuit with explanations to the modes "Erase", "program", "Save" in the nv-cell pair 1 , "Save" in the nv-cell pair 4 and "Recall" from nv cell pair 4 .

4 a memory cell according to the invention in an NV-SRAM memory circuit in a dual-cell architecture and

5 a memory cell according to the invention in an NV-SRAM memory circuit with an SRAM memory cell and folded FLASH double-cell architecture

In the 1 is a memory cell according to the invention in an NV-SRAM memory circuit 1 which may also be referred to as an arrangement of a complex combined volatile and non-volatile multi-bit memory cell, each SRAM flip-flop 2 four complementary non-volatile memory cells 3 and 4 be assigned, these memory cells are designed as memory with selection transistors.

Every SRAM flip-flop 2 are several non-volatile memory cells 3 and 4 assigned such that via the SRAM selection transistor T2 a plurality of first non-volatile memory cells 3 (FLASH cells) containing the true information and, via the SRAM selection transistor T3, a plurality of second nonvolatile memory cells 4 (FLASH cells complement) containing negated information associated with it.

The four non-volatile memory cells 3 and 4 form a stack memory in which a plurality of information bits from the associated SRAM cell can be stored true and complementary to different times. The number of pairs of nonvolatile memory cells 3 and 4 can vary between one and 2 ⁿ cells.

For volatile access, the SRAM cell is selected via the two word lines WLF 5 and WLS 6 which are both switched to a high level H. With V _store1 = 0, the nonvolatile memory cells are deselected. Thus, only the information of the SRAM cell on the bit lines BL 7 and BLQ 8th (READ) or from the bit lines in the SRAM cell 2 (WRITE).

The read access to the non-volatile memory cells 3 and 4 is done by activating all selection transistors TS1 to TSn with V _store = H and V _recall = H. With WLF = H and WLS = 0, the SRAM cell becomes 2 separated from the non-volatile data and there is a data transfer to the bit lines BL 7 and BLQ 8th , With WLF = 0 and WLS = H, the bit lines BL become BL 7 and BLQ 8th deselected and the Data gets into the SRAM cell 2 transfer. The selection of the non-volatile data takes place via the control of the various V _SE signals.

The writing of the non-volatile cells can be analogous to the bit lines or the SRAM cells 2 respectively. In this case, V _recall = 0, so that no current path to V _{ccrecall is} possible, all selection and memory transistors in the stack are opened up to the selected memory transistor, all the transistors behind _{them are} closed up to V _ccrecall .

The applied differential principle allows for faster and less sensitive data access. A particular advantage of the invention is that in addition to the separate access to the non-volatile and SRAM cells 2 over the bitlines 7 and 8th every SRAM cell 2 can communicate directly with their associated 2 ⁿ FLASH cell pairs as well as the 2 ⁿ FLASH cell pairs with their associated SRAM cells in parallel on page, block or bulk level, as explained below.

Each mode of the complex combined volatile and non-volatile multi-bit memory cell can be initiated via a simple command. As such, this memory cell is a low voltage cell, with only the gates V _{SE of} the nonvolatile transistors being a high voltage driven node.

In the 2 is a complex combined volatile and non-volatile multi-bit memory cell according to the invention 1 represented, on which the features according to the invention are further explained by corresponding labels. By means of this arrangement according to the invention, the following advantages result:
A SRAM cell 2 can be assigned to 2 ⁿ nv cell pairs. An nv cell pair is passed through the nv cells 3 and the nv cells Q 4 formed in the example n = 2 and the number 2 ⁿ = 4.

Selective access to the SRAM cell 2 takes place for the true data on the bit line BL 7 and the transistors T1 9 and T2 10 and for the negated data on the negated bit line BLQ 8th and the transistors T4 12 and T3 11 ,

A selective access to the nv cells 3 (true) via the transistors T1 9 , TSn and TSEn. A selective access to the negated nv cells 4 via the transistors T4 12 , TSnQ and TSEnQ. Here, the variable n, for example, for the first nv-cell pair 13 the value 1 and for the fourth nv-cell pair 14 the values 1 to 4.

For these external accesses via the bit lines to the nv cells 3 and 4 remains the memory contents of the SRAM memory cell 2 obtained, with both a reading of bits from the memory cells 3 and 4 as well as storing bits in the memory cells 3 and 4 is possible.

A further advantage is that a direct data transfer between SRAM memory cell 2 and each nv cell pair (nv cells 3 / Nv-ZellenQ 14 ) is possible.

It there is no page limitation. Thus, both are bidirectional Transfer of one or more complete SRAM blocks as well as the entire SRAM a memory circuit or memory array possible.

Each stack consists of 2 ⁿ nv cell pairs (nv cells 3 / Nv-ZellenQ 4 ) and a recall transistor. Per bit 4 + 2 / n transistors are required.

By the possibility Direct data transfer will reduce power consumption as well as an increase reached the data rate.

Furthermore, there is only one common low-voltage interface (column decoder, precharge and sense amplifier) per bit line 7 and negated bit-line 8th required.

A reduced row decoder overhead is provided by "low-voltage" signals on all word lines 5 and 6 and the store lines V _store1 to V _store4 possible. A "high-voltage" signal is only necessary on one of the lines V _SE1 to V _SE4 .

The Invention allows a significant system simplification in an automatic data transfer for storing the information in the non-volatile memory area, which For example, in the so-called "power down" so a failure the supply voltage or controlled by a control command he follows.

This Also applies to a data recovery "Recall", in which on the non-volatile Memory area stored bits is used.

The inventive arrangement has one opposite lower power consumption in the prior art and a higher non-volatile reading and write speed, since the invention has parallels Page, block and device level uses and no external interfaces or buses needed.

The invention thus enables high reliability in non-volatile data storage It ensures optimal system performance by implementing the memory cell in a dual-memory architecture, minimizing power dissipation, independent accesses to the SRAM and FLASH memory sections, and competitive system cost.

At the in the 3 illustrated complex combined volatile and non-volatile multi-bit memory cell according to the invention 1 Next, the "Erase" mode will be used to clear non-volatile memory cells 3 and 4 and the "WRITE" mode for programming non-volatile memory cells 3 and 4 explained.

To erase the non-volatile transistors TSE1-4 of the nonvolatile memory cells 3 and the non-volatile transistors TSE1Q-4Q of the nonvolatile memory cells 4 For example, the associated control lines V _SE1 to V _{SE4 are} applied to the negative erase voltage V _ER of, for example, -10V.

Furthermore, the select transistors TS1 to TS4 and TS1Q to TS4Q are disabled and the control signals V _store1 to V _store4 are set to 0 V for this purpose.

It is possible to set individual control lines as well as all control lines V _SE1 to V _SE4 to the potential V _ER , thus individual pages, blocks or the entire array can be deleted.

Prior to each programming, erase of the respective non-volatile transistors TSE1-4 of the nonvolatile memory cells 3 and the non-volatile transistors TSE1Q-4Q of the nonvolatile memory cells 4 as described above. It is also possible to perform this erase globally before many consecutive "WRITE" cycles.

The information to be programmed in the nonvolatile memory cells is "true" at node K1 15 at and in their negated form at node K1Q 16 ,

• – Speicherung in das erste nv-Zellen-Paar 13 und
• – Speicherung in das vierte nv-Zellen-Paar 14

beschrieben werden.This information can either via the transistors T1 9 and T4 12 from the bit lines BL 7 and BLQ 8th or via the transistors T2 10 and T3 11 from the SRAM cell 2 to be provided. Such storage in the nonvolatile memory area 3 and 4 should be exemplary for the two cases

• - Storage in the first nv-cell pair 13 and
• - Storage in the fourth nv cell pair 14

to be discribed.

The first nv-cell pair 13 consists of transistors TS1, TSE1, TS1Q and TSE1Q. The fourth nv cell pair 14 consists of transistors TS4, TSE4, TS4Q and TSE4Q.

To transfer the information from the nodes K1 15 and K1Q 16 to the nodes K _SRSE1 / K _DTSE1 and K _STSE1Q / K _{DTSE1Q leading} to the first nv cell pair 13 are associated, a potential V _High of, for example, 1.8 V is applied to V _store1 . By applying this potential, the transistors TS1 and TS1Q become conductive.

For this example, let V (K1) = 0V and V (K1Q) ~ 1V (VHigh - Vth). Since TSE1 and TSE1Q are depletion transistors at this time due to the previous erase operation and VSE1 = 0 V, the potentials are V (K _STSE1 ) = V (K _DTSE1 ) = 0 V and V (K _STSE1Q ) = V (K _DTSE1Q ) ~ 1V (VHigh - Vth).

With V _store2 = 0 V, the nv cells number 2 to number 4 are separated from the information to be stored. To optimize the non-volatile storage, the control _nodes V _recall = V _SE4 = V _store4 = V _SE3 = V _store3 = V _SE2 = V can be switched _high . With V _SE1 = V _PP ( _10V ) and V (K _STSE1 ) = V (K _DTSE1 ) = 0V, the threshold voltage of TSE1 is shifted and TSE1 is converted into an enhancement transistor.

Since the potential V (K _STSE1Q ) = V (K _DTSE1Q ) = 1 V and a capacitive coupling of VSE1 to K _STSE1Q / K _{DTSE1Q occurs} at V _store1 = V _High , the voltages V (K _STSE1Q ) = V (K _DTSE1Q ) >> 6 V.

The Gate-source voltage of TS1Q becomes smaller than its threshold voltage and TS1Q locked. Since the gate-source voltage of TSE1Q << 4 V is TSE1Q is not programmed.

The transistor TSE1Q thus remains a depletion transistor. With the discharge to V _SE1 = 0 V, the non-volatile storage is completed. V _store1 = 0 V allows subsequent SRAM accesses and separates the nv cells from the SRAM cell.

To transfer the information of the nodes K1 and K1Q to the nodes K _STSE4 / K _DTSE4 and K _STSE4Q / K _{DTSE4Q corresponding} to the fourth nv cell pair 14 are attached to the control lines V _store4 = V _SE3 = V _store3 = V _SE2 = V _store2 = V _SE1 = V _store1 = V _high .

Transistors TS1, TSE1, TS2, TSE2, TS3, TSE3, TS4 and TS1Q, TSE1Q, TS2Q, TSE2Q, TS3Q, TSE3Q, TS4Q are conductive. In the example, let V (K1) = 0V and V (K1Q) = 1V. Since TSE4 and TSE4Q are depletion transistors at this time and the voltage VSE4 = 0V, the Po potential V (K _STSE4 ) = V (K _DTSE4 ) = 0 V and V (K _STSE1Q ) = V (K _DTSE1Q ) = 1 V.

With a voltage V _recall = 0 V is the nv cell 14 separated from the supply voltage V _ccrecall . With V _SE4 = V _PP of 10 V and V (K _STSE4 ) = V (K _DTSE4 ) = 0 V, the threshold voltage is shifted by TSE4 and TSE4 becomes an enhancement transistor.

Because V (K _STSE4Q ) = V (K _DTSE4Q ) ~ _1V and the capacitive coupling of VSE4 to K _STSE4Q / K _DTSE4Q at V _store4 = V _High , V (K _STSE1Q ) = V (K _DTSE1Q ) >> _6V , because the gate-source voltage of TS4Q is less than its threshold voltage and it is thus locked.

Since the gate-source voltage of TSE4Q is much smaller than 4V, TSE4Q is not programmed. TSE4Q thus remains a depletion transistor. With the unloading of VSE4 = 0 V, the non-volatile storage is finished. V _store1 = 0 V allows subsequent SRAM accesses and separates the nv cells from the SRAM cell.

Hereinafter, the "recall" mode, which is a restoring of information bits from the pair of nonvolatile memory cells 3 and 4 into the SRAM cell 2 realized, using the example of the fourth nv-cell 14 explained.

To transfer the information from the transistors TSE4 and TSE4Q to the nodes K1 and K1Q a high potential is applied such that Vrecall = V _store4 = V _SE3 = V _store3 = V _SE2 = V _store2 = V _SE1 = V _store1 = V _high is ,

The gate voltage of the transistors TSE4 and TSE4Q to be read, in this case V _SE4 , remains at 0 V. The transistors TS1, TSE1, TS2, TSE2, TS3, TSE3, TS4 and TS1Q, TSE1Q, TS2Q, TSE2Q, TS3Q, TSE3Q, TS4Q are conductive. In this example, TSE4 is an enhancement and TSE4Q is a depletion transistor. K1 and K1Q are before the start of the restore via the transistor T1 and the bit line BL 7 and via the transistor T4 and the bit line BLQ 8th set to 0V. TSE4 is disabled and node K1 can not be charged, whereas node K1Q is charged to ~ 1V via transistors T6, TSE4Q, TS4Q, TSE3Q, TS3Q, TSE2Q, TS2Q, TSE1Q and TS1Q. This voltage difference of ~ 1V between K1 and K1Q can be transferred to the SRAM cell via both transistors T2 and T3 2 taken as well as via T1 and T4 from the bit lines BL 7 and BLQ 8th assigned, not shown here, the sense amplifier to be evaluated.

The Information is thus available for reuse volatile.

• • nvSRAM only – READ – WRITE – STORE – RECALL – Autostore – Power up Recall
• • FLASH only – Page WRITE – Page READ – Page ERASE – Block ERASE
• • nvSRAM/FLASH – Block Transfer FLASH zu SRAM – Block Transfer SRAM zu FLASH – Page Transfer nvSRAM zu FLASH

The solution according to the invention comprises the following operating modes:

• • nvSRAM only - READ - WRITE - STORE - RECALL - Autostore - Power up Recall
• • FLASH only - Page WRITE - Page READ - Page ERASE - Block ERASE
• • nvSRAM / FLASH - Block Transfer FLASH to SRAM - Block Transfer SRAM to FLASH - Page Transfer nvSRAM to FLASH

In a further embodiment of the invention it is provided that the complex combined volatile and non-volatile multi-bit memory cell is implemented as a double cell, in which two SRAM cells 2 are arranged in an architecture on the chip, as in the 4 shown. Every SRAM cell 2 four FLASH cell pairs, which form the non-volatile memory area, are assigned. These are in the 4 as the first non-volatile memory cell 3 and second nonvolatile memory cell 4 shown in excerpts.

By This arrangement variant will make better use of existing ones chip area reached.

In In this embodiment, there is the possibility of a word line-controlled Summons to not program the unselected FLASH Cells of a double-cell architecture for FLASH-only operations (data from BL / BLQ) and / or selective nv-SRAM transfer operations.

The 5 shows a further embodiment of the invention. In this it is envisaged that in the complex combined volatile and non-volatile multibit memory cell the FLASH cells will be folded with each SRAM cell 2 Two stacks of nv-cell pairs are assigned, as in the 5 shown. Thus, the node is K1 15 with two first non-volatile memory cells 3 and the node K1Q 16 with two second non-volatile memory cells 4 connected.

The selection of the stack of nv-cell pairs takes place via the 4 control lines V _recall , V _{recall 2} , V _{storesel 1} and V _{storsel 2} .

Thus, for example, in the case of the store operation, the information of the nodes K1 / K1Q with active V _storesel1 and VSE1 = Vpp in the Transisto TSE1 / TSE1Q are written non-volatile. To avoid a parasitic store in the transistors TSE5 / TSE5Q, V _storesel2 = V _recall1 = 0V and Vrecall2 = VSE4 = Vstore4 = VSE3 = Vstore3 = VSE2 = Vstore2 = Vhigh.

In order to are the potentials V (Kstse5) = V (Kdtse5) = V (Kstse5q) = V (Kdstse5q) ~ 1 V and become VSE1 = Vpp >> 6 V coupled.

TSE6 and TSE6Q are disabled and the gate-source voltages of TSE5 and TSE5Q are << 4V, it is done no programming.

LIST OF REFERENCE NUMBERS

1

NV-SRAM memory cell

2

SRAM memory cell

3

first nonvolatile memory cells

4

second nonvolatile memory cells

5

wordline WLF

6

wordline WLS

7

bit BL

8th

negated Bit line BLQ

9

first Transistor T1

10

second Transistor T2

11

third Transistor T3

12

fourth Transistor T4

13

first nv cell pair

14

fourth nv cell pair

15

first Center tap K1

16

second Center tap K1Q

17

first final transistor

18

second final transistor

19

third final transistor

20

fourth final transistor

Claims (8)

A memory cell in an NV-SRAM memory circuit, comprising an SRAM memory cell for volatile storage of information bits and a non-volatile memory area containing nonvolatile memory cells, the nonvolatile memory area having control lines for storing and reading information bits (STORE, RECALL) and for erasing the information bits Memory cells (ERASE) is connected, wherein the SRAM memory cell is connected to a first bit line BL and a second bit line BLQ, characterized in that between the SRAM memory cell ( 2 ) and the bit line BL ( 7 ) a first transistor ( 9 ) and a second transistor ( 10 ) and between the SRAM memory cell ( 2 ) and the bit line BLQ ( 8th ) a third transistor ( 11 ) and a fourth transistor ( 12 ) is arranged such that a first center tap ( 15 ) between the first and second transistors ( 9 and 10 ) and a second center tap ( 16 ) between the third and fourth transistors ( 11 and 12 ) is arranged such that the first center tap ( 15 ) having a plurality of first information storage bits arranged in a first information circuit storing first non-volatile memory cells ( 3 ) and the second center tap ( 16 ) having a plurality of second non-volatile memory cells storing negated true information bits arranged in a second series circuit ( 4 ), that the last nonvolatile memory cell ( 3 ) of the first series connection via a first termination transistor ( 17 ) and the last nonvolatile memory cell ( 4 ) of the second series connection via a second termination transistor ( 18 ) are each connected to a potential V _recall and V _ccrecall . Arrangement according to claim 1, characterized in that the SRAM memory cell ( 2 ) is designed as a flip-flop memory cell. Arrangement according to claim 1 or 2, characterized in that each non-volatile memory cell ( 3 and 4 ) each consists of a nonvolatile transistor and a selection transistor. Arrangement according to one of Claims 1 to 3, characterized in that the nonvolatile memory area contains a plurality of complementary pairs of nonvolatile memory cells ( 13 to 14 ), in each of which a first non-volatile memory cell ( 3 ) and a second non-volatile memory cell ( 4 ) is arranged to store a bit in its true and negated form. Arrangement according to one of Claims 1 to 4, characterized in that the SRAM cell ( 2 ) by means of a first active control signal on a word line WLS ( 6 ) via the second transistor ( 10 ) and the third transistor ( 11 ) with an nv-cell pair selected by means of a selection signal ( 13 to 14 ) is connected to backup or restore information bits. Arrangement according to one of Claims 1 to 4, characterized in that the s is the SRAM cell ( 2 ) by means of the first active control signal on the word line WLS ( 6 ) and a second active control signal on the word line WLF ( 5 ) via the second transistor ( 10 ) and the first transistor ( 9 ) with the bit line BL ( 7 ) as well as the third transistor ( 11 ) and the fourth transistor ( 12 ) with the bit line BLQ ( 8th ) connected is. Arrangement according to one of Claims 1 to 4, characterized in that an nv-cell pair selected by means of a selection signal ( 13 to 14 ) for writing or reading information bits by means of the second active control signal on the word line WLF ( 5 ) over the first transistor ( 9 ) with the bit line BL ( 7 ) and via the fourth transistor ( 12 ) with the bit line BLQ ( 8th ) connected is. Arrangement according to one of Claims 1 to 3, characterized in that parallel to the first series connection of nonvolatile memory cells ( 3 ) a third series connection with nonvolatile memory cells ( 3 ) is arranged such that parallel to the second series connection of nonvolatile memory cells ( 4 ) a fourth series connection with nonvolatile memory cells ( 4 ) is arranged such that parallel to the first termination transistor ( 17 ) a third termination transistor ( 19 ) and parallel to the second termination transistor ( 18 ) a fourth termination transistor ( 20 ), wherein the third and fourth terminating transistors ( 19 and 20 ) are each connected to a potential V _recall2 and _Vccrecall .

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