DD205560A1 - CIRCUIT FOR COMPUTER COUPLING WITH "M VON N" COMPARISON - Google Patents

Abstract

The invention relates to a circuit arrangement for computer coupling, with the systems, especially for high reliability and / or security requirements, can be realized. Such a circuit arrangement can be used everywhere where similar measured values or other similar signals in digital form from n different sources according to the "m of n" principle are checked for agreement. The aim of the circuit arrangement according to the invention is to ensure secure information processing and, moreover, to increase the reliability (availability) of the information processing. According to the invention, signals from n data sources are compared according to the "m of n" principle and the coupling to a computer-internal bus is established. The computer signals are output to an external bus and / or peripherals. The computer signals of n-parallel operating units are checked in the operating mode "internal comparison" on agreement.

Description

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Circuit arrangement for computer coupling with "m of η" comparison

Field of application of the invention; The invention relates to a circuit arrangement with which systems, especially for high reliability and / or safety requirements, can be realized. "Such a circuit arrangement can be used anywhere where similar measured values or other similar signals in digital form of η different sources after the" m be checked for conformity by η "principle

Characteristic of the known technical solutions A circuit arrangement is known ;-( DEr-CS 2612-, 100,)

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a digital data processing with two-channel modules, which are gradually controlled by a common clock power supply. At each processing step, a monitoring pulse is output in addition to a plurality of control signals. *, 'This clocking pulse is used to interrogate series-connected comparators.' In the presence of correct signal pairs, the monitoring pulse becomes error-free to trigger for the next processing step required control signals and another monitoring pulse output to the clock power supply * A disadvantage of this solution is that additional facilities for clock generation and clock transmission are required. In addition, there is a digital

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talrechnervorrichtung consisting of two mutually umschal tbaren computer combinations known (DE-OS 2915 401) »The redundant computer in the combination is only for comparison and a computer operates on the output, wherein between the output of the first computer and the output of the second computer Bit-by-bit comparison is performed. The number of equality or inequality is counted, and at a certain level, the message and a switch or block the working on the technological unit two-computer group _s complex systems with more than a dual computer system, this solution is economically complicated, since for each Doppelrechnersys- a similar, redundant system is provided,

Furthermore, a multicomputer system for controlling train-bound means of transport is known (DE-AS 2725 922), in which all computers process the same information asynchronously, the result information for checking for errors being compared with one another only at the end of a computing cycle. To ensure asynchronous operation, the information is forwarded to the individual computers at different times. * The output data of the individual computers are checked by means of a comparison and switching device. »The comparison is first made. led when the majority of computers have come to an end. This is done by a logic circuit that is not redundant, so that errors that may occur within the logic circuit are not detected,

Object of the invention .

The aim of the circuit arrangement according to the invention is to ensure secure information processing and moreover to increase the reliability (availability) of the information processing,

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Presentation of the invention

The invention has for its object to develop a circuit arrangement for Eechnerkopplung that compares redundant signals from η data sources according to the "m of η" - principle that produces coupling to a computer internal bus, outputs computer signals to an external bus and / or peripheral devices and Computer signals from parallel operating units linked in an internal comparison * According to the invention the object is achieved in that the first bidirectional terminal of an input / output module is connected to a computer internal bus, the second bidirectional connection of the input / output module a Zweirichtungstor and a latch is connected, wherein the output of the Zweirichtstores with the sources QV to Qn is merged. The first input of the bidirectional gateway is linked to the first output of a data comparator * The first input of the data comparator receives the data of the parallel units * The second input of the data comparator is linked to a buffer, a controlled gate and the parallel units, with the controlled gate the data of the source Qi is present "The third bi-directional connection of the input / output module is connected to the control signal logic and a coupling logic. The output of the control signal logic is connected to the first bidirectional terminal of a shake-hand logic, the 2'-whisker , the second input of the bidirectional gate, the third entry, the data comparator, the controlled gate and the first input of a 7 / artelogik. The ready output of the input / output module is connected to the wait logic, to the buffer and to the shake-hand logic. "The I-ready output of the buffer is connected with the shake-hand logic, on whose third bidirectional port is sourced from the signals of the sources Q1 to Qn and whose second bidirectional port is connected to the parallel units _o The ready "output of the shake-hand logic is

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connected to the wait logic, whose first output is connected to the internal computer bus and whose second output is connected to the input / output module. »The first output of the shake-hand logic is connected to the first input of an error evaluation logic whose output is connected to the Input / output module is connected, the second input of the error evaluation logic with the output of the coupling logic, the aft bidirectional terminal connected to the parallel units and the third bidirectional terminal connected to the sources Q 1 to Qn, the second The output of the shake-hand logic is linked to the bidirectional gate, and the third output of the shake-hand logic is connected to the data comparator, the second output of the data comparator being connected to the third input of the error-evaluating logic »

In a further embodiment of the invention, the fourth bi-directional connection of the shake-hand logic is connected to a first time logic and the fourth bi-directional connection of the coupling logic to a second time logic ,, The first and the second time logic is required when the information from the data sources Q1 until Qn arrive asynchronously »The buffer and the controlled gate are not required if there are no parallel operating units. The data input Qi and outputs Q1 to Qn can be combined to form a bidirectional connection if all the computers to be coupled or "other devices have bidirectional connections"

The bidirectional connections between the blocks of the circuit arrangement are either independent unidirectional connections in both directions or true bidirectional connections »

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The invention is based on an embodiment

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be explained in more detail.

The enclosed drawing shows:

Pig _o 1: Circuit arrangement for computer coupling with " m of η 'comparison

The circuit arrangement according to the invention (Pig »1) is used to construct a connection card for a computer of a multi-computer system and organized in conjunction with the connected computer, the structure of a data transmission path and the transmission of data words Pur applications with high level of reliability required is a comparison of η input data (thereof n-1 reserve) possible with 1-bit, while the output of information is single-channel »work η parallel units from the same algorithm, so are also η output signals available,

The circuit arrangement is connected via an input / output module 1 to the computer-internal bus If in the overall system no data transmission, for which the circuit arrangement according to the invention is required, is desired, all signals between the circuit arrangement according to the invention and the possible coupling partners inactive ο Will of a Computer arrangement sends a data transmission from or to another computer system of the system (coupling partner), the former sends a coupling signal containing the address of the partner to be called. The called computer arrangement returns the call by sending an acknowledgment signal, which can also contain an acknowledgment address. The combination of the call and acknowledgment signals in the control signal logic 10 results in the specific for each coupling control signals that block or open the individual data paths in the circuit arrangement «Thus, the data transmission is opened and two partners d coupled with the system «Subsequently, word-wise data transmission (1-bit in each case) starts over the coupled link, with the help of shake-hand signals, which are ready-to-use.

Signals from the respective input / output module 1 of the connected computer arrangements are output "After input / output of a data word via the input / output module 1, the associated ready signal is active and thus also via the wait logic 6 ? / artesignal »The computer arrangement waits for the ready ⁺ signal of its coupling partner, which puts the waiting signal into the inactive state and the computer arrangement can thus input / output the next data word. u» s «f _β until the end of the data transmission * The duration the state of the state is monitored in the wait logic 6, this state is ended when the specified time is exceeded and reported to the computer via the input / output module 1. "

In the data comparator 3, in the shake-hand logic 8 and in the coupling logic 11, a comparison of the respectively associated η signals takes place and the selection signals ("m of η" majority decision) are further processed in the manner described above for this is that each η computer work in parallel and provide redundant information (data sources Q1 to Qn) meet this η information in terms of time, z "B" by different signal propagation times, staggered program execution, or · different program versions in the computer arrangement, in the example consisting of the sources Q1 to Qn, this time is compensated by the time logic 9 * 1 or »9 · 2 in a fixed interval» Bei .einer Zeitüberschreitung the selection signal formed at this time is output and an error signal to the error evaluation logic 7 guided In case that three equal input signals are present before the expiry of the specified time, the error signal logic 7 detects all individual errors from the data comparator 3> the shake-hand logic 8 and the coupling logic 11 and stores them until registration by the computer to the central message »At two and

more registered different individual errors, the formation of a multiple error signal Z ₀ B ₀ causes an interruption or at least causes a repetition of the program lausage.

Another mode is provided to increase the reliability - and / or security of multiple parallel computers. According to the program specified information from the redundant computers are compared. For this purpose, in each computer, the output of a 1-bit data word and EinsÃEeieherung in the buffer 5 »In the second step, this data word is given via the internal connections between the parallel operating units to the data comparator 3 of the parallel units and compared there. Signals that may be present from the external data sources are blocked by the controlled gate 4 in this operating mode. "For this operating mode, corresponding shake-hand signals (ready and I-ready) exist as in the operating mode described first. The signal I-ready represents the ready message for the operating mode "internal comparison". In Fig. 1 these signal paths are identified by the designation " ⁿ parallel units." For the described "inner comparison", the same circuit units are used as for the external data transmission * With the operating mode. " internal comparison "can also be easily the Wiederangleicht a repaired computer to reintegrate into the parallel mode of operation _{o In} addition receives the computer to be adjusted on his Singangsyergleicher the current data of the other parallel operating units and can thus fill his main memory.

If the computer arrangement under consideration itself is a data source, the two-directional gate is switched to output with the specific control signals, so that a 1-bit data value can be output via the input / output module 1 in a single channel «

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In the "internal comparison" operating mode, the output path is blocked via the two-directional gate 2. "If the redundant computer systems are linked by bidirectional bus lines, the outputs in Pig. 1 unidirectional Bin- and output lines according to their logical identity to connect. With the aid of the coupling-type-specific control signals from the control signal logic TO, the unwanted signal paths possible by this connection are interrupted. The bidirectional connections between the individual blocks shown in Pig.i consist of unidirectional connections in both directions or are "true" bidirectional connections Implementation variant of the data and control signal comparators is the use of a programmable Pestwertspeichers, with the help of both the formation of the selection and the error signals is carried out *

Claims (1)

ι 1 s ^ 1 I j invention claim 1. Circuit arrangement for Reclmerkopplung with "m of η" comparison, characterized in that the first bidirectional terminal of a Sin- / outputting device (1) is connected to a computer-internal bus, the second bidirectional connection of the input / output module (1) is connected to a bidirectional gate (2) and a buffer memory ^), the output of the bidirectional gate (2) being connected to the sources Q1 to Qn, the first input of the bidirectional gate (2) to the first output of a data comparator (3 ) and at the first input of the data comparator (3) are the data of the parallel units, the second input of the data comparator (3) with a buffer (5) »a controlled gate (4) and the parallel units is linked, wherein the controlled Tor (4) abut the data of the source Qi, the third bidirectional connection of the input / output module (1) with the control signal logic (10) and a coupling logic (11) the output of the control signal logic (10) is connected to the first bidirectional terminal of a shake-hand logic (S), the buffer (5), the second input of the bidirectional gate (2), the third input of the data comparator (3). ? the controlled gate (4) and the first input of a waiting logic (6) is combined, the ready output of the input / output module, (1) to the. Wartel.ogik (6), to the. Latch (5) and connected to the shake-hand logic (8), the 1-ready output. of the "latches" (5), with the shake-hand logic (S), at whose third bidirectional terminal the signals of the sources Q1 to Qn are present and whose second bidirectional terminal is connected to the parallel units, the ready ' Output of the shake-hand logic (S) with the V / artelogic (6) whose first output to the computer-internal bus and whose second output to the input / output component (1) is notch, connected, the first one * - ' ^f > t U O' {J - 10 - Output of the shake-hand logic (8) to the first input of a fault evaluation logic (7) whose output is connected to the input / output 3-block (1) is linked, wherein the second input of the Pehlerbewertungslogik (7) with the Output of the coupling logic (11), whose second bidirectional terminal is connected to the parallel units and whose third bidirectional terminal is connected to the sources QI to Qn, the second output of the shake-hand logic (8) is connected to the bidirectional gate (2 ) and the third output of the shake-hand logic (δ) is connected to the data comparator (3), wherein the second output of the data comparator (3) is connected to the third input of the Pehlerbewertungslogik (7). o circuit arrangement for computer coupling with "m of η" comparison according to item 1, characterized in that -the fourth bidirectional connection of the shake-hand logic (8) with a first time logic (9 * 1) and the fourth bidirectional connection of the coupling logic (11) is connected to a second time logic (9 * 2) « For this 1 page drawing