DD204788A1 - CIRCUIT ARRANGEMENT FOR IMPLEMENTING CIRCUITS IN A SYSTEM - Google Patents

Abstract

The invention relates to a circuit arrangement for simulating circuits in a system. The circuit arrangement is intended to make it possible initially to carry out and test logic or circuit changes in LSI circuits without hardware changes. A circuit simulator is proposed which operates in place of the circuit in the system. It monitors the input levels and, if a level changes, brings about a system stop, calculates the output signals based on the stored logic and makes them available to the system for further processing.

Description

Title of the invention

Circuit arrangement for simulating circuits in a system

Field of application of the invention

The invention relates to the replacement of complex logic circuits (master-slice circuits) in electronic logic systems during the initial commissioning of such systems and to their simulation in the development _β

Characteristic of the known technical solutions In the development of complex electronic systems / z. As EDVA central processing units), it is known to simulate circuit complexes to verify the accuracy of the design. For this purpose, the hardware functions are simulated with software means, so that with special simulation programs, the effect of the logic circuits can be modeled. Purely the simula ionization schemes are to be created by the logic designer simulation examples that define the input and output conditions of a logical complex. The execution of these examples is performed on large computer systems and is associated with a high computing time. The evaluation of the simulation results is usually done on a manual basis.

When commissioning such systems, numerous errors are still found that need to be eliminated during this process. In this case, circuit changes are required, the correctness must be tested again »It must be changed lines and circuits u. U. be replaced.

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In the use of master-slice circuits containing several hundred gates, this particular difficulties arise difficulties, since a change in the wiring of such a circuit is not possible. It is necessary to make new circuits and the commissioning is interrupted until their provision or continued by means of interim solutions. Furthermore, it is desirable to first test the changes - before the new circuit is made - in the system in order to obtain a high degree of certainty as to their accuracy. The verification of the logic circuits can be done with discrete logic, special circuits in LSI technology, programmable logic arrays (PLA), and the like. Like. Be performed. The disadvantage of these solutions is that for the replica first to design a special logic circuit (possibly with machine support) and the hardware implementation is to be realized. It thus costs and a Zeitverdessen size of the nachzubildenden circuit. Depends.

Object of the invention

The aim of the invention is to improve the quality and quantity of said processes while reducing costs ",

Explanation of the essence of the invention

The invention has for its object to provide a programmable device for reproducing complex logical structures, djie individually as a substitute for such a logical structure, uijjd. in a majority to replicate the complete system is suitable.

According to the invention, the object is achieved by means of a circuit arrangement with a data memory, a command memory with a command register and an arithmetic unit for logic functions which has the following features: a register for recording the input signals of the circuit to be emulated in parallel

«Comparators connected to the register and the input device

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a clock stop line connected to the comparators and the own clock control as well as the system

»A selection circuit connected to the input lines and the data memory

- An output register connected to the data memory for the calculated output levels

- A line for triggering the clock start of the system, which is connected to the command register

an input register for serial-to-parallel conversion for the instruction memory connected to the diagnostic device of the system.

A preferred embodiment is that the command memory aifei command register with control and address part downstream, the address parts with the data memory and the Ausvuahleleängen the selection circuit and the control parts are connected to the arithmetic unit, the output register, the own and the system clock control and the input register ,

Äusführungsbeispiel

In the drawing,

Figo 1 i a block circuit diagram of the circuit simulator, ELg.-2s a block diagram of the data and instruction memory, _e Figure 3: 'two OR circuits,

SIg. 4s details of a selection circuit »

Figure 1 _e shows a circuit adapter 1, which connects the contacts of the to be replaced in the system circuit to the driver / receiver circuit. 2 Its output leads via the input lines 12 to a register 7, a comparator and a selection circuit 11. One of the lines 12 is connected to the clock controller 10. From the output of the comparator, a line 9 leads to the clock control of the system and to the clock control 10 whose outputs 23 provide the clocks for controlling the circuit simulator. A line 27 from the input lines 12 leads to an input register 15, referred to as

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Shift register is formed and its parallel outputs are connected to the bus 16. The output of the selection circuit 11 leads via the line 24 also to the bus 16g to the further the data memory 3 »the instruction memory 4 with the command register 5> the arithmetic unit 6 with the registers 18j 19 and via line 25 an output register 13 are connected. Its parallel outputs lead to the driver / receiver circuit 2 via the output lines 17. The output lines 17 also contain control lines for the driver / receiver circuit 2. From the command register, a line 14 leads to the clock control of the system. The dashed arrows symbolize control inputs and outputs.

The Big, "2 shows some more details of the data and instruction memory 3; 4 · The commands include 2 bytes. The instruction memory 4 is preceded by an address network 22 and there are two instruction registers 5 · 1; 5 * 2, which consist of a control part 20 (4 bits) and an address part 21 (12 bits). From the control part lines lead to the selection circuit 11, the arithmetic unit 6, the input register 15 and the output register 13 «The address parts 21.1; 21.2 are connected to the data memory 3 "of the selection circuit 11 and the output register 13. The "word width" of the data memory is 1 bit.

4 shows the principle of the selection circuit 11 for one of the input lines 12 and the distribution of the calculated output and control signals to the output register 13. The last 128 memory locations are used to store the input and output signals. The address signal on line 28 is formed by the OR circuit 29 from the 7 lowest address strokes when the 5 highest address bits are 1. To the HOR circuit 30, the line 28, one of the input lines 12 and an OR circuit 31 are connected, which decrypts the instruction code 1 in conjunction with the NOR circuit 30. As a result, the selected input line is switched to the line 24. Another OR circuit

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decrypts the instruction code 2 in conjunction with the NOR circuit 33, whereby the line 25 is switched to the line 34, which leads to a flip-flop of the output register 13.

Table 1, in conjunction with FIG. 2, serves to explain the calculation of the OR circuits shown in FIG. The assignments of the inputs ABC; EFG are stored in the data memory 3. The instructions for transporting the data to the registers 18; 19 and back to the data memory and for the operation to be performed are alternately applied to the instruction registers 5.1; 5 · 2 supplied. The assignment of output D is saved to the assigned address. It can be seen that the reading of the command memory 4 and the reading and writing of the data memory take place simultaneously. The logical function is executed in the same step with the reading and writing of the data memory. Table 2 shows the command code and the functions controlled by it.

The operation and the effect of the circuit simulator will be briefly described below. The circuit adapter 1 is connected to the system instead of the circuit to be simulated. The loading of the instruction memory 4 is microprogram controlled by an operator and service processor connected to the system. For the addressing of the circuit simulators and for the data transport, the means of transmission and data paths of the existing Orthogona system for login / logout are used. The operator and service processor also provides the shift clock for the input register 15. The incoming shift clock is counted in the clock controller 10 and triggers a memory cycle for transferring one instruction word from the input register to the instruction memory 4 every 16 shift clocks. The Adreßbereitstellung carried by the address network 22, in which springs in memory cycle, the address is increased by 1. After completion of the charging process for a circuit simulator is in the address network 22, the start address for the start of a calculation cycle.

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Are in. System replaces several or all circuits by circuit simulators, their instruction memory are loaded in the same way. Thereafter, by resetting the system, the initialization of all circuit simulators, i. that is, the native reset signal triggers one or more calculation cycles to define the outputs of flip-flops.

Each level change detected on the input lines triggers a calculation cycle in the following. This is understood as the one-time execution of the program stored in the instruction memory. In the comparator 8 level changes are detected on all input lines at the times * n * ^ n + 1 * ^t n + 2 * ^etc. *. When an inequality is signaled, the system is placed in the stop state via line 9 and the circuit simulator is activated by the clock controller 10, in which clocking and clocking are performed for the logic and memory circuits. The cycle length is determined by the gate delay time of the operation logic on the one hand and on the other hand by the timing of the memory circuits used. About the selection circuit 11, the applied level values are first transferred to the data memory. As already mentioned, the highest addresses are used for this purpose. The control of the transmission is performed by the command code 1 to the addresses specified in the command, which simultaneously determine the input lines. The instruction words read from the instruction memory are alternately input to the instruction registers 5.1; 5 * 2 registered. Parallel to each command word reading is a write cycle of the data memory 3 »which is addressed by the address part of the command word. The addressing of the command memory. 4 is done by the address network 22 providing the address in ascending order. The address handoff is controlled by the clock controller 10 so that a memory cycle can be started at each clock cycle. For instructions with logic functions, the data bits from the data memory are transferred to registers 18; 19 transmitted. The logical one

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Linking takes place within the memory cycle for the data transport according to the command codes 8 to 11 (Table 2). The register 18 records the result. The individual steps for calculating the logic state of a gate output are shown in Table 1.

At the end of a calculation cycle, i. h., When the logic state of all gate outputs of the circuit to be simulated is known, the output data from the data memory 3 are transported to the output register 13. The addressing of the individual flip-flops of the register takes place as shown in FIG.

The "transmission is controlled by the instruction code 2. The output data also includes the control data for the driver / receiver circuit.""After the output data has been provided, the system is started via the line 14 by the instruction code 14" _{e "} are several circuits through simulators System work can only be continued once all the simulators have provided the output data, which means that it is necessary to evaluate the completion signal of all circuit simulators in an additional logic circuit - only after stabilization of the system, ie no further level changes be detected, the forwarding of the system clock is released lin the following;

Claims (2)

238 59 2 4 invention claim 1. Circuit arrangement for simulating circuits in a system with a data memory, an instruction memory with command register and a computing unit for logic functions, characterized by a register for receiving in parallel the input signals of the circuit to be reproduced - with the register and the input lines - connected comparator a clock stop line connected to the comparator and its own clock control as well as that of the system a selection circuit connected to the input lines and the data memory - An output register connected to the data memory for the calculated output levels - A line for triggering the clock start of the system, which is connected to the command register an input register for serial / parallel conversion for the command memory connected to the diagnostic device of the system. 2. Circuit arrangement according to item 1, characterized in that: the j command spei rather two command register with control and j & drq (senkelΓ downstream, the address parts with the Data memory and the selection inputs of the selection circuit and the, control parts with the arithmetic unit, the Ausgangsregist he, the own and the system clock control and the; Input registers are connected   'ι' For this 2 pages drawings and 2 pages tables.