DD204593A1 - TWO SIDES AD CONVERTER - Google Patents

Abstract

The invention relates to a dual-slope AD converter for integrating AD conversion. The aim is to reduce the influence of imperfect resistance properties. The object of providing a high precision two-flank AD-converter without dominating resistors is achieved by the integration time (TI) being proportional to the primary reference voltage (Uz) such that the reference voltage (UR) used for the integration is equal to the primary reference voltage (UR). Uz) is that for a digital reference adjustment in a digital reference source (30) a reference digital value (DR) stored and the duration of Aufintegrationszeit by determining the equality of the Zaehlerinhalts the Vorwaertszaehlers (23) with the reference digital value (DR) by means of an equivalent circuit (34 ) and that the reference digital value (DR) is numerically equal to the primary reference voltage (Uz). The inventive solution is preferably applicable in devices of electronic metrology or the BMSR technique.

Description

238639

Title of the invention Two-flank AD converter

Field of application of the invention

The invention relates to a two-flank AD converter (dual-slope AD converter) for integrating analog-to-digital conversion. It can be used, for example, in devices of the electronic measuring technology or the BMSR technology.

Characteristic of the known technical solutions

In known Zweflank (dual-slope) AD converters for integrating AD implementation, especially as a digital voltmeter with interference suppression realized for DC voltage measurement, u.a. DE-OS 1 935 124 (21e-19/26), an integrator, a comparator, a gate circuit and a result counter with display are nachgesetzt. The time sequence is coordinated by means of a control circuit and is derived from a clock frequency. During the actual integration time, the analog variable (voltage) to be converted lies at the input of the integrally discharged integrator. The charge taken during this time is proportional to the analog value (to the voltage) at the input. Therefore, the duration of the

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Abintegration with a constant analogue reference (reference voltage) equal to the full scale value of the analogue quantity to be converted (voltage) and of opposite polarity proportional to the magnitude of this input analogue voltage (voltage) · The duration of the integration is measured in a time interval meter consisting of gate and counting circuit with clock, as the equivalent of the analog input value determined and displayed. Since both the gate opening time and the counting frequency and the up and the Abintegrationszeit are derived from the same clock generator, there is no implementation error in this regard · Similarly, the implementation error is kept low, that the same evaluation circuit (integrator) is used within the integrator for the input variable and the reference variable, ie the same integrator resistor for voltage measurement. Differences in the switching-through resistances can be reduced by fine adjustment, so that the conversion steepness with negligible zero-point error theoretically depends almost exclusively on the reference variable, which is equal to the maximum input variable to be converted (full-scale value).

A disadvantage is the great influence of imperfect resistance properties (temperature coefficient, aging) for the provision of the reference variable (voltage) as a final value of the primary reference value (voltage), which arises directly on a primary reference component (for example, a reference Zener diode) the accuracy of the AD implementation.

Object of the invention

The aim of the invention is to reduce the influence of imperfect resistance properties in the two-flank AD conversion.

Explanation of the essence of the invention

The object of the invention is to provide a two-flank AD converter in which dominant resistances with respect to the conversion accuracy are not required.

According to the invention by a two-flank AD converter, consisting of an integrator / comparator, an analogue switch with an input switch and a reference switch, an analog reference source, a clock generator, a control circuit and an up counter, optionally with a secondary display, and further characterized by an integration time and an integration time are achieved. A reference voltage connected to the reference switch which is measurable at an output of the analogue reference source is equal to a primary reference voltage measurable directly at a primary reference component a first output of the control circuit for controlling the Aufintegrationszeit and a second gate circuit having a second output of the control circuit for controlling the Abintegrationszeit and a comparator output d he integrator / comparator connected, both gate circuits are connected to the clock generator. The up counter is connected via its reset input to a third output of the control circuit. An input side connected both at a data output of the forward counter and at a reference output of a digital reference source, the reference digital value numerically equal to the voltage value of the primary reference voltage, connected equivalent circuit is in terms of their initial output with a S expensive input of the control circuit connected.

..-. * - 238639

It is expedient to arrange a programmable integrated Pestwertspeicher as a digital reference source.

By adapting the reference digital value and thus - at a constant clock frequency - the Aufintegrations · "time to the immediate numerical value of the primary reference voltage produced in the analog reference source no resistance-dependent impairment of the reference voltage and thus the Umsetzungskennlinie the two-flank AD converter« For this purpose, the up counter The integration time is terminated at the moment when the equality of the up-counter reading and the reference digital value is signaled to the control circuit via the initial output of the equivalent circuit. · After the resetting of the up-counter, the time-out begins, the duration of which depends on the charge of the integrator and thus dependent on the average value of the input voltage during the Aufintegratiohszeit jst and is terminated at complete integrator discharge by a signal voltage at the comparator output.

The solution according to the invention for a two-flank AD converter has the advantage of high conversion accuracy, which is uninfluenced by resistance properties, with little circuit complexity.

AusführungsbeJ3piel

The invention will be explained in more detail below using an exemplary embodiment. The accompanying drawing shows an advantageous embodiment of the solution according to the invention for two-flank AD conversion as a block diagram.

238639

Between a circuit input 1 for an input voltage TJx and an input 5 of an integrator / comparator arrangement 4, an input switch 3, which is controlled by a first control line 10 from a first output 13 of a control circuit 11, is arranged. A reference switch 7 connects - controlled by a second control line 19 from the output of a UED gate 18 - the integrator 5 to an output 8 for a reference voltage UR an analog reference source 9 »The integrator / comparator 4 is - as well as the analog reference source 9 - with connected to the ground terminal connected to a reference potential 2. The reference voltage UR at the reference output 8 is equal to a primary reference voltage Uz, such as a high-constant Z-diode voltage, within the analog reference source 9. During an integration time TI, the input switch 3 is and during an integration time the reference switch 7 is closed and the other one is opened.

Between a Ecmpar atorausgang 6 for outputting a comparator voltage UK and a circuit output 32 for delivering an input voltage Uz proportional output digital value Da is a second - during the Abintegrationszeit open - gate 21 with a subsequent via an OR gate 22 and a counting input 24 connected upstream counter 23rd »Whose data output 28 is connected to the circuit output 32, arranged. The second gate 21 is on the input side further connected to an output 17 for outputting a clock frequency fo of a clock generator 16 and to a second output 12 of the control circuit 11 for limiting to a maximum Abintegrationszeit Tm. An output side connected to the OR gate 22. ; first gate switching. 20 is on, side of the first output 13 of the control circuit

and connected to the clock output 17. The UID gate is connected on the input side to the comparator output 6 and the second output 12.

An equivalent circuit 34 is the input side via a first input 26 to the circuit output 32 and via a second input 27 to a reference output of a digital reference source 30 for outputting a reference digital value DR and the output side via an initial output 29 for delivering an initial pulse I with a control input 15 of the control circuit 11th A third output 35 of the control circuit for outputting a reset pulse R is connected to a reset input 25 of the forward counter 23. The timing is due to the connection of a clock input 14 of the control circuit 11 with the clock generator 16 isochronous. At the circuit output 32, a display 33 is connected.

During the integration time TI loads the input. voltage Ux on the integrator. Subsequently, the deconvolution time, while being discharged with the reference voltage UE and terminated at the gullet crossing of the integrator charging signaled by the comparator voltage UK, depends on the amount of charge and thus on the time average of the input voltage Ux during the integration time TI measured in the form of a time interval measurement with the count of the forward counter 23 as the result »

Before the start of the integration time TI, the up-counter 23 is reset by means of a reset pulse R. During the integration time TI, clock pulses pass via the first gate circuit 20 and the OR gate 22 into the counting input 24 to the forward counter 23 at its data output 28

Digital value equal to the reference digital value DR. This equality triggers an initial pulse I in the equivalent circuit 34, which terminates the integration time TI via the control circuit 11. Before the start of the integration time, the forward counter 23 is also reset. This is followed by the integration voltage proportional to the input voltage Ux - limited to the maximum value Tm for a minimum AD conversion sequence - at which the clock pulses arrive via the second gate circuit 21 and the OR gate 22 in the counting input 24 and at their End - given by a jump of the comparator voltage UK - in the forward counter 23, the AD conversion result is and outputs as output digital value Da and is applied to the display 33. Re-conversion starts again with the initial reset of the up-counter 23.

At a constant clock frequency fo, the integration time TI is directly proportional to the primary reference voltage Uz. For this purpose, the reference digital value DR is to be adjusted in several digits to the numerical value of the primary reference voltage Uz, for example by means of a programmable plotting value memory (PROM) as a digital reference source 30. With known measures of time interval comparison, which ensure by changing the clock frequency fo that the integration time TI is a multiple a period of the mains frequency, the integration time TI is kept constant and the clock frequency fo becomes proportional to the primary reference voltage Uz due to the digital reference adjustment.

Measures for two-flank AD conversion of bipolar input voltages with output of the magnitude of the output digital value Da and the polarity are well known and directly applicable to the solution according to the invention; for example, by two oppositely directed reference voltages, two comparators, one count direction switch for the up / down counter at imlldurchgang, etc.

Claims (2)

- 8 Experience report 238839 A two-level AD converter for integrating AD conversion, consisting of an integrator / comparator arrangement, an analogue switch with an input switch and a reference switch, an analogue reference source, a clock generator, a control circuit and an up-counter, optionally with a secondary display, and further characterized by an integration time and an integration time characterized *** in that a reference voltage (UR) connected to the reference switch (7) measurable at an output (8) of the analogue reference source (9) is equal to a primary reference voltage (Uz) measurable directly on a primary reference component - that a counting input (24 ) of the forward counter (23) disjunctively via a first gate circuit (20) having a first output (13) of the control circuit (11) for controlling the Aufintegrationszeit (TI) and a second gate circuit (21) having a second output (12) the control circuit (11) for controlling the Abintegrationszeit and to a comparator output (6) of the integrator / comparator (4) is connected, wherein both gate circuits (20; 21) are connected to the clock generator (16) that the forward counter (23) via its reset input (25) to a third output (35) of the control circuit (11) is connected and that an input side both at a data output (28) of the forward counter (23) and to a Em reference output (31) of a digital reference source (30) whose reference digital value (DR) is equal to the voltage value of the primary reference voltage (Uz), connected Xquivalenzschaltung (34) with respect to their initial output (29) with a control input (15) of the control circuit (11 ) connected is· -9 - £ 0 O Ό ό 3 2. Two-flank AD converter according to item 1, g e k e η η-characterized in that a programmable integrated pest value memory (PROM) is arranged as the digital reference source (30). For this 1 page drawings