DD154244B1 - MEMORY ARRANGEMENT WITH ERROR IDENTIFICATION AND DIAGNOSTIC PROPERTIES, PREFERABLY FOR MICROORCHNERS - Google Patents

Description

Field of application of the invention

The invention relates to a memory arrangement with error detection and Diagnoseeiaenschaften, preferably as program and data memory in microcomputers, d. H. in computer arrangements based on commercially available microprocessor circuits, is provided.

Characteristic of the known technical solutions

It is known to provide additional bits for error detection in memory arrays in each memory cell in order to achieve an error check. The simplest case is to extend the memory by one bit per memory cell to perform a parity check. The preference for odd parity is preferred. For greater error safety, multiple parity bits are provided. Circuits are also known which, with the arrangement of a corresponding number of parity bits and a suitable choice of the memory data bits included in the parity check, permit the correction of one or more defective bits.

Such arrangements have been used for some time for computers and other information handling equipment, and they are well described in the literature. Corresponding representations can be found, for example, in the Hewlett-Packard Journal, October 1978, pp. 23-27.

For diagnosing information processing systems using memory arrays, it is known to arrange devices which provide information about whether a particular memory cell or a range of memory cells has been accessed or not. This may, for example, be implemented as an arrangement of comparison circuits which compare the current memory address with fixed values and provide coincidence-corresponding signals (DWP 75 162). While in larger and medium-sized systems such devices are usually permanently installed, this is usually too expensive in microcomputer systems. Therefore, these devices exist in externally connectable form for service purposes, both as service devices or operating units that are tailored to a particular system, as well as universal logic analyzers. This is also the use of RAM memory elements for comparison purposes and of microprocessors for controlling the various operations known and described for example in the Hewlett-Packard Journal, January 1977, p 8-9. Another principle, especially in microcomputers, realizes the desired reaction in the coincidence case by inserting special jump instructions at the required points (software breakpoints). The disadvantage of the known switching means is their effort, which forces in microcomputer systems to the described separation (in the form of external service equipment) in order to realize the system itself cost-effective. Of course, a separate service device is a disadvantage for the service and maintenance friendliness of the system, since the required connections must be made manually. In addition, the service device must always be available. In particular, the disadvantage of the external service device shows when the system itself is relatively complex (such as an array of multiple microcomputers) and when the requirements for service and maintenance times are critical (such as important devices within a computer system).

Software processes are much cheaper, but have only a certain scope. Thus, in principle only controls the command read accesses are possible if the real-time conditions are still to be met. For more complex controls, the program duration is extended by several orders of magnitude. However, this is not acceptable for many real-time applications.

-2- 225 072

Aim of the invention _y

The object of the invention is to provide a memory device which allows error detection during ongoing operation and which, on the other hand, permits comparison control for diagnostic purposes, with the additional expense involved being so small that the device can be successfully used in microcomputer systems as well.

Essence of the invention

The object of the invention is to provide a memory arrangement in which known principles of error checking during normal operation (such as a parity check) are realized and which enables comparator tests (eg address comparison) for diagnostic purposes with very little additional effort. An alternative use of the two operating modes is considered sufficient. In addition, it should be possible that operation, mode selection, etc. can be made by the controlling device (eg a microcomputer) itself.

The shortcomings of the known solutions are due to the fact that the means for error checking and comparison tests are designed as completely separate circuit arrangements, the circuit complexity, especially for the facilities for comparison tests is considerable (for the logic circuits themselves, for the adaptation to the testing device and the means of operation).

According to the invention the object is achieved in that between the data input of the additional read / write memory and the Prüfsignalgeneratorschaltung a selection circuit is arranged that the Datenaüsgang the additional read / write memory in addition to the Prüfsignalkontrollschaltung a condition signaling circuit is connected to the write pulse input of the additional read / write memory a Upstream of which the Schreibimpulsleituhg the actual information memory and a first and second control line are connected, connected to the selection circuit, the output of the Prüfsignalgeneratorschaltung and the first control line and a third control line and the second control line, that the first control line connected to the Prüfsignalalkonschaltung is that a fourth control line is connected to the enable input of the condition signaling circuit and that said Control lines are connected to program programmable registers.

The solution is further characterized in that the additional read / write memory has an access width of several bits, of which only a part is connected to the condition signaling circuit and that the actual information memory is connected on the input side directly and output side via an output register to the data bus of a microcomputer, in that the test signal generator circuit is a parity generator, that the test signal control circuit is a parity tester, that the error register and the control register are connected to the data bus, that the error signalisation circuit is followed by an external error signal line and that the Bedihgungssignalisierungsschaltung with an interrupt (interrupt) input of the CPU of the microcomputer and an external signal line is connected.

embodiment

In the following embodiment show:

1 shows the block diagram of a microcomputer with the memory arrangement according to the invention

2 shows details of the connection of the memory arrangement according to the invention

Fig. 3: Details of the embodiment of the condition signaling circuit

Fig. 4: Details of the execution of the error signaling circuit.

Fig. 1 shows how the memory device according to the invention is used in the context of a practically common microcomputer configuration.

The actual information memory 1 is addressed by the connected device 3, and its data inputs and outputs are also connected to the connected device 3. The access width of the information memory 1 corresponds to that of the connected device 3. In addition, a read / write memory 4 (hereinafter referred to as RAM 4) is provided. This is addressed in parallel to the information memory 1. His Schreibimpuls- and data inputs a selection circuit 5 is connected upstream; which in turn is connected to control registers 7 of the connected device 3 and to a test signal generator circuit 6. The Prüfsignalgeneratorschaltung 6 provides test signals on the type of parity control or even an error-correcting code. By appropriate assignment of the control register 7, one of three options can be selected in each case to enter information into the RAM 4 during write access to the information memory 1:

a) The output signals of the Prüfsignalgeneratorschaltung 6 are written.

This is the normal operating condition in which the data in the information memory 1 is monitored by additional control bits (parity bits or bits of the error-correcting code).

b) Special information from the control registers 7 is written. This is the case when the arrangement is switched to the "comparison stop" mode.

c) No write accesses are performed for RAM 4. This is the case when the device is operated in the "compare stop" mode.

On the output side, the arrangement of information memory 1 and RAM 4 is followed by a test signal control circuit 8 which is connected to an error signaling circuit 10. The test signal control circuit 8 performs a check of the read information by both the data bits of the information memory 1 and the RAM 4 are evaluated, again in the manner of parity control or an error correcting code. Furthermore, RAM 4 is followed by a condition signaling circuit 11. Both signaling circuits 10; 11 are controlled by special signals from the control registers 7. This results in the following possibilities:

a) The error signaling circuit 10 is activated. This is the normal operating condition in which the data in the information memory 1 is monitored by additional control bits (parity bits or bits of the error-correcting code).

-3- 225

b) both signaling circuits 10; 11 are inactive. This is the case when the operating mode of the arrangement is changed (from parity check to compare stop or vice versa).

c) The condition signaling circuit 11 is active. This is the case when the device is operated in the "compare stop" mode.

The arrangement is therefore based on the principle of using additional memory elements, which are used in a known manner for the purpose of controlling the stored information, alternatively to perform diagnostic functions by a "comparison stop" mode, for which the additional memory elements are in the respective positions These bit patterns are evaluated by the condition signaling circuit 11 when operating in this "compare stop" mode. If, for example, it is to be checked whether a write access is made to the address 2531, then a corresponding bit pattern is to be entered into the relevant position in RAM 4. Upon access to the specified address, this is detected by the condition signaling circuit 11.

The alternative use of the RAM 4 requires that for switching between the two modes of normal operation must be interrupted for a short time. However, this is not a limitation for most practical applications. Usually, in normal operation, control of the stored information (eg, by parity check) will be turned on. For troubleshooting purposes, however, the "compare stop" mode can often be used to advantage, since troubleshooting is typically manual intervention and is a non-standard mode of operation, so the required interruption of operation is usually meaningless Memory arrangement in the context of microcomputer configurations or the like, the changeover of the modes can usually be accomplished by programs housed in other memory media, the fact that, when operating in the "compare stop" mode, the reliability of the operation becomes less due to the lack of control, is also generally negligible, taking into account the inherently high reliability of microelectronic devices and the comparatively small time portion of the diagnosis over the entire operating life of the device.

If the RAM 4 contains multiple bits in each position, for example, to accommodate error correcting code, it is possible to use some bits for the comparison stop conditions and some for a reduced form of information control (such as for a parity check) in the "compare stop" mode use

 Example:

- Access width of the information memory 1:16 bits

- Access width of RAM 4: 5 bits

- Usage in normal mode: 5 bits error correction code

Assignment in "comparison stop" mode: 3 bits comparison condition, 2 bits parity check (each 1 parity bit for 8 information bits) In the following a specific embodiment will be described in more detail, in which the connected device 3 is a microcomputer, as shown in FIG. 1 is already indicated in detail The microcomputer itself constitutes a common arrangement of CPU 14, ROM 16 and timer circuits CTC 19 and serial and parallel input / output circuits SIO, PIO 21, 22, which are implemented as MOS LSI circuits are connected to each other via a data bus 2, an address bus 17 and control lines 18.

The address bus 16 has a width of 16 bits and the data bus 2 one of 8 bits. The memory arrangement is likewise connected to these line systems. In this case, an output register 12 is connected between the output of the information memory 1 and the data bus 2.

In addition, the control register 7 and an error register 9 are connected to the data bus 2. Registers 7; 9 are further connected to parts of the address bus 17 and the control lines 18 so that the control registers 7 can be written by programs and that the error register 9 can be read by programs. The information memory 1 is a read / write memory with a capacity of 32 kbytes. It will also be called RAM in the following. RAM 4 has a capacity of 32 kbit, d. H. each position occupies one bit. Thus, a parity check is possible, so that the Prüfsignalgeneratorschaltung 6 are formed as a parity generator and the test signal control circuit 8 as a parity checker. For a more detailed explanation, FIG. 2 shows further details of the connection of the memory arrangement, in particular the design of the selection circuit 5 and the assignment of the control registers 7. The control registers 7 contain 2 bytes, which can be loaded individually programmatically. Only a few bits are occupied to control the memory arrangement, the remaining bits are used for other purposes. The control registers 7 are flip-flop registers, at whose outputs the relevant control lines are directly connected. ,

Meaning of the control signals:

- ENABLE PARITY. The parity control mode is on. The signal causes the output signal of the parity generator 6 to be turned on to the data input of the RAM 4 and, during write operations, also receives RAM 4 write pulses from the WRITE PULSE line.

- ENABLE ERROR SIGNALIZATION. It is allowed that the error signaling circuit 10 outputs an external error signal.

- ENABLE COMPARE STOP. In this mode, ENABLE PARITY must be inactive, so that no write pulses are sent to RAM 4. RAM 4 is only read, and the information is evaluated in the condition signaling circuit 11.

- ENABLE INJECT. This is the mode change mode. It is allowed that the occupation of the line INJECT HIGH is taken over in the RAM 4 via the selection circuit 5 (in write accesses).

- FORCE EVEN PARITY / INJECT HIGH. This bit is used twice:

a) If ENABLE PARITY is active, parity generator 6 is switched to the generation of even parity check bits (the normal mode is the odd parity). Parity checker 8 must always signal errors. This signal thus serves to check the functionality of the parity check. It can, for. B. be used in the context of diagnostic programs.

b) If ENABLE INJECT is active, the assignment of this bit is transferred to the RAM 4 during write accesses.

- STOP ON READ. STOP ON WRITE. These two bits are meaningful only when ENABLE COMPARE STOP is active. They control the evaluation of the comparison stop condition in the condition signaling circuit 11.

For the meaning of the further control signals in FIG. 2:

WRITE PULSE is the write pulse for the RAMs 1; 4, which is supplied by the general controller of the microcomputer at every write access.

-4 225 072

PARITY CHECK is the error signal of the parity checker 8, which is generated only if the parity check is allowed and if the microcomputer accesses the RAM (signal RAM ACCESS from the general control of the microcomputer). 3 shows a detailed embodiment of the condition signaling circuit 11. It outputs the following output signals which are each supplied by a flip-flop:

COMPARE STOP. This is a pulse that is output to the external signal line 15 when the "comparison stop" condition is satisfied in one cycle.

NMI. This is an interrupt signal for the CPU 14 which is also asserted when the "compare stop" condition is met

NMI IN PROGRESS. This signal indicates that an interrupt to the treatment of a "compare stop" condition from the

CPU 14 is being processed.

The "comparison stop" condition can be evaluated in two different ways:

a) by signaling to the outside, z. B. for a visual display. For this purpose, a pulse COMPARE STOP is given on line 15.

b) from the CPU 14 of the microcomputer itself. For this purpose, an interruption is triggered, which starts an evaluation program, which is accommodated in the ROM 16. The interrupt must be given priority by the CPU 14. To do this, many of the common microcomputer circuits have an input for a "non-maskable interrupt" (NMI), which is energized by the NMI line.

In addition to the signals already described, the following signals are also processed from the general control circuits of the microcomputer:

READ OPERATION. The signal indicates that a read cycle is being executed with RAM 1 and RAM 4.

WRITE OPERATION. The signal indicates that a disk cycle is being executed with RAM 1 (a read cycle is being executed simultaneously with RAM 4).

CYCLE RUNNING. The signal indicates that the microcomputer is executing a memory cycle.

NMI ENABLE. The signal indicates that the handling of the "compare stop" condition is performed by the CPU 14 itself NMI DONE.

The signal is programmatically activated by the CPU 14. It indicates that the CPU 14 has finished handling the "compare stop" condition.

NMI ACTION. The signal indicates that the CPU 14 has accepted the interruption.

A "compare stop" condition is detected when a "1" is read from RAM 4 (via the RAM OUTPUT 8 line) in the current cycle and the respective control register bits are set.

ENABLE COMPARE STOP must always be active. If a stop is required for read accesses, STOP ON READ must also be set. Accordingly, STOP ON WRITE must be set if a stop is required during write accesses.

FIG. 4 shows details of the error signaling circuit 10 and the error register 9.

About the error register 9 programs in the CPU 14 error signals from the entire microcomputer programmatically query. It is indicated in Fig. 4 that in addition to the already described parity error signal PARITY CHECK other error signals are routed to the error register 9. Also there is the signal NMI connected in PROGRESS. This is used for status analysis during error handling. The error signaling circuit 10 supplies the external error signal ERROR on the error signal line 13, if permitted by the control signal ENABLE ERROR SIGNALIZATION. The error signal ERROR is kept active by a flip-flop until a reset (signal RESET) is triggered in the microcomputer. Important to the way in which errors are handled is the fact that microcomputers commonly co-operate with other devices in real-time operation. Thus, extensive error action programs (such as in computer systems) make little sense. Rather, it is a matter of informing the other institutions of the error in order to prevent serious malfunctioning by an emergency measure. Thereafter, a general reset is usually required.

The switching between the modes can be done by the CPU 14. For this purpose, corresponding programs are stored in the ROM 16.

Algorithm for switching to the "comparison stop" mode:

- Delete ENABLE PARITY. , -ENABLE INJECT

Delete INJECT HIGH

- Read all memory locations in RAM 1 one after the other and rewrite them. At the same time 4 zeros are entered into the RAM.

Set -ENABLE INJECT

- Read and rewrite all memory locations for which a comparison stop is desired. Here are entered in these positions in the RAM 4 ones.

- Delete ENABLE INJECT

- Set ENABLE COMPARE STOP

- If desired, set STOP ON READ or STOP ON WRITE or both

- Start desired function Algorithm for returning to parity check:

- Delete ENABLE COMPARE STOP - delete INJECT HIGH

- Delete ENABLE ERROR SIGNALIZATION

- Set ENABLE PARITY

- Read and rewrite all memory locations one after the other

- set ENABLE ERROR SIGNALIZATION, '

- Start the desired function.

Claims (4)

1. A memory arrangement with error detection and diagnostic features, preferably for microcomputers, in which an additional read / write memory is arranged parallel to the actual information memory, which is connected to test signal circuits (eg for parity control) and means for performing an address comparison. characterized in that between the data input of the additional read / write memory (4) and the Prüfsignalgeneratorschaltung (6) a selection circuit (5) is arranged, that at the data output of the additional read / write memory (4) next to the test signal control circuit (8) a condition signaling circuit ( 11), that the write pulse input (WE) of the additional read / write memory (4) is preceded by a gate, to which the write pulse line of the actual information memory (1) and a first and second control line (ENABLE PARITY, ENABLE INJECT) are connected ß to the selection circuit (5) the output of Prüfsignalgeneratorschaltung (6) and the first control line (ENABLE PARITY) and a third control line (INJECT HIGH) and the second control line (ENABLE INJECT) are connected, that the first control line (ENABLE PARITY) to the test signal control circuit (8) is connected, that a fourth control line (ENABLE COMPARE STOP) is connected to the enable input of the condition signaling circuit (11) and that said control lines are connected to programmatically loadable registers (7). -1- 225 Invention claim: 2. Arrangement according to item 1, characterized in that the additional read / write memory (4) has an access width of several bits, of which only a part of the Conditionsignaiisierungsschaltung (11) is connected. 3. Arrangement according to item 1, characterized in that the actual information memory (1) on the input side directly and the output side via an output register (12) to the data bus (2) of a microcomputer (3) is connected, that the additional read / write memory (4) an access width of one bit has the check signal generator circuit (6) being a parity generator, the check signal control circuit (8) being a parity checker, the error register (9) and the control register (7) being connected to the data bus (2) Error signaling circuit (10) is followed by an external error signal line (13) and that the condition signaling circuit (11) with an interrupt (interrupt) input of the CPU (14) of the microcomputer (3) and an external signal line (15) is connected. For this 4 pages drawings