DD154244A1 - MEMORY ARRANGEMENT WITH ERROR IDENTIFICATION AND DIAGNOSTIC PROPERTIES, PREFERABLY FOR MICROORCHNERS - Google Patents

Abstract

Allowing for error checking and comparison checks for diagnostic purposes with little effort. Alternative use of known principles of error checking for comparison testing (e.g., address comparison) for diagnostic purposes. Parallel to the actual information memory, an additional read / write memory is arranged, which is preceded by a selection circuit which is connected to a Pruefsignalgeneratorschaltung and with control registers. The memory arrangement is followed by a test signal control circuit whose outputs are connected to an error register and an error signaling circuit. The additional memory is followed by a condition signaling circuit connected to outputs of the control registers and to inputs of the error register.

Description

-λ- 2 25

Title of the invention

Memory arrangement with error detection and diagnostic properties, preferably for microcomputers

Field of application of the invention

The invention relates to a memory arrangement with error detection and diagnostic properties, preferably as a program and data memory in microcomputers, d. H. in Rechnan ranordnun conditions based on commercially available microprocessor circuits, is provided.

Characteristic of the Known Technical Solutions It is known to provide additional bits for error detection in memory arrangements in each memory cell, in order to thereby achieve an error check. The simplest pail is to extend the memory by one bit per memory cell to perform a parity check. The preference for odd parity is preferred. For greater error security, several parity bits are provided. Circuits are also known which, with the arrangement of a corresponding number of parity bits and a suitable choice of the memory data bits included in the parity check, permit the correction of one or more defective bits. Such arrangements have been used for some time for computers and other information handling equipment, and they are well described in the literature. Corresponding representations can be found, for example, in Hewlett-Packard-Journal, October 1978, pp. 23-27. For the diagnosis of information processing systems, the

Using memory arrays, it is known facilities

This may, for example, be implemented as an arrangement of comparison circuits which compare the current memory address with fixed values and signals corresponding to coincidence deliver (DYfP 75 162). While in larger and medium-sized systems such devices are usually permanently installed, this is usually too expensive in microcomputer systems. Therefore, these devices exist in externally connectable form for service purposes, both as service devices or operating units that are tailored to a particular system, as well as universal logic analyzers. This is also the use of RAM memory elements for comparison purposes and of microprocessors for controlling the various operations known and described for example in the Hewlett-Packard Journal, January 1977 »S * 8 - 9 described. Another principle, especially in microcomputers, realizes the desired reaction in the coincidence case by inserting special jump instructions at the required points (software breakpoints). The disadvantage of the known switching means is their effort, which forces in microcomputer systems to the described separation (in the form of external service equipment) in order to realize the system itself cost-effective. Of course, a separate service device is a disadvantage to the service and maintenance friendliness of the system because the required connections must be made manually. In addition, the service device must always be available. In particular, the disadvantage of the external service device shows when the system itself is relatively complex (such as an array of multiple microcomputers) and when the requirements for service and maintenance times are critical (such as important devices within a computer system).

Software processes are much cheaper, but have only a certain scope. Thus, in principle only controls the command read accesses are possible if the real-time conditions are still to be met. For complex ·

225 072

The duration of the program will be extended by several orders of magnitude. However, this is not sustainable for many real-time applications ·

Object of the invention

The object of the invention is to provide a memory arrangement which allows fault detection during operation and which, on the other hand, permits comparison checks for diagnostic purposes. The additional effort required should be so low that the arrangement can be successfully used in microcomputer systems.

Essence of the invention

The object of the invention is to provide a memory arrangement in which known principles of error checking during normal operation (such as a parity check) are realized and which enables comparisons (eg address comparison) for diagnostic purposes with very little additional effort. An alternative use of the two operating modes is considered sufficient. In addition, it should be possible that operation, mode selection, etc. can be made by the controlling device (eg, a microcomputer) itself. The deficiencies of the known solutions are due to the fact that the means for error checking and comparison tests are designed as completely separate circuit arrangements, the circuit complexity is particularly considerable for the devices for comparison tests (for the logic circuits themselves, for adaptation to the * 'device to be tested and the means of operation). According to the invention, the object is achieved in that an additional read / write memory is arranged parallel to the actual information store with an access path corresponding to the data path of the connected device, preceded by a selection circuit connected to a

Prüfsignalgeneratorschaltung and connected to outputs of control registers, that the entire memory device is followed by a Prüfsignalalktrollschaltung whose outputs are connected to an error register and a Fehlersignalisierungsschaltung and that the additional read / write memory is followed by a condition signaling circuit connected to outputs of the control register and to inputs of the error register connected. The solution is further characterized in that the additional read / write memory has an access width of several bits, of which only a part of the condition signal; Sierungsschaltung is connected and that both the Prüfsignalgeneratorschaltung and the test signal control circuit are designed so that they can be switched to different test algorithms that require a different number of check bits, and that the actual information storage on the input side directly and output side connected via an output register to the data bus of the microcomputer in that the additional read / write memory has an access width of one bit, the check signal generator circuit is a parity generator, the check signal control circuit is a parity checker, the error register and the control register are connected to the data bus, and the error signalization control is followed by an external error signal line and that the condition signaling circuit is connected to an interrupt signal of the CPU of the microcomputer and an external signal line.

embodiment

In the following embodiment show:

1 shows the block diagram of a microcomputer with the memory arrangement according to the invention

Fig. 2 details of the connection of the memory device according to the invention

Fig. 3 Details of the embodiment of the condition signaling circuit

Fig. 4 details the execution of the error signaling circuit.

225 072

Pig · 1 shows how the memory arrangement according to the invention is used in the context of a practically frequently occurring microcomputer configuration.

The actual information memory 1 is addressed by the connected device 3, and its data inputs and outputs are also connected to the connected device 3. The access width of the information memory 1 corresponds to that of the connected device 3. In addition, a read / write memory 4 (hereinafter referred to as RAM 4) is provided »This is addressed in parallel to the information store T.» His Schreibimpuls- and data inputs is preceded by a selection circuit 5, which in turn is connected to control registers 7 of the connected device 3 and to a test signal generator circuit 6. The Prüfsignalgenera gate circuit 6 provides test signals on the type of parity control or even an error-correcting code. By appropriate assignment of the control register 7, one of three options can be selected in each case to enter information into the RAM 4 during write access to the information memory 1:

a) The output signals of the Prüfsignalgeneratorschaltung 6 are written.

This is the normal operating condition in which the data in the information memory 1 is monitored by additional control bits (parity bits or bits of the error-correcting code).

b) Special information is entered from the tax registers. This is the Pail, when the assembly is shifted to the ^{M n} comparison Stop mode.

c) No write accesses are performed for RAI ₁ I 4. This "* is the Pail when the device is operated in the comparison stop ^M mode.

On the output side, the arrangement of information memory 1 and RAM 4 is a; The test signal control circuit 8 performs a check of the read information by both the data bits of the information memory 1 and the RAM 4 are evaluated, again in the manner of parity control or a

error-correcting code · Furthermore, RAM 4 is followed by a condition signaling circuit 11 · both signaling circuits 10; 11 are controlled by special signals from the control registers 7. This results in the following possibilities:

a) The Pehlersignalisierungsschaltung 10 is activated. This is the normal operating case in which the data in the information memory 1 are monitored by additional control bits (parity bits or bits of the error-correcting code).

b) both signaling circuits 10; 11 are inactive. This is the Pail when the operating mode of the arrangement is changed (from parity check to compare stop or vice versa).

c) The condition signaling circuit 11 is active.

This is the pail when operating the array in the "compare stop" mode.

The arrangement is thus based on the principle of using additional memory elements which are used in a known manner for the purpose of controlling the stored information, alternatively to carry out diagnostic punctures by means of a comparison stop ⁿ mode, for which purpose the additional memory elements are in the respective positions loaded with characteristic bit patterns. These bit patterns are evaluated when operating in this ⁿ Vergleichssop "mode on the condition signaling circuit 11. If, for example, it is to be checked whether a write access is made to the address 2531, then a corresponding bit pattern must be entered at the relevant position in. RAM 4. Upon access to the specified address, this is detected by the condition signaling circuit 11.

The alternative use of the RAM 4 requires that for switching between the two modes of normal operation must be interrupted for a short time · This is not a limitation for most practical applications. Typically, the control of the stored information (for example, by parity checking _e) will be turned on in normal operation *

225 072

For purposes of debugging, however, the ^w Vergleichsstop ⁿ mode can often be used advantageously. Since troubleshooting is usually associated with manual intervention and is a non-standard mode of operation, the required interruption of operation is usually meaningless. When using the memory array in the context of microcomputer configurations or the like, the conversion of the operating modes can usually be accomplished by programs that are housed in other storage media. The fact that the reliability of the operation is low when operating in the ^w compared Stop "mode because of the lack of control is also generally negligible when considering the high per se reliability of microelectronic devices and the relatively low proportion of time of diagnosis of the total operating time of the Arrangement considered ·

If the RAM 4 contains several bits in each position, for example to record an error-correcting code, it is possible to use some bits for the comparison stop conditions in ⁿ comparison stop mode and some for a reduced form of the information control (for instance for a parity check). to use

 Example:

- Access width of the information memory 1: 16 bits

- Access width of RAIvI 4: 5 bits

- Usage in normal mode: 5 bits error correction code

- assignment in "Comparison ⁿ Stop Mode: 3 bits comparison condition,

2 bits parity check (each 1 parity bit for 8 information bits), In the following, a special embodiment will be described in more detail, in which the connected device 3 is a microcomputer, as already indicated in detail in Fig. 1. The microcomputer itself constitutes a common arrangement of CPU 14, ROM16, and ⁵ timer circuits CTC 19 and "serial and parallel I / O circuits SIO, PIO 21, 22 which are referred to as"

MOS LSI circuits are executed. The devices are interconnected via a data bus 2, an address bus 17 and control lines 18.

The address bus 16 has a width of 16 bits and the data bus 2 one of 8 bits. The memory arrangement is likewise connected to these line systems. In this case, an output register 12 is connected between the output 'of the information memory 1 and the data bus 2. ,

In addition, the control register 7 and an error register 9 are connected to the data bus 2. Registers 7; 9 are further connected to parts of the address bus 17 and the control lines 18 so that the control registers 7 can be written by programs and that the error register 9 can be read by programs. The information memory 1 is a read / write memory with a capacity of 32 kbytes. It will also be referred to as RAM in the following. RAlI 4 has a capacity of 32 kbit, d. H. each position occupies one bit. Thus, a parity check is possible, so that the Prüfsignalgeneratorschaltung 6 are formed as a parity generator and the test signal control circuit 8 as a parity checker. For a more detailed explanation, FIG. 2 shows further details of the connection of the memory arrangement, in particular the embodiment of the selection circuit 5 and the assignment of the control registers 7. The control registers 7 contain bytes which can be loaded individually in terms of program technology. Only a few bits are occupied to control the memory arrangement, the remaining bits are used for other purposes. The control registers 7 are flip-flop registers, at whose outputs the relevant control lines are directly connected. Meaning of the control signals:

- EUABLE PARITY. The parity control mode is on. The signal causes the output signal of the parity generator 6 to be turned on to the data input of the RAM 4 and, in the case of writes, also receives RAM 4 write pulses from the YfRITE PULSE line.

_9_ 225 07a

- ENABLE ERROR SIGNALIZATION. The error signaling circuit 10 is allowed to output an external error signal.

- MABLE COlIPARE STOP. The comparison ^w Stop "mode is turned on. In this mode ENABLE PARITY must be inactive. To allow any write pulses to RAM 4. RAM 4 is read only, and the information is evaluated in the condition signaling circuit 1t.

- ENABLE INJECT. This is the mode of operating mode changeover. It is permitted that the assignment of the INJECT HIGH line to the RAL ¹ I 4 is accepted via the selection circuit 5 (for write accesses),

-FORCE EVEN PARITY / INJECT HIGH. This bit is used twice:

a) If ENABLE PARITY is active, parity generator 6 is switched to the generation of even parity check bits (the normal mode is the odd parity). Parity checker 8 must always signal errors. This signal thus serves to check the functionality of the parity check. It can, for. B »be used in the context of diagnostic programs.

b) If ENABLE INJECT is active, the assignment of this bit is transferred to the RAM 4 during write accesses.

STOP ON READ, STOP ON MITE. These two bits are only meaningful if ENABLE COLIPARE STOP is active. They control the evaluation of the comparison stop condition in the. Condition signaling circuit 11.

Regarding the meaning of the further control signals in FIG. 2: V7RITE PULSE is the write pulse for RAIiIs 1; 4, which is supplied by the general controller of the microcomputer at every write access.

PARITY CHECK is the error signal of the parity checker 8 which is only generated if the parity check is allowed and if the microcomputer is accessing the RAM (signal RAM'ACCESS from the general control of the microcomputer).

225 072

Pig · 3 shows the detailed design of the condition signaling circuit 11 · It outputs the following output signals, which are supplied by a respective flip-flop: COlCPARE STOP. This is a pulse that is output to the external signal line 15 when the "compare stop ^M condition" is satisfied in one cycle.

MI, This is an interrupt signal for the CPU 14 which is also asserted when the ⁿ comparison stop condition is met.

UMI IN PROGRESS. This signal indicates that an interrupt is being processed by the CPU 14 to handle a ^tt compare stop condition.

The ^tt comparison stop condition can be evaluated in two different ways:

a) by signaling to the outside, z. B. for a visual display. For this purpose, a pulse COMPARE STOP is given on line 15.

b) from the CPU 14 of the microcomputer itself. For this purpose, an interruption is triggered, which starts an evaluation program, which is accommodated in the ROM 16. The interrupt must be given priority by the CPU 14. For this purpose, many of the usual microcomputer circuits have an input for a ^n- maskable interrupt "(Ulli) which is energized by the NMI line.

In addition to the signals already described, the following signals are also processed from the general control circuits of the microcomputer:

READ OPERATION. The signal indicates that a read cycle is being executed with RAM 1 and RAIi 4. ,

T / RITE OPERATION. The signal indicates that a write cycle is being executed with RAM 1 (a read cycle is being executed simultaneously with RALl 4).

CYCLE RUMING, The signal indicates that the microcomputer is executing a memory cycle

 NMI ENABLE, The signal indicates that the treatment of the

225 072

"Stop comparison is carried ^M -Bedingung by the CPU 14 itself. DOES MI. The signal is programmatically enabled by the CPU 14. It indicates that the CPU 14 has finished the treatment of the ⁿ comparison ^w Stop condition.

HMI ACTION. The signal indicates that the CPU 14 has accepted the interruption.

A compare stop ^w condition is detected when in the current cycle a 1 ^{t is} read from RAM 4 (via RAIi OUTPUT 8 line) and the respective control register bits are set.

ENABLE COMPARE STOP must always be active »If a stop is required for read accesses, STOP ON READ must also be set. Accordingly, STOP ON WRITE must be set if a stop is required during write accesses.

FIG. 4 shows details of the error signaling circuit 10 and the error register 9.

Via the error register 9, programs in the CPU 14 can interrogate error signals from the entire microcomputer in a routine manner. It is indicated in Fig. 4 that in addition to the already described parity error signal PARITY CHECK other error signals are routed to the error register 9. Also there is the signal NMI IN PROGRESS connected. This is used for status analysis during error handling. The Errorignslisierungsschaltung 10 provides the external error signal ERROR on the error signal line 13, if this is allowed by the control signal ENABLE ERROR SIGNALIZATION. The error signal ERROR is kept active by a flip-flop until a reset (signal RESET) is triggered in the microcomputer. Important for the way the error is handled is the fact that microcomputers usually work together with other facilities in real-time operation. Thus, extensive error action programs (such as in computer systems) make little sense. Rather, it is a matter of informing the other institutions of the mistake, of serious ones

Prevent malfunctions through an emergency measure · Afterwards, a general reset is usually required.

The switching between the modes can be done by the CPU 14 ₀ For this purpose, appropriate programs are stored in the ROM 16.

Algorithm for switching to the "comparison stop" mode:

- Delete ENABLE PARITY

- Switch on ENABLE INJECT

- Delete INJECT HIGH

- Read all memory locations in RAM 1 one after the other and rewrite them. At the same time 4 zeros are entered into the RAM.

- Set ENABLE INJECT

- Read and rewrite all memory locations for which a comparison stop is desired. Here, 4 positions are entered in these positions in the RAIi.

- Delete ENABLE INJECT

- Set ENABLE COIiIPARE STOP

- If desired, set STOP ON READ or STOP ON V / RITE or both

- Start the desired puncture

Algorithm for returning to parity check:

- Delete ENABLE COIiPARE STOP

- Delete INJECT HIGH

- Delete ENABLE ERROR SIGNALIZATION

- Set ENABLE PARITY

- Read and rewrite all memory locations one after the other

- Set ENABLE ERROR SIGNALIZATION

- Start the desired function.

Claims (1)

_ ₁₃ . 225 072 invention claim 1 memory device with Pehlererkennungs- and diagnostic properties, preferably for microcomputer, characterized in that parallel to the actual information memory (1) with the data path (2) of the connected device (3) corresponding access width, an additional read / write memory (4) is arranged , which is preceded by a selection circuit (5) which is connected to a Prüfsignalgeneratorschaltung (6) and outputs of control registers (7), that the entire memory device (1; 4) is followed by a test signal control circuit (8) whose outputs to an error register (9) and an error signaling circuit (10) are connected and that the additional read / write memory (4) a condition signaling circuit (11) is arranged downstream, which is connected to outputs of the control register (7) and to inputs of the error register (9). , " Arrangement according to item 1, characterized in that the additional read / write memory (4) has an access width of several bits of which only a part is connected to the condition signaling circuit (11) and that both the test signal generator circuit (6) and the Test signal control circuit (7) are designed so that they can be switched to different test algorithms that require a different number of check bits. 3 "arrangement according to item 1, wherein the connected device 'is designed as a microcomputer, characterized in that the actual information memory (1) on the input side directly and output side via an output register (12) on de.n data bus (2) of the microcomputer (3) is connected, that the additional read / write memory (4) has an access width of one bit, that the Prüfsignalgeneratorschaltung (6) is a parity generator, that the Prüfsignale control circuit (8) is a parity checker that the error register 225 072 (9) and the control register (7) are connected to the data bus (2), that the Pehlersignalisierungsschaltung (10) an external error signal line (13) is arranged downstream and that the condition signaling circuit (11) with an interrupt (interrupt) Singang the CPU (H) of the microcomputer (3) and an external signal line (15) is connected ο