DD136686B1 - PROGRAMMABLE INTEGRATED TIME CONTROL - Google Patents

Description

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Programmable Integratable Timing Circuit Scope of the Invention

The invention relates to a monolithic integrated timing control circuit which is suitable in connection with external passive and active actuatable components for programmable electronic timing devices of different time functions and variable very short to very long retardation times for devices and devices of control technology or for time relays.

Characteristic of the known technical solutions

S e ction s in the control or relay technology are designed mechanically, electromechanically or electronically according to the respective technical development status. All in all, a very large number of special designs have been produced, which can be read off from the production programs, of which only the electronic solutions are to be considered comparatively.

In the case of time-switching devices in control technology, a series of functions at the output have each acquired technical significance, which, based on the intended application, represent single-cell solutions. Thus, especially the astigmatic and the monostable output function dominate.

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In the case of time relays, on the other hand, in the analysis of the types occurring, the output functions of pull-in, drop-off, tilt and delay and modifications w, i оьсі are found. ijouxj. XLL с; χ σ ixu. oj.xj.CI üxcj. CI j. σ aLuiugj * u ^ u wj. 3 η, υ- fall delay. Ss are also often single-purpose solutions, but, in some devices, the pull-in and the drop-off delay are technically combined,

Different in both application groups are not only the output functions. Thus, time switching devices for the control technology with respect to the supply voltage to a single Systenispannung adapted while timers are to adapt a number of supply voltages to the circuit for generating the functions.

Another distinguishing feature is that the outputs of the solutions of both application groups are designed differently. In the case of time switching devices in the field of control technology, it is particularly important for the information technology to pass on the generated output functions, i. on small levels, on. In the case of time relays, on the other hand, the output consists of high-performance output elements of electromechanical or electronic embodiments.

Although further distinguishing features of both application groups exist, only the main distinguishing feature, the function or time structure, should be considered. In mechanical solutions, principles of energy use of tensioned springs or clockworks predominate as driving mechanisms. In the case of electromechanical solutions, these are motors, couplings, springs and combinations of these. These elements have advantages as well as a number of disadvantages, e.g. low wear resistance, difficult to modify, maintenance-intensive or not mass-produced economically.

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Following these considerations, electronic solutions are known which no longer have these disadvantages. So often two and sometimes more than two functions are realized in one arrangement. The most frequently used active principles are based on discrete analog circuits, such as the condensate charging and discharging in additionally modified evaluation circuits.

Even with the use of digital principles of action, the requirements regarding the feature of time formation can be met. Here, the use of integrated solid-state circuits is increasingly being observed. Find use. Combinations of solid-state circuits of different technologies, which are joined together with discrete electrical components to form corresponding Schalturgsanordnungen. However, the effort is quite large here.

In DE-OS 2 22 ^ - 734 a time-switching device is described which has a constant oscillating oscillator, a Impulszählteilerkette with a selector switch, a control block with reset circuit and an output block with power gates at a large variable delay time. The disadvantage here is the design for a function, i. the circuit is not programmable for different time functions.

DE-OS 2 737 325 further describes a circuit with integrated power supply.

In DE-OS 2 24-3 799 a time control circuit is described with a variable frequency oscillator. The advantage here is the simple change of the time range. Another disadvantage is the design for a function.

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Another disadvantage of the circuit disclosed in DE-OS 2 243 799 is that the pulse generation by an electronic generator over several decades with subsequently arranged fixed divider stages requires a generator that must work over a wide frequency range voltage and temperature stable.

For multi-range time relays or for time switching devices over large time ranges this means a circuit conversion with the 2Taehr rush, a cumbersome range switching, a readjustment of the frequency range and a complex temperature compensation of external circuit elements. Another disadvantage is that due to the nature of the divider stages used in conjunction with the switchover on the generator only strictly decadic times are obtained in the second dimension, and thus the usual and desired seconds, minutes or hours © in eilung on a scale unreachable is.

Another disadvantage is the fact that, although a high time-reproducibility, but no order of magnitude comparable Sinsteilgenauigkeit is achievable. The cause of this defect can be seen in the quality of the simple potentiometers used for economic and space reasons, which do not allow calibration »

Object of the invention

The object of the invention is to provide a one-time, in-variably and simply pre-programmable timing control circuit which is equally applicable to electronic control technology and electronic time relay applications, which have delay times of tenths of a second

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Provides constant external wiring up to days Ъеі and further provides several functions at the output, thereby signaling the expiration and the final state of the delay time.

Explanation of the essence of the invention

The invention has for its object to provide an integrated timing control circuit which includes an integrated Steueriogik so that a plurality of Funircionen can be realized with only one circuit. This eliminates the circuit conversion with the disadvantages of cumbersome range switching in the realization of electronic timing relay. Next is a bounce suppression by the control logic to be effective, so that the pulses resulting from the bouncing contacts are ineffective. An electronic subdivision of the relatively lye splitter кетгсе for measurement purposes to allow an examination of this circuit in the shortest possible time, so that the cost of the measurement remain low.

Sin fine adjustment of the oscillator frequency should be possible to use for economic reasons simple potentiometer for timing.

Features of the invention

The invention relates to a programmable integratable timing circuit with a large variable delay time and multiple time functions. In this case, the timing control circuit comprises a bounce-lock input block, a continuously oscillating oscillator, a pulse count-divider chain with a selector switch, a reset-block control block, and an output block with power gates.

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According to the invention, the output of an A2TD gate of the bounce suppression in the input block is fed to a first input of a gate of the pulse counter divider chain whose output is connected to the S input of a flip-flop in the control block. The respective selected via the selector output of the divider of the Zählzählteilerkette is connected on the one hand via a monoflop to the second input of the gate of the Impulszählteilerkette, on the other hand to the input of a first gate of the control block.

Furthermore, the outputs of the first gate and a second gate of the control block are linked in the output block by a gate.

Furthermore, the reset circuit is connected to the R input of a flip-flop of the bounce suppression.

Finally, the input block to the control block via the output of an inverter to the input of a third gate, via the output of a monoflop on the one hand to the S-Singang another flip-flop, on the other hand negated with a fourth and fifth gate and further negated with a sixth gate, and connected via the output of another monoflop over a seventh gate on the one hand with reinen eighth gate and on the other hand negated connected to each of a ninth and tenth gate.

Finally, programming inputs IA; 13; IC connected via true and negative outputs of a PLA via an eleventh gate to the seventh gate, to the third, sixth, seventh and eighth gates and the fourth, fifth, ninth and tenth gates. There are connections from the latch outputs of the PLA to the respective control input of the first, second gate and a twelfth and thirteenth gate in the control block.

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In an embodiment of the invention, the oscillator is connected in the control block on the one hand to the reset circuit and on the other hand via a fourteenth gate to the first divider of the Impulszälilteilerkette. Furthermore, the reset circuit is connected to the R inputs of the two flip-flops and a third flip-flop and the S-Singang a fourth flip-flop. Furthermore, the fourth flip-flop, at the R input of the fourth and the ninth gate and at the input of the fifth and the tence gate abut, with; the fourteenth gate and negated connected to the blocking outputs of the 'divider, wherein at the fourteenth gate nor the output of the third gate is applied.

Furthermore, the third flip-flop is connected via the twelfth gate and the second flip-flop via the thirteenth gate тіъ the second gate. Furthermore, the fifth gate is connected to the R input of the first flip-flop whose negated output is applied to the S-input of the third flip-flop and to the R-B input of the second flip-flop, wherein at another R input of the second flip-flop, the output of the eighth gate is applied.

Finally, the true output of the first flip-flop is via the sixth gate to the R inputs of the first and third flip-flops and negated to the eleventh gate and the negated output of the third flip-flop to the S input of the fourth flip-flop. Connected flops «

In an embodiment of the invention, a multiplexer is connected between the first and second divider. In this case, the multiplexer is also connected to the input of the first divider and two blocking outputs of the PLA and the output of the multiplexer is connected to the 7/1 switching IT.

But the output of the first divider is not connected to the IT switch.

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The oscillator frequency is determined by, external components. The frequency can be varied at least in the range 10: 1. Sin fine adjustment of the oscillator is possible via a connection of the oscillator. The oscillator delivers a temperature and voltage stable oscillation.

When a supply voltage is applied to the circuit, the oscillator begins to oscillate and continues to oscillate. Running the frequency to the setpoint is thus avoided when starting the function sequence.

When changing the oscillator frequency in the ratio of i0i1 the following time ranges result:

0.1 ... 1s

1 ... 10s 10 ... 100s

1 ... 10 min.

By reducing the oscillator frequency, these times can then be increased accordingly.

embodiment

The invention will be explained in more detail below using an exemplary embodiment. In the accompanying drawings show

Fig. 1: the inventive basic circuit arrangement of the timing circuit

Thirty. 2: the reset circuit for the flip-flops FIG. 3; the bounce suppression switching

Fig. 4-i the multiplexer for optimal substring testing

FIG. 5 'shows the circuit diagrams associated with the circuit and the coding table of the PLA with the inputs IA, IB, IC for the different functions.

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For a general explanation, it should be noted that the levels H = high = logic 1 and L = low = logical O mean. The coding allows 2 = 8 combinations according to the binary code. Of these, the serial numbers 1 and 8 (binary coding for 0 and 7) are not intended for applications, but reserved the circuit test not explained here.

Furthermore, gate is understood to be a NAND logic circuit.

The inventive programmable integratable timing circuit is shown in FIG.

In Singangsblock E is the input IS, at which a switch is applied, via an inverter 1 via two gates 2; 3 with two monoflops 32; 33 and connected via a negator 25 пііѣ a gate 26. The output of the monoflop 32 is connected to a bounce cancel circuit 31, which in turn is connected to the gates 2; 3 is connected.

Further, the monoflop having the control block, namely, the inverter 4 and the monoflop 33, which is also connected to the bounce suppressing circuit 31, is connected to a negator 5 through a gate 48. The negator 4 is with two gates 6; 7 and the negator with two gates 8; 9 connected. The inverters 7; 9 are connected to the S input and the inverters 6; 8 is connected to the • R input of a flip-flop 35. Sin oscillator ¹ YES is connected to the input of a pulse counter divider chain Z via a gate 36, to which the gate 26 and the flip-flop 35 are still connected. The pulse counting

Consists of a 2: 1 divider 37 _f two iO; 1 ~ dividers 38; 39 and a 6j1 divider 40, which are connected in series.

Between the dividers 37; 3β is a multiplexer 49, on which also the input of the divider 37 anli egt.

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Furthermore, the flip-flop 35 via a Uegator 10 with the blocking outputs of the divider 37; 33; 39; 4-0 connected. The outputs of the multiplexer 49 and the divider 33; 39; 40 are with the! Inputs OA; IF; OG; OD of a selector switch IT connected. The selector switch IT is connected to a gate 19 and via a monoflop 45 to a gate 47 to which a further output of the bounce suppression circuit 31 is applied.

The programming inputs IA; 13; IG are connected to the control block S via a PLA. Namely, the output A1 to the gate 26, the output A2 to the gate 48, the output A3 via a gate 12 to the gate 48, the output A4 via a gate 14 with the R-Singang a flip-flop 44, the Output A5 via a gate 15 with a flip-flop 42, the output A6 with the gates 6; 9 and the output A7 with the gates 7; connected. Furthermore, the output AS via a gate 16 and the output A9 via a gate 17 with a gate 18, at which the output is still applied to the A10 and the gate 19 to the output A11.

The gates 18; 19 are connected in output block A to a gate 20 which is connected to the output ORs and via an iTegator A6 to the output ORs. A reset circuit 50, to which the oscillator 34 is applied, is connected to the R-inputs of the flip-flops 42; 44, another flip-flop 43 and the S input of the flip-flop 35 and the bounce canceling circuit y \ .

The monoflop 32 is connected via an inverter 13 to the gate 15 and directly to the S-Singang of the flip-flop 44, which is connected to the gate 17.

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Furthermore, the gate ii> is connected to the H input of the flip-flop 43, which in turn is connected to the gate 16 and the 3 input of the flip-flop 35. The gate 7 is still connected to the R input and the gate 47 is connected to the 3-input of the flip-flop 42, its negated output Q2 * to the S input of the flip-flop 43 and the R input of the flip-flop 44 and its true output Q2 to the gate 15th and is connected via an inverter 11 to the gate 12. Finally, the PLA 41 with its Ausgärgen A12; АІЗ connected to the multiplexer 49 ·

The reset circuit is shown in FIG. It consists of a negator 80 and a gate 81, which are cross-coupled with each other. The supply voltage US is connected via a voltage divider H3; R1 to the input of the inverter 80 and via a voltage divider R4; R2 mi-G the input of the gate 81, where still the oscillator 34 is applied. The output of the gate 31 - input of the inverter 80 - is connected to the set inputs of the flip-flops 35; 42; 43; 44 connected.

After applying the supply voltage to the power supply circuit, this voltage is applied simultaneously to the reset circuit shown in Fig. 2 for the memory.

The task of this reset circuit is to secure when switching the Yersorgungsspannung, so even after an interruption of this, a setting of the circuit in always the same initial state. In this case, this circuit can process a slow and rapid voltage increase of 7ersorgungsspannung. By dimensioning the resistors of the reset circuit

R1 R2, R4 R3 and

R2 + R4 = R1 + R3,

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5 ¹ Ig. 2, it is forced that the potential at the input of the gate 81 is lower than that of the gate 80 and stays longer in the L level range. Therefore, the flip-flop composed of the inverter 80 and the gate 81 occupies the positions Q7 = L and q7 = H. This is possible because the oscillator 34- starts to oscillate delayed and its output at the beginning, because of its internal structure, Η potential.

In Fig. 3, the bounce is around; Erdrückungsschaltung 31 shown.

It consists of two flip-flops 58; 59. The monoflop is connected to the S-input of the flip-flop 59 and via an AND connection to the S input of the flip-flop 58. The gate 48 is connected to the R-input of the flip-flop 59 UEd connected via the IMD-V he connected to the S input of the flip-flop 58, whose output 0.5 via an oscillator 56 and a negator 22 with two gates 23; 24 and the S input of the flip-flop, to which the reset circuit 50 is connected, is connected. The output Q6 of the flip-flop 59 is connected to the gate 3 via the gate 24 and the output QS is connected to the gate 2 via the gate 23 ".

With the first closing of the start input IS, an L pulse is produced at the monoflop 32. With this, the two memory flip-flops 58; 59 set so that the outputs Q5; Q6 of the memory flip-flops 58; 59 H signal. Thus, the FF 58 releases the oscillator. The transition of the oscillator to L at the output are via negator 22, the gates 23 and 24 free. Since the flip-flop 59 has outputs Q6 = H and Q ^ = L, the gate 24 switches from H to L signal. This S-3 signal forces the gate 3 (Fig. 1)> on the output Η signal. Ss, the state is reached as if the closing contact via the gates 1; 2 and 3 Η potential generated at the output gate 3. Thus, can

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the contact at the start input IS open again, first bounce action, without the monoflop 33 can give an L-pulse.

The time for which the gate carries 3 Η potential at the output depends on the oscillator frequency. After the appropriately set bounce time, the output of the oscillator 56 returns from L to Η potential. Thus, the FF 58 is set to the position Q5 = L and q5 = H, the outputs of the gates 23, 24 aufge-level is imposed, so that the output of the gate 3 is able to follow the signal at the start input IS again.

When opening the contact on St art input IS of the func-tion process is similar, but that the monoflop 33 provides the triggering L-pulse and that at FF 59 at Q6 = L and Q6 * = K-3ignal. Eggs are forced onto the gate 2 as before the gate 3> <i & s H signal.

The multiplexer 49 consists of two inverters 27; 29, whose inputs to the divider 37 and the gate 36 and their outputs to the gates 28; 30 are connected. At the gates 28; 30 are still the outputs A13; A12 of the PLA 41. The gates 28; 30 are connected via an AND gate 51 to the input of the divider 38.

The first time domain output can be additionally connected to the supply voltage with a light-emitting diode including a series resistor and lights up intermittently. Thus, an optical monitoring of the working circuit is given. After reaching the delay time, this LED goes out and a second light-emitting diode is energized and can thus serve as an optical display for the achieved delay time Sndzustand.

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Description of the functions, according to FIG. 5: jTach. Applying the supply voltage, the following initial states are set at the memories inside the timing circuit and at external terminals; Memory: FF 35: 3 1 = L; FF 43: Q 3 = L

FF 42: Q 2 = H FF 44: Q 4 = L Q ~ 2 = L Q ~ 4 "= H

Connections: Relay output

OSs = H; Start input IS = Ξ; Uonoilop 32, 33 = H; Divider outputs = H;

Function 1 (pull-in delay 1) PLA outputs; A1 = L; A 7 = L

A2 = H A 8 = H

A3 = L A 9 = L

A4 = L AIO = H

A5 = L Д11 = L

Дб = H PIA inputs: IA = H

IB = L

IC = L

With the closing of the contact at the start input IS, an L-pulse is produced at the monoflop 32. This arrives at the FF 35 via the gates 4, b, whereby the output Q1 = H is obtained and the gate 36 is opened. Thus, the oscillator pulse of the oscillator 34 enters the divider chain 37 ... 40. With the first H-L edge of this pulse all divider outputs are brought from H to L level and there is created at the output of the monoflop 45, a new L-pulse. However, this does not come because of the signal of the driven by the acting bounce suppression circuit 31 gates 4-7: to 'Älrk

When one of the divider outputs OA, OB, OC or OD miT is connected; IT passes after appropriate number of pulses and bounce bounce elapsed time a H-L edge to the monostable 45, which can now deliver their L-pulse.

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This sets the FF 42 so that Q2 = L and Q2 = Η level. Subsequently, the FF 43 is also implemented; "via the gates 16, 18 and 20, the potential of the relay output ORs goes from Ξ to L level and at the same time the FF 43 converts the FF35 so that Q1 = L and GpT = Η-level. This closes again the crook 35 and the 'divider chain 37 - ·· 40 reaches its initial state «

If one opens .nun the contact at the start input IS, so arises at the monostable 33, an L-pulse, which resets the memory FF 42 and FF 43 in their initial positions. Damir ?, the relay output ORs, switched from L to Zi signal. Sin new trip cycle can begin. In Fig. J? is the function sequence with respect to the connections start input IS and relay output ORs drawn under 5 * 1, 50, 51, whereby from left to right allowed ilcdifikationen regarding the St; ar input IS and their effect on the relay output CRs can be seen.

Function 2 (pull-in delay 2) PLA outputs: A1 = H · A7 = L

A2 = H AS = Ξ

A3 = H A9 = L

A4 = L A10 = Ξ

A5 = L A11 = L

Аб = H PLA-length: IA = L ·

13 = H IC = L

The bouncing suppression is never described before. 3s, the temporal function after elapsed bounce suppression is shown below. This function works like the previously described function 1, as long as the contact at the input IS is longer than the set value

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Delay time remains closed, Fig. 5 · 2, 52, 53 "The closing of the Zontakt, it is the S - carton input IS is started as before the funktionsablauf 3s the FF 35 is set, open the gate 36 and the Divider 37 ··· 4-0 begins to operate The gate 12 is released by the Q2 ~ = L-level on the flip-flop 4-2 and by the coding on the PLA 41 and on opening of the Z-clock on the S ". carte input IS, the L-pulse of the 1-onoflops 33 is suppressed. In consequence.-Cann auca not; the flip-flop 35 is reset; become. The coding in the PLA 41 simultaneously enables the gate 26 and sets the monoflop 33; because of its behavior at Kont; akt open the output of the gate 25 to L level. As a result, the whole 35 is closed and the dividers 37 ··· 40 remain due to the absence of the pulse. JTach that the contact; at the start input IS closed again, open the Gafuer 36 and the divider 37 ... 40 continue the division sequence. Thus, the closing duration of the cosine is summed at the source input IS, as shown in Fig. 5 at 5x2, 52, 53; is.

is; the total delay time reached, switches; the Heiais output ORs from Ξ- to L-level. For this purpose, the flip-flop 42 is implemented via the ilonoflop 45 and therefore the monoflop 32 is released via the flip-flop 42. Now open the contact; at the start; input IS, so sets; the previously described L-pulse returns the memories, and also the divider chain 37 ... ^ O and brings; the output of the gate 3 ° back to Ξ level.

Function 3 (waste delay)

PLA outputs: A1 = L; A 7 = H

A2 = H A 3 = L

A3 = L A 9 = H

A4 = L A 10 = E

A5 = L A 11 = L Ao = L

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PLA-L ¹ ingange: ιλ - Ξ

13 = Ξ

IC = L

After closing the contact on the input of the input signal, "the pressure reduction is effective, and lionoflop 32 again provides the above-mentioned L-pulse, which succeeds the Ga +, V to the lip-flop without its state change. The same situation applies to the flip-flop 44 and the gates OR 17, 13, 20, the relay output ORs of Ξ- set to L level.

To the S ^- CaTi; this function is; depending on the opening of the contact to start input IS of importance. The monoflop 33 was running; its L-pulse, which via the C-atrers 5, 8 the flip-flop 35 unseuzu, the Gaader opens 3 °; the stages are working. The L-pulse of the Eonoflops ^ 5, which is triggered by the first Ξ-L edge of the divider stages, is uneffected by the Preliunterdrückungsschaltjung. Given the appropriate delay time, the L-pulse appears on Lionoflop's ervrdr-cerma3en, which converts the flip-flop Ц-2 , which also converts the flip-flops ^ -3 »44; become. The flip-flop 43 in turn controls the flip-flop 35, which brings the Garter 36 schlB-G and the divider stages 37 ... ^ O in the starting position.

Finally, the flip-flop - + 4 via the Gaü ~ er 17, 13, 20, the relay output ORs back into the E-level state. The graph is drawn in Fig. 5 "under 5 x 3" o4 and 65;

Function 4 (zip function)

PLA outputs: A1 = L; A 7 = L

A2 = L AS = L

A3 = L A 9 = H

A4 = L A10 = Ξ

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A3 = H A11 = L

Αδ = Ξ

PLA 3 inputs: IA = L

13 = L

IC = Ξ

In this function, the L-pulse generation of the monoflop 33 is prevented by the selected form of the Ilodierung. This is; It is irrelevant for the function flow how long the contact at the start input IS remains closed. The tilt time corresponds to the size of the set delay time.

When the contact is closed with strong input IS, the L-pulse of the llonoflops 32 sets the flip-flop 35; the gate is 3 ° open; and the divider stages 37 ··· 40 released to work. At the same time; the flip-flop 44 has been set and the relay output 03s is set to the L-level state. After the delay time has been set, the monoflop 45 again supplies an L-pulse, which reverses the flip-flops 42, 43 and resets the divider stages 37 ··· 4-0. The flip-flop 42 in turn controls the flip-flop 44 back and the Heiaisausgang OHs returns to the E-level state.

In Fig. 5 at p.4, 65,67,68 various cases of the functional sequence are drawn graphically.

Function 5 (wiping function) PLA outputs: A1 = L; A 7 = L

A2 - ? A 8 = L A3 = Yy A 9 = Ξ A4 - "H" A10 = H A5 - yy A11 = Yy A6 - 2 PLA inputs: IA = H 13 T - yy (541) IC = H

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Hit the streak of contact at the Soar input 13 -er et en again the llonoflop 32, the gaiter 4, 6, the flip-flop 35, the gate 36, the reed 37 ··· 40 in radio-ion.

3s, the conversion of the flip-flop 44 takes place, and via the gates 17, 13, 20 the helix becomes -a-гіз · П ^ Я all " ¹ *" - ^ дсгоі о ^ Ьгя ^ іт ¹ ·, ~ ja-r > ofctp Т_Т * пт) п "І с - ^ а с

Once again, Llonoflops 45 is intercepted, the ever-acting bounce-suppression breech is intercepted. Is the Sontaki; at the star input IS closed for a longer time than the set delay time tv, then divide the divisor on 37 · · · 40 ao over time; via the llonoflop 4-5 which converts the flip-flop 42; soft turn the flip-flop 43 and dami ": the flip-flop 35 controls;" Zs then sleeps after the g-atter jo and the ladder stages 37 ··· 40 are reset, on the flip-flop ^ Z Flip-Flop 4 ^ - back and the Heiaisausgang OHs obtained again H-Potentiai.

If the Zontakt is opened at the start input IS before the expiration of the set delay time tv, then it is interrupted, as shown by the diagram in FIG. 5 under 5.5, 70.

Function б (astable multivibrator)

PLA outputs: Δ1 = L; A 7 = L

A2 = H A 3 = H

A3 = L A 9 = L

A4 = H A10 = L

A5 = L АЛЛ = E

Ao = H? LA inputs: IA = L

IB = H

IC = E

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The astable mode of operation is: programmed so that the gate 1o at the output constantly .ΐ-level leads and the gate 19 is released.

With the background of the contact at the start; input IS yields; the Г-ionoflop 32 again the L-pulse putting the flip Ποό 35, the gate jS opens and cie lever stages 37 ··· 40 works lait. via the gate 19, the Heiaisausgang OHs follows the level of the respective divider output 37 or J, o or 39 or ^ O so, da3 a meandering pulse sequence of the Yerzögerungszeii set; tv eat eat. At the start of the input IS, the signal is sent to an arbitrary line, so that the oil-lip 35 can be readjusted, the L-pulse of the ion-bomb 33 is immediately reset, the gate ys locked, and the dividing steps 37. · ^ O resets; The P.elaisausgang OHs attained, 'H-level.

In Fig. 5 and 5 * 5, 71 * 72 the corresponding diagrams are drawn.

The LIuIt; iplexer in pig. ^ - be more of several gates 27 ... ЗО, 51. Are the PLA inputs IA = IB = IC = L and the PLA outputs A12 = H, АІЗ = L guide; the Gau-he also a Η signal. This prevents;

ΊΟ pulse from the divider 2: 1.37 in the subsequent divider stages 33 ··· ^ O can get. At the same time, it is achieved that the pulse of the oscillator 3 can be fed directly from the gate 36, Fig. 1 to the subsequent lower stage 37.

This multiplexer allows the oscillator pulse to be processed in an equilateral manner by both divider stages. Thus it is possible to increase the test time of the

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sanrcen to reduce the rope chain 37 ··· ^ O.

The tap of the output of the divider chain 37 takes place at the output OA.

When the supply voltage is applied to the circuit, the oscillator begins to vibrate immediately and then oscillates constantly iisizer. There are run-in effects; it not.

3In changing the oscillator frequency; in the ratio of 10: 1, the following zones are covered over: 0.1 ... 1s 1.0 ... 10s 10 ... 100s and 1 ... 10 min.

If the oscillation frequency is further reduced, the lines are correspondingly larger.

Claims (3)

-22- 2Q5438 Invention claim A programmable integration time control circuit having a large variable delay time and a plurality of timing functions, the timing circuit comprising a bounce-ringing voice block, a continuously oscillating oscillator, a pulse counting sub-chain with a selector switch, a reset-reset control block and an output block having power gates, characterized by - That the output of an AiTO gate (82) of the bounce suppression (31) ini input block (3) to a first input of a gate (4-7) of the Impulszählteilerkette (Z) whose output with the S-Singang a flip-? lops (42) connected in the control block (3), is guided, in that the respective output of the dividers (37, 38, 39, 40) of the pulse counter-divider chain (Z) selected via the selector switch (IT) is connected, on the one hand, via a monoflop (45) to the second input of the gatherer (47 ), on the other hand connected to an input of a gate (19) of the control block (S), - That the outputs of the gates (18, 19) of the control block (S) in the output block (A) by a gate (20) are linked, - That the reset circuit (50) is connected to the R-Singang a flip-flop (58) of the bounce suppression (31), - That the input block (S) with the control block (S) via the output of a bTegators (25) having an input of a gate (26) via the output of a monoflop (32) on the one hand to the S input of a flip-flop (44), on the other hand negated with two gates (6, 7) and further negated with a gate (15), as well as the output of another monoflop (33) via a gate (48) on the one hand with a gate (14) negated on the other hand another two gates (8; 9) is connected, -23- 205438 - That programming inputs (IA: 13: IC) via true and negated outputs (A1 ... .DELTA.7) of a PLA (41) via a gate (12) with the gates (48) and with; the gates (26; 43; 14; 15) and the gates (6; 7; 0; 9) are connected and connections from the Yerriegelungsausgängen (A8 ... A11) of the PLA (41) to the respective control input of the gates (16 ; 17; 18; 19) in the control block (S). 2. Time your circuit by point; 1, characterized in that in the control block (S) of the oscillator (34) on the one hand with the Rücksetζschaltung (50) and on the other hand via a gate (36) to the first divider (37) of the Impulszählteilerkette (Z) is connected, in that the reset circuit (50) is connected to the R-3 input of the flip-flops (42; 43; 44) and to the 3-input of the flip-flop (35) , - That another flip-flop (35) »at the R-Zingang the gates (6; 8) and at its S input, the gates (7; 9) are present, with the jTA2TI> gate (36) and negated with the blocking outputs of the dividers (37; 38; 39; 40) are connected, wherein the output of the gate (26) is still applied to the UAITD gate (36), - That a flip-flop (43) via the gate (16) and the flip-flop (44) via the gate (17) to the gate (18) is connected, - That further the gate (7) is connected to the R input of the flip-flop (42) whose negated Ausgarg at the S input of the flip-flop (43) and at the R-Singang of the flip-flop (44 ) is applied, wherein at еіпэт further R input of the flip-flop (44), the output of the gate (14) is connected, - That the output (0,2) of the flip-flop (42) via the gate (15) with the R inputs of the flip-flops ("-2; 43) as negated connected to the gate (12) i =; ~ and the negated output of the flip-flop (43) is connected to the S input of the flip-flop (35). 205 ^ 38 3- With this circuit according to point 1 »characterized by., Da3 between the first and second divisors
(37; 38) sio- multiplexer (49) is connected, that the multiplexer continues to be connected to the input of the Теііегь (37) and two 31ockierausgängen (A12; A13) ^ he PLA and that finally the output of the multiplexer (49) with the 'number switch (IT) is connected. For this ... J [L $ a drawings